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##==========================================================================
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##
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## hal_var_bank.inc
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##
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## SH support code for variants using register banks
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##
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##==========================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##==========================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): jskov
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## Contributors: jskov
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## Date: 2002-01-11
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## Purpose: SH support code for variants using register banks
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##
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######DESCRIPTIONEND####
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##
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##==========================================================================
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#---------------------------------------------------------------------------
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# The models with banked registers jump directly to code without storing
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# anything on the stack. Instead, the CPU switches to use banked registers
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# leaving initial saving of state to the VSRs.
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# reset 0xa0000000
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# other exceptions VBR+0x100
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# tlb miss VBR+0x400
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# interrupts VBR+0x600
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#===========================================================================
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# Reset code must be PC relative so it can be executed out of the shadow
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# area during startup. Not until after hal_hardware_init can the system
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# be expected to provide the proper address space (at that time we
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# jump to the VMA base of the code).
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.org 0x000
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FUNC_START(_reset)
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mov.l $_reset_platform,r0
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jmp @r0
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nop
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# Note: this is the unmapped, shadow address of the start of code
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# Sadly, it is too far to just branch to.
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.align 2
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$_reset_platform:
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#ifdef CYG_HAL_STARTUP_RAM
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.long CYG_LABEL_DEFN(_reset_platform)
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#elif defined(CYG_HAL_STARTUP_ROMRAM)
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// Uncached "shadow" address but adjusted for VMA/LMA differences
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.long __reset_platform+0x20000000-CYGMEM_REGION_ram+CYGMEM_REGION_rom
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#else
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// Uncached "shadow" address
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.long CYG_LABEL_DEFN(_reset_platform)+0x20000000
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#endif
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#---------------------------------------------------------------------------
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# Exception entry
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.org 0x100
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__exception:
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#if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
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mov #1,r7
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#endif
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mov.l $nCYGARC_REG_EXCEVT2,r1
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mov.l @r1,r1
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shlr2 r1
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shlr r1 ! divide cause by 0x08
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mov.l $hal_vsr_table2,r0
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mov.l @(r0,r1),r1
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jmp @r1
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nop
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.align 2
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SYM_PTR_REFn(hal_vsr_table,2)
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#---------------------------------------------------------------------------
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# TLB miss entry
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.org 0x400
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__tlb_miss:
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#if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
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mov #2,r7
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#endif
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mov.l $nCYGARC_REG_EXCEVT2,r1
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mov.l @r1,r1
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shlr2 r1
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shlr r1 ! divide cause by 0x08
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mov.l $hal_vsr_table3,r0
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mov.l @(r0,r1),r1
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jmp @r1
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nop
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.align 2
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SYM_PTR_REFn(hal_vsr_table,3)
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$nCYGARC_REG_EXCEVT2:
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.long CYGARC_REG_EXCEVT
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#---------------------------------------------------------------------------
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# Interrupt entry
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.org 0x600
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__interrupt:
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#ifdef CYGHWR_HAL_SH_IRQ_HANDLE_SPURIOUS_INTERRUPTS
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# A spurious interrupt with INTEVT=0 may be caused by
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# clearing of BL. Those interrupts need to be ignored.
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mov.l 1f,r0
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mov.l @r0,r0
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cmp/eq #0,r0
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bf 2f
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rte
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nop
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.align 2
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1: .long CYGARC_REG_INTEVT
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2:
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#endif
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#if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
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mov #3,r7
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#endif
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mov.l $hal_vsr_table_int,r1
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mov.l @r1,r1
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jmp @r1
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nop
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.align 2
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$hal_vsr_table_int:
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.long CYG_LABEL_DEFN(hal_vsr_table)+CYGNUM_HAL_VECTOR_INTERRUPT*4
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##============================================================================
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## Macros for saving/restoring register state on an exception.
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#---------------------------------------------------------------------------
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## Save registers on exception:
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## At entry:
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## r15 is location to be stored to
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## r0 is the available scratch register
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## At exit:
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## r7 is the vector #
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## all other registers (except sp) are available
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.macro hal_cpu_save_regs
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# We come here with all register containing their
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# pre-exception values except:
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# r0_b-r7_b = saved r0-r7
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# r7 = vector #
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# spc = saved pc
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# ssr = saved sr
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# Save away some registers
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mov r15,r1 ! entry sp
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#ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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add #-12,r15 ! Space for cause, gbr, and vbr
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#else
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add #-4,r15 ! Space for cause
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stc gbr,r0 ! GBR
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mov.l r0,@-r15
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stc vbr,r0 ! VBR
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mov.l r0,@-r15
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#endif
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stc spc,r0
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mov.l r0,@-r15 ! PC
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stc ssr,r0
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mov.l r0,@-r15 ! SR
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sts.l pr,@-r15 ! PR
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sts.l mach,@-r15 ! mach
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sts.l macl,@-r15 ! macl
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mov.l r1,@-r15 ! entry sp
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mov.l r14,@-r15 ! r14-r0
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mov.l r13,@-r15
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mov.l r12,@-r15
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mov.l r11,@-r15
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mov.l r10,@-r15
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mov.l r9,@-r15
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mov.l r8,@-r15
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stc.l r7_bank,@-r15
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stc.l r6_bank,@-r15
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stc.l r5_bank,@-r15
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stc.l r4_bank,@-r15
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stc.l r3_bank,@-r15
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stc.l r2_bank,@-r15
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stc.l r1_bank,@-r15
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stc.l r0_bank,@-r15
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# After setting the SR it will be possible to use breakpoints.
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mov.l 1f,r1
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ldc r1,sr
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bra 2f
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nop
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.align 2
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1: .long CYG_SR
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# ------------------------------------------------------------
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# Register bank has changed now.
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2:
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.endm
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# No additional magic needed. hal_cpu_save_regs does it all.
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.macro hal_exception_entry_extras
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.endm
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.macro hal_interrupt_entry_extras
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.endm
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#---------------------------------------------------------------------------
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## Restore registers after exception:
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## At entry:
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## r15 is location to be loaded from
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## all other registers (except sp) are available
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## At exit:
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## Returns to interrupted code
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.macro hal_cpu_restore_regs_return
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# Disable interrupts and switch register bank during the restore
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# operation
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mov.l 1f,r1
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ldc r1,sr
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# ------------------------------------------------------------
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# Register bank has changed now.
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#
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# Single step debugging becomes impossible after this point!
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#
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mov r15,r0
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ldc.l @r0+,r0_bank
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ldc.l @r0+,r1_bank
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ldc.l @r0+,r2_bank
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ldc.l @r0+,r3_bank
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ldc.l @r0+,r4_bank
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ldc.l @r0+,r5_bank
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ldc.l @r0+,r6_bank
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ldc.l @r0+,r7_bank
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mov.l @r0+,r8
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mov.l @r0+,r9
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mov.l @r0+,r10
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mov.l @r0+,r11
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mov.l @r0+,r12
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mov.l @r0+,r13
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mov.l @r0+,r14
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mov.l @r0+,r15 ! return SP
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lds.l @r0+,macl ! macl
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lds.l @r0+,mach ! mach
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lds.l @r0+,pr ! PR
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mov.l @r0+,r2
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ldc r2,ssr ! return SR
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mov.l @r0+,r2
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ldc r2,spc ! return PC
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#ifndef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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mov.l @r0+,r2
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ldc r2,vbr ! return VBR
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mov.l @r0+,r2
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ldc r2,gbr ! return GBR
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#endif
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rte
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nop
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.align 2
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1: .long CYG_SR_BANK1
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.endm
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#---------------------------------------------------------------------------
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# Translate cause of exception to a vector number
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.macro hal_exception_translate
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mov.l 1f,r0
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mov.l @r0,r4
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mov #-5,r0 ! divide cause by 0x20
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shld r0,r4
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mov #CYGARC_SHREG_EVENT,r0
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bra 2f
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mov.l r4,@(r0,r15) ! store decoded vector number back
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.align 2
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1: .long CYGARC_REG_EXCEVT
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2:
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.endm
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#---------------------------------------------------------------------------
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# end of hal_var_bank.inc
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