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##==========================================================================
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##
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##      hal_var_sp.inc
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##
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##      SH support code for variants using stack at exception entry
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##
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##==========================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##==========================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s):    jskov
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## Contributors: jskov
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## Date:         2002-01-11
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## Purpose:      SH support code for variants using stack at exception entry
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##
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######DESCRIPTIONEND####
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##
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##==========================================================================
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#include 
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#include 
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## This is the address of the reset entry
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#if defined(CYG_HAL_STARTUP_RAM) || defined(CYGARC_SH_MOD_CAC_NO_WINDOWS)
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        // No translation if RAM startup, or if the variant does not
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        // have cached/non-cached windows in the address space.
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# define _RESET_ENTRY CYG_LABEL_DEFN(_reset_platform)
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#elif defined(CYG_HAL_STARTUP_ROMRAM)
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        // Uncached "shadow" address but adjusted for VMA/LMA differences
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# define _RESET_ENTRY __reset_platform+0x20000000-CYGMEM_REGION_ram+CYGMEM_REGION_rom
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#else
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        // Uncached "shadow" address
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# define _RESET_ENTRY CYG_LABEL_DEFN(_reset_platform)+0x20000000
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#endif
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#if !defined(CYG_HAL_STARTUP_RAM) || !defined(CYGSEM_HAL_USE_ROM_MONITOR)
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## This is the table of HW_EXC_ENTRY pointers fetched from by the CPU
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## on an exception. They point to pre-VSR handlers (below) which prep
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## R0 with the vector number (which, AFAICT, there''s no other way
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## to find) before calling the VSR.
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## Note that this takes up a massive 4KiB so it should only be included
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## when really needed (that is, when not relying on RedBoot to provide
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## it).
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        .align   2
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FUNC_START(_HW_EXC_ENTRY_TABLE)
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# Power-on reset entry address and stack
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        .long _RESET_ENTRY
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        .long 0
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# Manual reset entry address and stack
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        .long _RESET_ENTRY
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        .long 0
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# All the other vectors
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        .set    vecno, 0
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        .rept   (256-4)
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        .long   $vectors_code+(vecno)*16
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        .set    vecno, vecno+1
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        .endr
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## The piece of code pointed to by the HW_EXC table. Each vector
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## has such a piece of code, which saves R0 on the stack, fetches
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## the VSR pointer and loads the vector number into R0.
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##
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## Note the three variants:
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##  exception_vector:      maps the HW_EXC vector to the same eCos HAL_VECTOR
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##  exception_vector_trap: maps the HW_EXC vector to the eCos HAL_VECTOR_TRAP
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##  exception_vector_int:  maps the HW_EXC vector to the eCos HAL_VECTOR_INTERRUPT
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##
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## With these we translate the SH2 vector style exceptions to something more
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## like the SH3/SH4 style:
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##
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##  HW vectors         eCos vectors
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##    00-31                0-31  Various exceptions
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##    32-63                32    TRAP
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##    64-255               33    Interrupt
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##                         34-63 Free for application
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##
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## This allows the VSR table to be reduced to 1/4 of the size, and eases
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## code sharing with the SH3/SH4 variants without any real loss of power.
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##
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        .macro exception_vector vec
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        mov.l r0,@-r15
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        mov.l 1f,r0
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        mov.l @r0,r0
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        jmp   @r0
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         mov  #\vec,r0
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        .align 2
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1:      .long CYG_LABEL_DEFN(hal_vsr_table)+4*\vec
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        .endm
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125
        .macro exception_vector_trap vec
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        mov.l r0,@-r15
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        mov.l 1f,r0
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        mov.l @r0,r0
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        jmp   @r0
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         mov  #\vec,r0
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        .align 2
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1:      .long CYG_LABEL_DEFN(hal_vsr_table)+4*CYGNUM_HAL_VECTOR_TRAP
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        .endm
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135
        # The comment argument is not used for anything. It's just there
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        # to provide callers a slot for comments (which is not otherwise
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        # possible when doing multiple invocations on the same line).
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        .macro exception_vector_int vec,comment
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        mov.l r0,@-r15
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        mov.l 1f,r0
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        mov.l @r0,r0
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        jmp   @r0
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         mov  #\vec,r0
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        .align 2
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1:      .long CYG_LABEL_DEFN(hal_vsr_table)+4*CYGNUM_HAL_VECTOR_INTERRUPT
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        .endm
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148
# And their entry points
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$vectors_code:
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        exception_vector 4              // general illegal instr
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        exception_vector 5              // reserved
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        exception_vector 6              // slot illegal instr
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        exception_vector 7              // reserved
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        exception_vector 8              // reserved
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        exception_vector 9              // CPU address error
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        exception_vector 10             // DMA address error
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        exception_vector_int CYGNUM_HAL_INTERRUPT_NMI // NMI
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        exception_vector 12             // User Break
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        exception_vector 13             // H-UDI
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        .set    vecno, 14
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        .rept   (32-14)
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        exception_vector vecno          // reserved
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        .set    vecno, vecno+1
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        .endr
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        .set    vecno, 32
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        .rept   (64-32)
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        exception_vector_trap vecno     // Trap
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        .set    vecno, vecno+1
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        .endr
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#ifdef CYGHWR_HAL_SH_SH2_CUSTOM_INTERRUPT_LAYOUT
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        # Some variants may have a very sparsely populated
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        # vector table (7044 is an example) which results
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        # in many unused entries in various interrupt tables.
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        # To reduce bloat, these may define a custom
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        # layout of these interrupt decoders - the code
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        # is to be found in var_intr.h since it's very
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        # tightly coupled with the interrupt vectors.
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        CYGHWR_HAL_SH_SH2_CUSTOM_INTERRUPT_LAYOUT
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#else
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        # Note that there''s an entry for vector 0 (NMI) here again
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        # to avoid having to make hal_interrupt_set_vectors()
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        # adjust for this off-by-one discrepancy.
184
        .set    vecno, CYGNUM_HAL_INTERRUPT_NMI
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        .rept   (256-64)
186
        exception_vector_int vecno      // interrupts
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        .set    vecno, vecno+1
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        .endr
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#endif // CYGHWR_HAL_SH_SH2_CUSTOM_INTERRUPT_LAYOUT
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#endif // !defined(CYG_HAL_STARTUP_RAM) || !defined(CYGSEM_HAL_USE_ROM_MONITOR)
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## For RAM startups, provide a convenient jump to the application start
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## at the very start of the image.
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FUNC_START(_reset)
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        mov.l   1f,r0
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        jmp     @r0
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         nop
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        .align  2
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1:      .long _RESET_ENTRY
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##-----------------------------------------------------------------------------
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## Macros for saving/restoring register state on an exception. These
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## are generic for all variants, so be careful to not make assumptions.
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207
## r15 is location stored to/loaded from
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## r0  is the available scratch register
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## At exit:
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## r7  is the vector #
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## all other registers (except sp) are available
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214
## Furthermore, stack content at this point is
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        #-- original SP address
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        # pre-exception SR
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        # pre-exception PC
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        # pre-exception r0
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        #-- present SP address
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        .macro hal_cpu_save_regs
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        mov.l   r0,@-sp                 ! vector number
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#ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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        add     #-8,sp                  ! Space for gbr, and vbr
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#else
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        stc     gbr,r0                  ! GBR
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        mov.l   r0,@-sp
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        stc     vbr,r0                  ! VBR
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        mov.l   r0,@-sp
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#endif
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        add     #-8,sp                  ! Space for entry PC and SR
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#if 0 // FIXME
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        stc.l   re,@-sp                 ! RE
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        stc.l   rs,@-sp                 ! RS
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        stc.l   mod,@-sp                ! MOD
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#endif
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        sts.l   pr,@-sp                 ! PR
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        sts.l   mach,@-sp               ! mach
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        sts.l   macl,@-sp               ! macl
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        add     #-4,sp                  ! Space for entry sp
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        mov.l   r14,@-sp                ! r14-r0
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        mov.l   r13,@-sp
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        mov.l   r12,@-sp
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        mov.l   r11,@-sp
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        mov.l   r10,@-sp
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        mov.l   r9,@-sp
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        mov.l   r8,@-sp
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        mov.l   r7,@-sp
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        mov.l   r6,@-sp
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        mov.l   r5,@-sp
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        mov.l   r4,@-sp
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        mov.l   r3,@-sp
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        mov.l   r2,@-sp
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        mov.l   r1,@-sp
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        add     #-4,sp                  ! space for r0
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        ! Compute location of pre-exception r0 and move
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        ! data from above structure into the structure
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        mov     sp,r1
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        add     #CYGARC_SH_EXCEPTION_SIZE,r1
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        mov.l   @r1+,r0                 ! pre-exception R0
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        mov.l   r0,@(CYGARC_SHREG_REGS,sp)
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        mov.l   @r1+,r2                 ! pre-exception PC
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        mov     #CYGARC_SHREG_PC,r0
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        mov.l   r2,@(r0,sp)
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        mov.l   @r1+,r2                 ! pre-exception SR
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        mov     #CYGARC_SHREG_SR,r0
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        mov.l   r2,@(r0,sp)
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        mov     #CYGARC_SHREG_SP,r0
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        mov.l   r1,@(r0,sp)             ! pre-exception SP
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        ! Load up the vector number
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        mov     #CYGARC_SHREG_EVENT,r0
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        mov.l   @(r0,sp),r7
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        .endm
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279
        .macro hal_exception_entry_extras
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        # Disable interrupts before anything else
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        mov.l   1f,r0
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        ldc     r0,sr
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        bra     2f
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         nop
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        .align  2
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1:      .long   CYG_SR
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2:
288
        .endm
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290
        # No additional magic needed. hal_cpu_save_regs does it all.
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        .macro hal_interrupt_entry_extras
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        .endm
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#---------------------------------------------------------------------------
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## Restore registers after exception:
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## At entry:
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## r15 is location to be loaded from
298
## all other registers (except sp) are available
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300
## At exit:
301
##  Returns to interrupted code
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303
        .macro hal_cpu_restore_regs_return
304
        ! Disable interrupts during the restore operation
305
        mov.l   1f,r1
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        ldc     r1,sr
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308
        ! Move R0/PC/SR values from register structure onto the stack where
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        ! they''ll be popped from on return. Note that this is the SP as
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        ! set in the register frame! (otherwise GDB would be unable to change
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        ! SP).
312
        mov.l   @(CYGARC_SHREG_SP,sp),r0
313
        mov     r0,r1
314
        add     #-12,r1
315
        mov.l   @(CYGARC_SHREG_REGS,sp),r0
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        mov.l   r0,@r1                  ! pre-exception R0
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        mov     #CYGARC_SHREG_PC,r0
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        mov.l   @(r0,sp),r2
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        mov.l   r2,@(4,r1)              ! pre-exception PC
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        mov     #CYGARC_SHREG_SR,r0
321
        mov.l   @(r0,sp),r2
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        mov.l   r2,@(8,r1)              ! pre-exception SR
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324
        ! Load up registers
325
        add     #4,sp                   ! skip r0
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        mov.l   @sp+,r1
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        mov.l   @sp+,r2
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        mov.l   @sp+,r3
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        mov.l   @sp+,r4
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        mov.l   @sp+,r5
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        mov.l   @sp+,r6
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        mov.l   @sp+,r7
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        mov.l   @sp+,r8
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        mov.l   @sp+,r9
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        mov.l   @sp+,r10
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        mov.l   @sp+,r11
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        mov.l   @sp+,r12
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        mov.l   @sp+,r13
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        mov.l   @sp+,r14
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        add     #4,sp                   ! skip SP
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342
        lds.l   @sp+,macl               ! macl
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        lds.l   @sp+,mach               ! mach
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        lds.l   @sp+,pr                 ! PR
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346
#if 0 // FIXME - also change SP adjustment below!
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        ldc.l   @sp+,re                 ! RE
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        ldc.l   @sp+,rs                 ! RS
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        ldc.l   @sp+,mod                ! MOD
350
#endif
351
        add     #8,sp                   ! skip sr and pc
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353
#ifndef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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        mov.l   @sp+,r0
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        ldc     r0,vbr                  ! return VBR
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        mov.l   @sp+,r0
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        ldc     r0,gbr                  ! return GBR
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#else
359
        add     #8,sp                   ! skip VBR+GBR
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#endif
361
 
362
        add     #-8*4,sp                ! get to new SP
363
        mov.l   @sp,sp
364
        add     #-12,sp                 ! get to exception state + saved r0
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366
        mov.l   @sp+,r0                 ! pre-exception r0
367
        rte
368
         nop
369
        .align  2
370
1:      .long   CYG_SR
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        .endm
372
 
373
#---------------------------------------------------------------------------
374
# Translate cause of exception to a vector number
375
        .macro hal_exception_translate
376
        .endm
377
 
378
#---------------------------------------------------------------------------
379
# end of hal_var_sp.inc

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