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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sh/] [arch/] [v2_0/] [src/] [context.S] - Blame information for rev 174

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##=============================================================================
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##
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##      context.S
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##
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##      SH context switch code
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s):   jskov
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## Contributors:jskov
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## Date:        1999-05-01
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## Purpose:     SH context switch code
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## Description: This file contains implementations of the thread context
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##              switch routines. It also contains the longjmp() and setjmp()
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##              routines.
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include 
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#include 
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#include 
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#include            // CYG_LABEL_DEFN
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#------------------------------------------------------------------------------
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# Register allocation for the Hitachi calling convention:
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#
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#       r0              arg return
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#       r1..r3          scratch
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#       r4..r7          args in
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#       r8..r13         call saved
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#       r14             frame pointer/call saved
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#       r15             stack pointer
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#       ap              arg pointer (doesn''t really exist, always eliminated)
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#       pr              subroutine return address
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#       t               t bit
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#       mach            multiply/accumulate result, high part
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#       macl            multiply/accumulate result, low part.
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#       fpul            fp/int communication register
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#       rap             return address pointer register
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#       fr0             fp arg return
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#       fr1..fr3        scratch floating point registers
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#       fr4..fr11       fp args in
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#       fr12..fr15      call saved floating point registers
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# hal_thread_switch_context
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# Switch thread contexts
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# R4 = address of sp of next thread to execute
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# R5 = address of sp save location of current thread
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# Need to save r8-r13, r14 (fp), r15 (sp), pr, mach, macl
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FUNC_START(hal_thread_switch_context)
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        mov     r15, r0                 ! R0 = saved stack pointer
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        sts.l   pr,@-r15                ! save caller in PC slot so it looks
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                                        ! sensible when GDB examines it
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        stc     sr,r1
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        mov.l   r1,@-r15
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        sts.l   pr,@-r15                ! return address
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        sts.l   macl,@-r15              ! macl
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        sts.l   mach,@-r15              ! mach
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        mov.l   r0,@-r15                ! saved r15 (entry sp)
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        mov.l   r14,@-r15               ! r14-r0
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        mov.l   r13,@-r15
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        mov.l   r12,@-r15
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        mov.l   r11,@-r15
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        mov.l   r10,@-r15
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        mov.l   r9,@-r15
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        mov.l   r8,@-r15
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        mov.l   r7,@-r15
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        mov.l   r6,@-r15
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        mov.l   r5,@-r15
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        mov.l   r4,@-r15
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        mov.l   r3,@-r15
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        mov.l   r2,@-r15
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        mov.l   r1,@-r15
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        mov.l   r0,@-r15
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        mov.l   r15,@r5                 ! save SP into save location
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        # Now load the destination thread by dropping through
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        # to hal_thread_load_context
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#------------------------------------------------------------------------------
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# hal_thread_load_context
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# Load thread context
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# R4 = address of sp of next thread to execute
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# Note that this function is also the second half of hal_thread_switch_context
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# and is simply dropped into from it.
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FUNC_START(hal_thread_load_context)
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        mov.l   @r4,r0
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        add     #4+4,r0                 ! skip r0 and r1
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        !mov.l   @r0+,r0
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        !mov.l   @r0+,r1
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        mov.l   @r0+,r2
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        mov.l   @r0+,r3
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        mov.l   @r0+,r4
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        mov.l   @r0+,r5
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        mov.l   @r0+,r6
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        mov.l   @r0+,r7
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        mov.l   @r0+,r8
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        mov.l   @r0+,r9
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        mov.l   @r0+,r10
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        mov.l   @r0+,r11
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        mov.l   @r0+,r12
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        mov.l   @r0+,r13
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        mov.l   @r0+,r14
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        mov.l   @r0+,r3                 ! New SP.
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        lds.l   @r0+,mach               ! mach
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        lds.l   @r0+,macl               ! macl
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        lds.l   @r0+,pr                 ! pr
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        mov     r3,r15                  ! update stack pointer
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        mov.l   @r0+,r2                 ! SR
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        hal_cpu_int_merge r2,r0,r1      ! restore interrupt state
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        rts                             ! and return
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         nop
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#------------------------------------------------------------------------------
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# HAL longjmp, setjmp implementations
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# hal_setjmp saves only to callee save registers r8-r13, r14(fp), r15(sp)
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# and pr into buffer supplied in r4[arg0]
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FUNC_START(hal_setjmp)
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        mov.l   r15,@(CYGARC_JMPBUF_SP,r4)
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        sts     pr,r0
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        mov.l   r0,@(CYGARC_JMPBUF_PR,r4)
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        mov.l   r8,@(CYGARC_JMPBUF_R8,r4)
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        mov.l   r9,@(CYGARC_JMPBUF_R9,r4)
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        mov.l   r10,@(CYGARC_JMPBUF_R10,r4)
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        mov.l   r11,@(CYGARC_JMPBUF_R11,r4)
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        mov.l   r12,@(CYGARC_JMPBUF_R12,r4)
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        mov.l   r13,@(CYGARC_JMPBUF_R13,r4)
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        mov.l   r14,@(CYGARC_JMPBUF_R14,r4)
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        mov    #0,r0            ! return 0
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        rts
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         nop
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# hal_longjmp loads state from r4[arg0] and returns
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# argument supplied in r5[arg1]
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FUNC_START(hal_longjmp)
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        mov.l   @(CYGARC_JMPBUF_SP,r4),r15
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        mov.l   @(CYGARC_JMPBUF_PR,r4),r0
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        lds     r0,pr
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        mov.l   @(CYGARC_JMPBUF_R8,r4),r8
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        mov.l   @(CYGARC_JMPBUF_R9,r4),r9
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        mov.l   @(CYGARC_JMPBUF_R10,r4),r10
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        mov.l   @(CYGARC_JMPBUF_R11,r4),r11
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        mov.l   @(CYGARC_JMPBUF_R12,r4),r12
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        mov.l   @(CYGARC_JMPBUF_R13,r4),r13
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        mov.l   @(CYGARC_JMPBUF_R14,r4),r14
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        mov     r5,r0
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        rts
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         nop
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#------------------------------------------------------------------------------
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# end of context.S

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