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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sh/] [cq7750/] [v2_0/] [cdl/] [hal_sh_sh7750_cq7750.cdl] - Blame information for rev 27

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# ====================================================================
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#
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#      hal_sh_sh7750_cq7750.cdl
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#
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#      CQ7750 board HAL package configuration data
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#
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# ====================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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# ====================================================================
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######DESCRIPTIONBEGIN####
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#
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# Author(s):      jskov
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# Original data:  jskov
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# Contributors:   Ryozaburo Suzuki
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# Date:           1999-10-29
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#
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#####DESCRIPTIONEND####
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#
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# ====================================================================
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cdl_package CYGPKG_HAL_SH_SH7750_CQ7750 {
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    display       "CqREEK SH7750 board"
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    parent        CYGPKG_HAL_SH
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    requires      CYGPKG_HAL_SH_7750
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    define_header hal_sh_sh7750_cq7750.h
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    include_dir   cyg/hal
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    description   "
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        The cq HAL package provides the support needed to run
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        eCos on a CqREEK SH7750 board."
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    compile       hal_diag.c plf_misc.c
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    implements    CYGINT_HAL_DEBUG_GDB_STUBS
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    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
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    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
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    implements    CYGINT_HAL_SH_PLF_BIGENDIAN_DEFAULT
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    define_proc {
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        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   "
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        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H "
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        puts $::cdl_header "#define CYGNUM_HAL_SH_SH4_SCIF_PORTS 1"
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        puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x08000000"
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        puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x08000100"
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    }
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    cdl_component CYG_HAL_STARTUP {
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        display       "Startup type"
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        flavor        data
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        legal_values  {"RAM" "ROM"}
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        default_value {"RAM"}
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        no_define
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        define -file system.h CYG_HAL_STARTUP
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        description   "
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           When targetting the CQ7750 board it is possible to build
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           the system for either RAM bootstrap or ROM bootstrap.
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           RAM bootstrap generally requires that the board
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           is equipped with ROMs containing a suitable ROM monitor or
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           equivalent software that allows GDB to download the eCos
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           application on to the board. The ROM bootstrap typically
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           requires that the eCos application be blown into EPROMs or
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           equivalent technology."
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    }
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    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
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        display      "Number of communication channels on the board"
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        flavor       data
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        calculated   1
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    }
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    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
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        display          "Debug serial port"
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        flavor data
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        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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        default_value    0
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        description      "
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           The CQ/7750 board has only one serial port. This option
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           chooses which port will be used to connect to a host
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           running GDB."
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    }
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    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
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        display          "Diagnostic serial port"
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        flavor data
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        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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        default_value    0
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        description      "
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           The CQ/7750 board has only one serial port.  This option
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           chooses which port will be used for diagnostic output."
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    }
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    cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {
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        display          "SH on-chip platform clock controls"
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        description      "
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            The various clocks used by the system are derived from
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            these options."
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        flavor        none
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        no_define
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        cdl_option CYGHWR_HAL_SH_OOC_XTAL {
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            display          "SH clock crystal"
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            flavor           data
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            legal_values     9000000 to 66000000
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            default_value    33333333
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            no_define
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            description      "
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                This option specifies the frequency of the crystal all
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                other clocks are derived from."
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        }
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        cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {
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            display          "SH clock PLL circuit 1"
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            flavor           data
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            default_value    6
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            legal_values     { 0 6 }
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            description      "
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                This selects the multiplication factor provided by
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                PLL1."
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        }
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        cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {
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            display          "SH clock PLL circuit 2"
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            flavor           data
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            default_value    1
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            legal_values     { 0 1 }
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            description      "
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                This selects the multiplication factor provided by
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                PLL2. If PLL2 is disabled this option should
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                be set to zero."
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        }
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        cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 {
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            display          "SH clock first clock divider"
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            flavor           data
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            legal_values     { 1 2 }
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            default_value    1
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            no_define
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            description      "
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                First stage clock divider according to the mode (MD0..2).
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                Set 2 for mode 2 and 4, otherwise set 1."
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        }
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        cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_IFC {
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            display          "SH CPU clock divider"
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            flavor           data
178
            default_value    1
179
            legal_values     { 1 2 3 4 6 8 }
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            description      "
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                This divider option affects the CPU clock."
182
        }
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        cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_BFC {
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            display          "SH bus clock divider"
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            flavor           data
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            default_value    3
188
            legal_values     { 1 2 3 4 6 8 }
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            description      "
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                This divider option affects the bus clock."
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        }
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        cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_PFC {
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            display          "SH peripheral clock divider"
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            flavor           data
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            default_value    6
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            legal_values     { 1 2 3 4 6 8 }
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            description      "
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                This divider option affects the peripheral clock."
200
        }
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        cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE {
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            display          "SH clock mode"
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            flavor           data
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            default_value    5
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            legal_values     { 0 1 2 3 4 5 }
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            description      "
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                This option must mirror the clock mode hardwired on
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                the MD0-MD2 pins of the CPU in order to correctly
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                initialize the FRQCR register."
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        }
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    }
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    cdl_component CYGBLD_GLOBAL_OPTIONS {
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        display "Global build options"
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        flavor  none
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        parent  CYGPKG_NONE
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        description   "
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            Global build options including control over
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            compiler flags, linker flags and choice of toolchain."
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        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
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            display "Global command prefix"
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            flavor  data
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            no_define
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            default_value { "sh-elf" }
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            description "
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                This option specifies the command prefix used when
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                invoking the build tools."
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        }
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        # CPU flags should be -m4-nofpu
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        cdl_option CYGBLD_GLOBAL_CFLAGS {
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            display "Global compiler flags"
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            flavor  data
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            no_define
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            default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
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            description   "
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                This option controls the global compiler flags which
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                are used to compile all packages by
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                default. Individual packages may define
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                options which override these global flags."
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        }
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        cdl_option CYGBLD_GLOBAL_LDFLAGS {
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            display "Global linker flags"
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            flavor  data
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            no_define
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            default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" }
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            description   "
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                This option controls the global linker flags. Individual
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                packages may define options which override these global flags."
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        }
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        cdl_option CYGBLD_BUILD_GDB_STUBS {
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            display "Build GDB stub ROM image"
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            default_value 0
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            requires { CYG_HAL_STARTUP == "ROM" }
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            requires CYGSEM_HAL_ROM_MONITOR
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            requires CYGBLD_BUILD_COMMON_GDB_STUBS
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            requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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            requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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            requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
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            requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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            requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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            no_define
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            description "
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                This option enables the building of the GDB stubs for the
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                board. The common HAL controls takes care of most of the
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                build process, but the final conversion from ELF image to
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                binary data is handled by the platform CDL, allowing
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                relocation of the data if necessary."
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275
            make -priority 320 {
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                /bin/gdb_module.bin : /bin/gdb_module.img
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                $(OBJCOPY) -O binary $< $@
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            }
279
        }
280
    }
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    cdl_component CYGHWR_MEMORY_LAYOUT {
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        display "Memory layout"
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        flavor data
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        no_define
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        calculated { CYG_HAL_STARTUP == "RAM" ? "sh_sh7750_cq7750_ram" : \
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                                                "sh_sh7750_cq7750_rom" }
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        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
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            display "Memory layout linker script fragment"
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            flavor data
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            no_define
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            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
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            calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
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                                                    "" }
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        }
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        cdl_option CYGHWR_MEMORY_LAYOUT_H {
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            display "Memory layout header file"
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            flavor data
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            no_define
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            define -file system.h CYGHWR_MEMORY_LAYOUT_H
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            calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
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                                                    "" }
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        }
306
    }
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    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
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        display       "Work with a ROM monitor"
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        flavor        booldata
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        legal_values  { "GDB_stubs" }
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        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
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        requires      { CYG_HAL_STARTUP == "RAM" }
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        parent        CYGPKG_HAL_ROM_MONITOR
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        requires      !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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        description   "
317
            Support can be enabled for boot ROMs or ROM monitors which contain
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            GDB stubs. This support changes various eCos semantics such as
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            the encoding of diagnostic output, and the overriding of hardware
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            interrupt vectors."
321
    }
322
 
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    cdl_option CYGSEM_HAL_ROM_MONITOR {
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        display       "Behave as a ROM monitor"
325
        flavor        bool
326
        default_value 0
327
        parent        CYGPKG_HAL_ROM_MONITOR
328
        requires      { CYG_HAL_STARTUP == "ROM" }
329
        description   "
330
            Enable this option if this program is to be used as a ROM monitor,
331
            i.e. applications will be loaded into RAM on the board, and this
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            ROM monitor may process exceptions or interrupts generated from the
333
            application. This enables features such as utilizing a separate
334
            interrupt stack when exceptions are generated."
335
    }
336
 
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    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
338
        display       "Redboot HAL options"
339
        flavor        none
340
        no_define
341
        parent        CYGPKG_REDBOOT
342
        active_if     CYGPKG_REDBOOT
343
        description   "
344
            This option lists the target's requirements for a valid Redboot
345
            configuration."
346
 
347
        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
348
            display       "Build Redboot ROM binary image"
349
            active_if     CYGBLD_BUILD_REDBOOT
350
            default_value 1
351
            no_define
352
            description "This option enables the conversion of the Redboot ELF
353
                         image to a binary image suitable for ROM programming."
354
 
355
            make -priority 325 {
356
                /bin/redboot.bin : /bin/redboot.elf
357
                $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
358
                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
359
                $(OBJCOPY) -O binary $< $@
360
            }
361
        }
362
    }
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}

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