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#ifndef CYGONCE_HAL_PLATFORM_INC
#define CYGONCE_HAL_PLATFORM_INC
##=============================================================================
##
##      platform.inc
##
##      SH/CQ7750 board assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s):   jskov
## Contributors:Ryozaburo Suzuki
## Date:        2000-04-18
## Purpose:     SH/CQ7750 board definitions.
## Description: This file contains various definitions and macros that are
##              useful for writing assembly code for the SH/CQ7750 board.
## Usage:
##              #include 
##              ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include 
 
#include 
#include 
 
#------------------------------------------------------------------------------
# Hardware initialization.
 
        .macro  hal_hardware_init
        // Set up the Bus State Controller
        mova     BSC_settings_table,r0
        mov      r0,r3
1:      mov.l    @r3+,r0                // Address (or zero)
        mov      r0,r2
        cmp/eq   #0,r0
        bt       4f
        mov.l    @r3+,r1                // data
        mov.l    @r3+,r0                // byte or word or long?
 
        cmp/eq   #0,r0   // byte
        bt       2f
 
        cmp/eq   #1,r0   // word
        bt       3f
 
        bra      1b      // long
        mov.l    r1,@r2  // delay slot
 
2:      bra      1b
        mov.b    r1,@r2  // delay slot
 
3:      bra      1b
        mov.w    r1,@r2  // delay slot
 
        .align  2
 
BSC_settings_table:
        # FRQCR:
        .long   CYGARC_REG_FRQCR
        .long   CYGARC_REG_FRQCR_INIT
        .long   2
 
        # BCR1:
        .long   CYGARC_REG_BCR1
        .long   0x0020000c
        .long   2
        # BCR2:
        .long   CYGARC_REG_BCR2
        .long   0x35F8
        .long   1
        # WCR1:
        .long   CYGARC_REG_WCR1
        .long   0x77117121
        .long   2
        # WCR2:
        .long   CYGARC_REG_WCR2
        .long   0xFC8AE520
        .long   2
        # WCR3:
        .long   CYGARC_REG_WCR3
        .long   0x07117101
        .long   2
        # PCR:
        .long   CYGARC_REG_PCR
        .long   0x0000
        .long   1
        # RTCNT:
        .long   CYGARC_REG_RTCNT
        .long   0xa500
        .long   1
        # RTCOR:
        .long   CYGARC_REG_RTCOR
        .long   0xa53b
        .long   1
        # RFCR:
        .long   CYGARC_REG_RFCR
        .long   0xa400
        .long   1
        # RTCSR:
        .long   CYGARC_REG_RTCSR
        .long   0xa508
        .long   1
        # MCR:
        .long   CYGARC_REG_MCR
        .long   0x10192194
        .long   2
        # SDMR2:
        .long   0xFF90008c
        .long   0xaa
        .long   0
        # MCR:
        .long   CYGARC_REG_MCR
        .long   0x50192194
        .long   2
        # SDMR2:
        .long   0xFF90008c
        .long   0xaa
        .long   0
        # Table end
        .long   0
 
        .align  2
4:
        .endm
 
#------------------------------------------------------------------------------
# Monitor initialization.
 
#ifndef CYGPKG_HAL_SH_MON_DEFINED
 
#if     defined(CYG_HAL_STARTUP_ROM) ||                 \
        (       defined(CYG_HAL_STARTUP_RAM) &&         \
                !defined(CYGSEM_HAL_USE_ROM_MONITOR))
 
        # If we are starting up from ROM, or we are starting in
        # RAM and NOT using a ROM monitor, initialize the VSR table.
 
        .macro  hal_mon_init
        mov.l   $hal_vsr_table,r3
        # Write exception vectors
        mov.l   $cyg_hal_default_exception_vsr,r4
        mov     #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
1:      mov.l   r4,@r3
        add     #4,r3
        dt      r5
        bf      1b
        # Write interrupt vector
        mov.l   $cyg_hal_default_interrupt_vsr,r4
        mov.l   $hal_vsr_table,r3
        add     #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
        mov.l   r4,@r3
        bra     2f
         nop
        .align  2
 
        SYM_PTR_REF(cyg_hal_default_exception_vsr)
        SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
        SYM_PTR_REF(hal_vsr_table)
2:
        .endm
 
#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
        # Initialize the VSR table entries
        # We only take control of the interrupt vector,
        # the rest are left to the ROM for now...
 
        .macro  hal_mon_init
        # Write interrupt vector
        mov.l   $hal_vsr_table,r3
        mov.l   $cyg_hal_default_interrupt_vsr,r4
        add     #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
        mov.l   r4,@r3
        bra     2f
         nop
        .align  2
 
        SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
        SYM_PTR_REF(hal_vsr_table)
2:
        .endm
 
#else
 
        .macro  hal_mon_init
        .endm
 
#endif
 
 
#define CYGPKG_HAL_SH_MON_DEFINED
 
#endif // CYGPKG_HAL_SH_MON_DEFINED
 
#endif // CYGONCE_HAL_PLATFORM_INC

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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sh/] [cq7750/] [v2_0/] [include/] [platform.inc] - Blame information for rev 565

Line No.	Rev	Author	Line
1	27	unneback	`#ifndef CYGONCE_HAL_PLATFORM_INC`
2			`#define CYGONCE_HAL_PLATFORM_INC`
3			`##=============================================================================`
4			`##`
5			`## platform.inc`
6			`##`
7			`## SH/CQ7750 board assembler header file`
8			`##`
9			`##=============================================================================`
10			`#####ECOSGPLCOPYRIGHTBEGIN####`
11			`## -------------------------------------------`
12			`## This file is part of eCos, the Embedded Configurable Operating System.`
13			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.`
14			`##`
15			`## eCos is free software; you can redistribute it and/or modify it under`
16			`## the terms of the GNU General Public License as published by the Free`
17			`## Software Foundation; either version 2 or (at your option) any later version.`
18			`##`
19			`## eCos is distributed in the hope that it will be useful, but WITHOUT ANY`
20			`## WARRANTY; without even the implied warranty of MERCHANTABILITY or`
21			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
22			`## for more details.`
23			`##`
24			`## You should have received a copy of the GNU General Public License along`
25			`## with eCos; if not, write to the Free Software Foundation, Inc.,`
26			`## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.`
27			`##`
28			`## As a special exception, if other files instantiate templates or use macros`
29			`## or inline functions from this file, or you compile this file and link it`
30			`## with other works to produce a work based on this file, this file does not`
31			`## by itself cause the resulting work to be covered by the GNU General Public`
32			`## License. However the source code for this file must still be made available`
33			`## in accordance with section (3) of the GNU General Public License.`
34			`##`
35			`## This exception does not invalidate any other reasons why a work based on`
36			`## this file might be covered by the GNU General Public License.`
37			`##`
38			`## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.`
39			`## at http://sources.redhat.com/ecos/ecos-license/`
40			`## -------------------------------------------`
41			`#####ECOSGPLCOPYRIGHTEND####`
42			`##=============================================================================`
43			`#######DESCRIPTIONBEGIN####`
44			`##`
45			`## Author(s): jskov`
46			`## Contributors:Ryozaburo Suzuki`
47			`## Date: 2000-04-18`
48			`## Purpose: SH/CQ7750 board definitions.`
49			`## Description: This file contains various definitions and macros that are`
50			`## useful for writing assembly code for the SH/CQ7750 board.`
51			`## Usage:`
52			`## #include`
53			`## ...`
54			`##`
55			`##`
56			`######DESCRIPTIONEND####`
57			`##`
58			`##=============================================================================`
59
60			`#include`
61
62			`#include`
63			`#include`
64
65			`#------------------------------------------------------------------------------`
66			`# Hardware initialization.`
67
68			`.macro hal_hardware_init`
69			`// Set up the Bus State Controller`
70			`mova BSC_settings_table,r0`
71			`mov r0,r3`
72			`1: mov.l @r3+,r0 // Address (or zero)`
73			`mov r0,r2`
74			`cmp/eq #0,r0`
75			`bt 4f`
76			`mov.l @r3+,r1 // data`
77			`mov.l @r3+,r0 // byte or word or long?`
78
79			`cmp/eq #0,r0 // byte`
80			`bt 2f`
81
82			`cmp/eq #1,r0 // word`
83			`bt 3f`
84
85			`bra 1b // long`
86			`mov.l r1,@r2 // delay slot`
87
88			`2: bra 1b`
89			`mov.b r1,@r2 // delay slot`
90
91			`3: bra 1b`
92			`mov.w r1,@r2 // delay slot`
93
94			`.align 2`
95
96			`BSC_settings_table:`
97			`# FRQCR:`
98			`.long CYGARC_REG_FRQCR`
99			`.long CYGARC_REG_FRQCR_INIT`
100			`.long 2`
101
102			`# BCR1:`
103			`.long CYGARC_REG_BCR1`
104			`.long 0x0020000c`
105			`.long 2`
106			`# BCR2:`
107			`.long CYGARC_REG_BCR2`
108			`.long 0x35F8`
109			`.long 1`
110			`# WCR1:`
111			`.long CYGARC_REG_WCR1`
112			`.long 0x77117121`
113			`.long 2`
114			`# WCR2:`
115			`.long CYGARC_REG_WCR2`
116			`.long 0xFC8AE520`
117			`.long 2`
118			`# WCR3:`
119			`.long CYGARC_REG_WCR3`
120			`.long 0x07117101`
121			`.long 2`
122			`# PCR:`
123			`.long CYGARC_REG_PCR`
124			`.long 0x0000`
125			`.long 1`
126			`# RTCNT:`
127			`.long CYGARC_REG_RTCNT`
128			`.long 0xa500`
129			`.long 1`
130			`# RTCOR:`
131			`.long CYGARC_REG_RTCOR`
132			`.long 0xa53b`
133			`.long 1`
134			`# RFCR:`
135			`.long CYGARC_REG_RFCR`
136			`.long 0xa400`
137			`.long 1`
138			`# RTCSR:`
139			`.long CYGARC_REG_RTCSR`
140			`.long 0xa508`
141			`.long 1`
142			`# MCR:`
143			`.long CYGARC_REG_MCR`
144			`.long 0x10192194`
145			`.long 2`
146			`# SDMR2:`
147			`.long 0xFF90008c`
148			`.long 0xaa`
149			`.long 0`
150			`# MCR:`
151			`.long CYGARC_REG_MCR`
152			`.long 0x50192194`
153			`.long 2`
154			`# SDMR2:`
155			`.long 0xFF90008c`
156			`.long 0xaa`
157			`.long 0`
158			`# Table end`
159			`.long 0`
160
161			`.align 2`
162			`4:`
163			`.endm`
164
165			`#------------------------------------------------------------------------------`
166			`# Monitor initialization.`
167
168			`#ifndef CYGPKG_HAL_SH_MON_DEFINED`
169
170			`#if defined(CYG_HAL_STARTUP_ROM) \|\| \`
171			`( defined(CYG_HAL_STARTUP_RAM) && \`
172			`!defined(CYGSEM_HAL_USE_ROM_MONITOR))`
173
174			`# If we are starting up from ROM, or we are starting in`
175			`# RAM and NOT using a ROM monitor, initialize the VSR table.`
176
177			`.macro hal_mon_init`
178			`mov.l $hal_vsr_table,r3`
179			`# Write exception vectors`
180			`mov.l $cyg_hal_default_exception_vsr,r4`
181			`mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5`
182			`1: mov.l r4,@r3`
183			`add #4,r3`
184			`dt r5`
185			`bf 1b`
186			`# Write interrupt vector`
187			`mov.l $cyg_hal_default_interrupt_vsr,r4`
188			`mov.l $hal_vsr_table,r3`
189			`add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3`
190			`mov.l r4,@r3`
191			`bra 2f`
192			`nop`
193			`.align 2`
194
195			`SYM_PTR_REF(cyg_hal_default_exception_vsr)`
196			`SYM_PTR_REF(cyg_hal_default_interrupt_vsr)`
197			`SYM_PTR_REF(hal_vsr_table)`
198			`2:`
199			`.endm`
200
201			`#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)`
202
203			`# Initialize the VSR table entries`
204			`# We only take control of the interrupt vector,`
205			`# the rest are left to the ROM for now...`
206
207			`.macro hal_mon_init`
208			`# Write interrupt vector`
209			`mov.l $hal_vsr_table,r3`
210			`mov.l $cyg_hal_default_interrupt_vsr,r4`
211			`add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3`
212			`mov.l r4,@r3`
213			`bra 2f`
214			`nop`
215			`.align 2`
216
217			`SYM_PTR_REF(cyg_hal_default_interrupt_vsr)`
218			`SYM_PTR_REF(hal_vsr_table)`
219			`2:`
220			`.endm`
221
222			`#else`
223
224			`.macro hal_mon_init`
225			`.endm`
226
227			`#endif`
228
229
230			`#define CYGPKG_HAL_SH_MON_DEFINED`
231
232			`#endif // CYGPKG_HAL_SH_MON_DEFINED`
233
234			`#endif // CYGONCE_HAL_PLATFORM_INC`