OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sh/] [edk7708/] [v2_0/] [include/] [pkgconf/] [mlt_sh_edk7708_romram.ldi] - Blame information for rev 565

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
// eCos memory layout - Fri Oct 20 09:51:30 2000
2
 
3
// This is a generated file - do not edit
4
 
5
#include 
6
 
7
MEMORY
8
{
9
    ram : ORIGIN = 0x88000200, LENGTH = 0xffe00
10
    rom : ORIGIN = 0x80000000, LENGTH = 0x20000
11
}
12
 
13
SECTIONS
14
{
15
    SECTIONS_BEGIN
16
    SECTION_vectors (ram, 0x88000200, AT (0x80000000))
17
    SECTION_text (ram, ALIGN (0x10), FOLLOWING (.vectors))
18
    SECTION_fini (ram, ALIGN (0x10), FOLLOWING (.text))
19
    SECTION_rodata1 (ram, ALIGN (0x10), FOLLOWING (.fini))
20
    SECTION_rodata (ram, ALIGN (0x10), FOLLOWING (.rodata1))
21
    SECTION_fixup (ram, ALIGN (0x10), FOLLOWING (.rodata))
22
    SECTION_gcc_except_table (ram, ALIGN (0x10), FOLLOWING (.fixup))
23
    SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table))
24
    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
25
    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
26
    SECTIONS_END
27
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.