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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sh/] [hs7729pci/] [v2_0/] [include/] [platform.inc] - Blame information for rev 454

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#ifndef CYGONCE_HAL_PLATFORM_INC
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#define CYGONCE_HAL_PLATFORM_INC
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##=============================================================================
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##
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##      platform.inc
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##
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##      Hitachi HS7729PCI board assembler header file
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s):   jskov
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## Contributors:jskov, gthomas
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## Date:        2001-05-25
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## Purpose:     Hitachi HS7729PCI platform startup
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## Description: This file contains various definitions and macros that are
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##              useful for writing assembly code for the Hitachi HS7729PCI
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##              board.
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## Usage:
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##              #include 
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##              ...
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##
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include 
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#include 
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#include 
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#------------------------------------------------------------------------------
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# Hardware initialization.
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        .macro  hal_hardware_init
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        // Set up the Bus State Controller
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        mova     BSC_settings_table,r0
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        mov      r0,r3
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1:      mov.w    @r3+,r0                // Address (or zero)
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        cmp/eq   #0,r0
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        bt       2f
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        mov.w    @r3+,r1                // data
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        bra      1b
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         mov.w    r1,@r0                // delay slot
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        .align  2
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BSC_settings_table:
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        .word   CYGARC_REG_WTCSR, 0xA502
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        .word   CYGARC_REG_WTCNT, 0x5A00
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        .word   CYGARC_REG_FRQCR, CYGARC_REG_FRQCR_INIT
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        # Settings from Hitachi docs
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        .word   CYGARC_REG_BCR1,  0x0008
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        .word   CYGARC_REG_BCR2,  0x2be0
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        .word   CYGARC_REG_BCR3,  0x0000
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        .word   CYGARC_REG_WCR1,  0x0c30
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        .word   CYGARC_REG_WCR2,  0x6cdf
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        .word   CYGARC_REG_MCR,   0x0014
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        # Settings from bootrom delivered with board
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        .word   CYGARC_REG_DCR,   0x0000
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        .word   CYGARC_REG_PCR,   0x0000
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        .word   CYGARC_REG_RTCOR, 0xa580
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        .word   CYGARC_REG_RFCR,  0xa400
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        .word   CYGARC_REG_RTCNT, 0xa500
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        .word   CYGARC_REG_RTCSR, 0xa508
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        .word   0
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2:
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        mov.l    $SDMR,r1               // Turns on SDRAM controller
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        mov.l    $SDMR_val,r2
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        mov.b    r2,@r1
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        mov.l    $SDRAM,r1
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        mov.l    $SDRAM_val,r2
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        mov.l    r2,@r1
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        mova     Post_settings_table,r0
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        mov      r0,r3
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1:      mov.l    @r3+,r0                // Address (or zero)
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        cmp/eq   #0,r0
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        bt       4f
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        mov.l    @r3+,r1                // data
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        bra      1b
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         mov.w    r1,@r0                // delay slot
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        .align  4
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$SDMR:  .long   0xffffe880
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$SDMR_val:
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        .long   0
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$SDRAM:
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        .long   CYGARC_REG_SD0001_SDRAM
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$SDRAM_val:
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        .long   CYGARC_REG_SD0001_SDRAM_INIT
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Post_settings_table:
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        # PFC settings from bootrom
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        .long   CYGARC_REG_PACR,0x0000
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        .long   CYGARC_REG_PBCR,0x0000
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        .long   CYGARC_REG_PCCR,0x5555
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        .long   CYGARC_REG_PDCR,0x0055
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        .long   CYGARC_REG_PECR,0xaa8a
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        .long   CYGARC_REG_PFCR,0xaaaa
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        .long   CYGARC_REG_PGCR,0xaaaa
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        .long   CYGARC_REG_PHCR,0x6a00
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        .long   CYGARC_REG_PJCR,0x0000
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        .long   CYGARC_REG_PKCR,0x0000
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        .long   CYGARC_REG_PLCR,0xaaaa
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        .long   CYGARC_REG_SCPCR,0x0000
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        .long   0
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4:
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        .endm
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#------------------------------------------------------------------------------
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# Monitor initialization.
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#ifndef CYGPKG_HAL_SH_MON_DEFINED
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#if     !defined(CYG_HAL_STARTUP_RAM) ||                \
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        (       defined(CYG_HAL_STARTUP_RAM) &&         \
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                !defined(CYGSEM_HAL_USE_ROM_MONITOR))
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        # If we are not starting up from RAM, or we are starting in
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        # RAM and NOT using a ROM monitor, initialize the VSR table.
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        .macro  hal_mon_init
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        mov.l   $hal_vsr_table,r3
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        # Write exception vectors
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        mov.l   $cyg_hal_default_exception_vsr,r4
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        mov     #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
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1:      mov.l   r4,@r3
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        add     #4,r3
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        dt      r5
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        bf      1b
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        # Write interrupt vector
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        mov.l   $cyg_hal_default_interrupt_vsr,r4
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        mov.l   $hal_vsr_table,r3
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        add     #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
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        mov.l   r4,@r3
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        bra     2f
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         nop
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        .align  2
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        SYM_PTR_REF(cyg_hal_default_exception_vsr)
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        SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
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        SYM_PTR_REF(hal_vsr_table)
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2:
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        .endm
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#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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        # Initialize the VSR table entries
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        # We only take control of the interrupt vector,
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        # the rest are left to the ROM for now...
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        .macro  hal_mon_init
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        # Write interrupt vector
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        mov.l   $hal_vsr_table,r3
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        mov.l   $cyg_hal_default_interrupt_vsr,r4
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        add     #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
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        mov.l   r4,@r3
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        bra     2f
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         nop
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        .align  2
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        SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
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        SYM_PTR_REF(hal_vsr_table)
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2:
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        .endm
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#else
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        .macro  hal_mon_init
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        .endm
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#endif
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#define CYGPKG_HAL_SH_MON_DEFINED
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#endif // CYGPKG_HAL_SH_MON_DEFINED
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#endif // CYGONCE_HAL_PLATFORM_INC

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