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#ifndef CYGONCE_HAL_PLF_INTR_H
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#define CYGONCE_HAL_PLF_INTR_H
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//==========================================================================
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//
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// plf_intr.h
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//
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// Platform specific Interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors: jskov
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// Date: 2001-06-12
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock for the SE77x9 board.
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// Usage:
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// #include <cyg/hal/plf_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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//----------------------------------------------------------------------------
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// External interrupts.
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#define CYGNUM_HAL_INTERRUPT_EXTERNALS_BASE CYGNUM_HAL_INTERRUPT_LVL0
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#define CYGNUM_HAL_INTERRUPT_SLOT_IRQ8 CYGNUM_HAL_INTERRUPT_LVL0
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#define CYGNUM_HAL_INTERRUPT_SLOT_IRQ7 CYGNUM_HAL_INTERRUPT_LVL1
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#define CYGNUM_HAL_INTERRUPT_SLOT_IRQ6 CYGNUM_HAL_INTERRUPT_LVL2
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#define CYGNUM_HAL_INTERRUPT_SLOT_IRQ5 CYGNUM_HAL_INTERRUPT_LVL3
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#define CYGNUM_HAL_INTERRUPT_SLOT_IRQ4 CYGNUM_HAL_INTERRUPT_LVL4
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#define CYGNUM_HAL_INTERRUPT_SLOT_IRQ3 CYGNUM_HAL_INTERRUPT_LVL5
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#define CYGNUM_HAL_INTERRUPT_SLOT_IRQ2 CYGNUM_HAL_INTERRUPT_LVL6
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#define CYGNUM_HAL_INTERRUPT_SLOT_IRQ1 CYGNUM_HAL_INTERRUPT_LVL7
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#define CYGNUM_HAL_INTERRUPT_PC_SIRQ4 CYGNUM_HAL_INTERRUPT_LVL8
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#define CYGNUM_HAL_INTERRUPT_PC_SIRQ3 CYGNUM_HAL_INTERRUPT_LVL9
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#define CYGNUM_HAL_INTERRUPT_PC_SIRQ2 CYGNUM_HAL_INTERRUPT_LVL10
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#define CYGNUM_HAL_INTERRUPT_PC_SIRQ1 CYGNUM_HAL_INTERRUPT_LVL11
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#define CYGNUM_HAL_INTERRUPT_PCIA CYGNUM_HAL_INTERRUPT_LVL12
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#define CYGNUM_HAL_INTERRUPT_PCIB CYGNUM_HAL_INTERRUPT_LVL13
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#define CYGNUM_HAL_INTERRUPT_PCIC CYGNUM_HAL_INTERRUPT_LVL14
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#define CYGNUM_HAL_INTERRUPT_PCID CYGNUM_HAL_INTERRUPT_LVL14 // !?!
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//----------------------------------------------------------------------------
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// Interrupt controller
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#define CYGARC_REG_INTC_A 0xbb000000
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#define CYGARC_REG_INTC_B 0xbb000002
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#define CYGARC_REG_INTC_C 0xbb000004
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#define CYGARC_REG_INTC_D 0xbb000006
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#define CYGARC_REG_INTC_E 0xbb000008
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//----------------------------------------------------------------------------
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// Interrupt configuration extention macros
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#define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level) \
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case CYGNUM_HAL_INTERRUPT_SLOT_IRQ8 ... CYGNUM_HAL_INTERRUPT_SLOT_IRQ5: \
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{ \
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cyg_uint16 msk; \
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int shift = 4*(3 - (vec - CYGNUM_HAL_INTERRUPT_SLOT_IRQ8)); \
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HAL_READ_UINT16(CYGARC_REG_INTC_A, msk); \
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msk &= ~(0x000f << shift); \
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if (level) msk |= (CYGNUM_HAL_INTERRUPT_LVL14 - vec + 1) << shift; \
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HAL_WRITE_UINT16(CYGARC_REG_INTC_A, msk); \
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break; \
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} \
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case CYGNUM_HAL_INTERRUPT_SLOT_IRQ4 ... CYGNUM_HAL_INTERRUPT_SLOT_IRQ1: \
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{ \
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cyg_uint16 msk; \
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int shift = 4*(3 - (vec - CYGNUM_HAL_INTERRUPT_SLOT_IRQ4)); \
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HAL_READ_UINT16(CYGARC_REG_INTC_B, msk); \
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msk &= ~(0x000f << shift); \
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if (level) msk |= (CYGNUM_HAL_INTERRUPT_LVL14 - vec + 1) << shift; \
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HAL_WRITE_UINT16(CYGARC_REG_INTC_B, msk); \
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break; \
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} \
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case CYGNUM_HAL_INTERRUPT_PC_SIRQ4 ... CYGNUM_HAL_INTERRUPT_PC_SIRQ1: \
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{ \
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cyg_uint16 msk; \
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int shift = 4*(3 - (vec - CYGNUM_HAL_INTERRUPT_PC_SIRQ4)); \
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HAL_READ_UINT16(CYGARC_REG_INTC_C, msk); \
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msk &= ~(0x000f << shift); \
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if (level) msk |= (CYGNUM_HAL_INTERRUPT_LVL14 - vec + 1) << shift; \
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HAL_WRITE_UINT16(CYGARC_REG_INTC_C, msk); \
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break; \
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} \
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case CYGNUM_HAL_INTERRUPT_PCIA ... CYGNUM_HAL_INTERRUPT_PCIC: \
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{ \
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cyg_uint16 msk; \
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int shift = 4*(3 - (vec - CYGNUM_HAL_INTERRUPT_PCIA)); \
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HAL_READ_UINT16(CYGARC_REG_INTC_D, msk); \
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msk &= ~(0x000f << shift); \
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if (level) msk |= (CYGNUM_HAL_INTERRUPT_LVL14 - vec + 1) << shift; \
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HAL_WRITE_UINT16(CYGARC_REG_INTC_D, msk); \
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break; \
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}
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//----------------------------------------------------------------------------
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// Reset.
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// Block interrupts and cause an exception. This forces a reset.
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#define HAL_PLATFORM_RESET() \
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asm volatile ("ldc %0,sr;trapa #0x00;" : : "r" (CYGARC_REG_SR_BL))
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#define HAL_PLATFORM_RESET_ENTRY 0x80000000
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//--------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_PLF_INTR_H
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// End of plf_intr.h
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