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#ifndef CYGONCE_VAR_INTR_H
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#define CYGONCE_VAR_INTR_H
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//==========================================================================
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//
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// var_intr.h
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//
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// HAL variant interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors: jskov,
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// Date: 1999-04-24
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock.
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//
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// Usage:
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// #include <cyg/hal/hal_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include CYGBLD_HAL_CPU_MODULES_H // INTC module selection
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//--------------------------------------------------------------------------
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// Optional platform overrides and fallbacks
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#include <cyg/hal/plf_intr.h>
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#ifndef CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF
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# define CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vec)
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#endif
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#ifndef CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF
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# define CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vec, level, up)
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#endif
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//----------------------------------------------------------------------------
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// Additional vectors provided by INTC V1
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#if (CYGARC_SH_MOD_INTC == 1)
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#ifndef CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF
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# define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level) \
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case CYGNUM_HAL_INTERRUPT_NMI: \
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/* fall through */ \
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case CYGNUM_HAL_INTERRUPT_LVL4 ... CYGNUM_HAL_INTERRUPT_LVL_MAX: \
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/* Cannot change levels */ \
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break;
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#endif
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#define CYGNUM_HAL_INTERRUPT_LVL8 9
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#define CYGNUM_HAL_INTERRUPT_LVL9 10
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#define CYGNUM_HAL_INTERRUPT_LVL10 11
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#define CYGNUM_HAL_INTERRUPT_LVL11 12
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#define CYGNUM_HAL_INTERRUPT_LVL12 13
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#define CYGNUM_HAL_INTERRUPT_LVL13 14
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#define CYGNUM_HAL_INTERRUPT_LVL14 15
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#define CYGNUM_HAL_INTERRUPT_DMAC0_TE 16
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#define CYGNUM_HAL_INTERRUPT_DMAC1_TE 17
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#define CYGNUM_HAL_INTERRUPT_WDT_ITI 18
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#define CYGNUM_HAL_INTERRUPT_REF_CMI 19
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#define CYGNUM_HAL_INTERRUPT_EDMAC_EINT 20
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#define CYGNUM_HAL_INTERRUPT_FRT_ICI 21
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#define CYGNUM_HAL_INTERRUPT_FRT_OCI 22
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#define CYGNUM_HAL_INTERRUPT_FRT_OVI 23
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#define CYGNUM_HAL_INTERRUPT_TPU0_TGI0A 24
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#define CYGNUM_HAL_INTERRUPT_TPU0_TGI0B 25
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#define CYGNUM_HAL_INTERRUPT_TPU0_TGI0C 26
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#define CYGNUM_HAL_INTERRUPT_TPU0_TGI0D 27
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#define CYGNUM_HAL_INTERRUPT_TPU0_TGI0V 28
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#define CYGNUM_HAL_INTERRUPT_TPU1_TGI1A 29
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#define CYGNUM_HAL_INTERRUPT_TPU1_TGI1B 30
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#define CYGNUM_HAL_INTERRUPT_TPU1_TGI1V 31
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#define CYGNUM_HAL_INTERRUPT_TPU1_TGI1U 32
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#define CYGNUM_HAL_INTERRUPT_TPU2_TGI2A 33
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#define CYGNUM_HAL_INTERRUPT_TPU2_TGI2B 34
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#define CYGNUM_HAL_INTERRUPT_TPU2_TGI2V 35
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#define CYGNUM_HAL_INTERRUPT_TPU2_TGI2U 36
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#define CYGNUM_HAL_INTERRUPT_SCIF1_ERI1 37
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#define CYGNUM_HAL_INTERRUPT_SCIF1_RXI1 38
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#define CYGNUM_HAL_INTERRUPT_SCIF1_BRI1 39
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#define CYGNUM_HAL_INTERRUPT_SCIF1_TXI1 40
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#define CYGNUM_HAL_INTERRUPT_SCIF2_ERI2 41
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#define CYGNUM_HAL_INTERRUPT_SCIF2_RXI2 42
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#define CYGNUM_HAL_INTERRUPT_SCIF2_BRI2 43
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#define CYGNUM_HAL_INTERRUPT_SCIF2_TXI2 44
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#define CYGNUM_HAL_INTERRUPT_SIO0_RERI0 45
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#define CYGNUM_HAL_INTERRUPT_SIO0_TERI0 46
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#define CYGNUM_HAL_INTERRUPT_SIO0_RDFI0 47
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#define CYGNUM_HAL_INTERRUPT_SIO0_TDEI0 48
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#define CYGNUM_HAL_INTERRUPT_SIO1_RERI1 49
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#define CYGNUM_HAL_INTERRUPT_SIO1_TERI1 50
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#define CYGNUM_HAL_INTERRUPT_SIO1_RDFI1 51
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#define CYGNUM_HAL_INTERRUPT_SIO1_TDEI1 52
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#define CYGNUM_HAL_INTERRUPT_SIO2_RERI2 53
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#define CYGNUM_HAL_INTERRUPT_SIO2_TERI2 54
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#define CYGNUM_HAL_INTERRUPT_SIO2_RDFI2 55
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#define CYGNUM_HAL_INTERRUPT_SIO2_TDEI2 56
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#define CYGNUM_HAL_INTERRUPT_LVL_MAX CYGNUM_HAL_INTERRUPT_LVL14
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#undef CYGNUM_HAL_ISR_MAX
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#ifdef CYGNUM_HAL_ISR_PLF_MAX
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# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_ISR_PLF_MAX
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#else
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# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_SIO2_TDEI2
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#endif
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// The vector used by the Real time clock
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#ifndef CYGNUM_HAL_INTERRUPT_RTC
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# define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_FRT_OCI
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#endif
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#elif (CYGARC_SH_MOD_INTC == 2)
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#ifndef CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF
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# define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level) \
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case CYGNUM_HAL_INTERRUPT_NMI: \
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/* Cannot change levels */ \
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break;
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#endif
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#define CYGNUM_HAL_INTERRUPT_DMAC0_DEI0 9
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#define CYGNUM_HAL_INTERRUPT_DMAC1_DEI1 10
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#define CYGNUM_HAL_INTERRUPT_DMAC2_DEI2 11
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#define CYGNUM_HAL_INTERRUPT_DMAC3_DEI3 12
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#define CYGNUM_HAL_INTERRUPT_MTU0_TGI0A 13
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#define CYGNUM_HAL_INTERRUPT_MTU0_TGI0B 14
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#define CYGNUM_HAL_INTERRUPT_MTU0_TGI0C 15
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#define CYGNUM_HAL_INTERRUPT_MTU0_TGI0D 16
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#define CYGNUM_HAL_INTERRUPT_MTU0_TGI0V 17
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#define CYGNUM_HAL_INTERRUPT_MTU1_TGI1A 18
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#define CYGNUM_HAL_INTERRUPT_MTU1_TGI1B 19
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#define CYGNUM_HAL_INTERRUPT_MTU1_TGI1V 20
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#define CYGNUM_HAL_INTERRUPT_MTU1_TGI1U 21
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#define CYGNUM_HAL_INTERRUPT_MTU2_TGI2A 22
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#define CYGNUM_HAL_INTERRUPT_MTU2_TGI2B 23
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#define CYGNUM_HAL_INTERRUPT_MTU2_TGI2V 24
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#define CYGNUM_HAL_INTERRUPT_MTU2_TGI2U 25
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#define CYGNUM_HAL_INTERRUPT_MTU3_TGI3A 26
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#define CYGNUM_HAL_INTERRUPT_MTU3_TGI3B 27
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#define CYGNUM_HAL_INTERRUPT_MTU3_TGI3C 28
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#define CYGNUM_HAL_INTERRUPT_MTU3_TGI3D 29
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#define CYGNUM_HAL_INTERRUPT_MTU3_TGI3V 30
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#define CYGNUM_HAL_INTERRUPT_MTU4_TGI4A 31
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#define CYGNUM_HAL_INTERRUPT_MTU4_TGI4B 32
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#define CYGNUM_HAL_INTERRUPT_MTU4_TGI4C 33
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#define CYGNUM_HAL_INTERRUPT_MTU4_TGI4D 34
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#define CYGNUM_HAL_INTERRUPT_MTU4_TGI4V 35
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#define CYGNUM_HAL_INTERRUPT_SCI0_ERI0 36
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#define CYGNUM_HAL_INTERRUPT_SCI0_RXI0 37
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#define CYGNUM_HAL_INTERRUPT_SCI0_TXI0 38
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#define CYGNUM_HAL_INTERRUPT_SCI0_TEI0 39
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#define CYGNUM_HAL_INTERRUPT_SCI1_ERI1 40
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#define CYGNUM_HAL_INTERRUPT_SCI1_RXI1 41
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#define CYGNUM_HAL_INTERRUPT_SCI1_TXI1 42
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#define CYGNUM_HAL_INTERRUPT_SCI1_TEI1 43
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#define CYGNUM_HAL_INTERRUPT_AD_ADI0 44
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#define CYGNUM_HAL_INTERRUPT_AD_ADI1 45
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#define CYGNUM_HAL_INTERRUPT_DTC_SWDTCE 46
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#define CYGNUM_HAL_INTERRUPT_CMT0_CMI0 47
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#define CYGNUM_HAL_INTERRUPT_CMT1_CMI1 48
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#define CYGNUM_HAL_INTERRUPT_WDT_ITI 49
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#define CYGNUM_HAL_INTERRUPT_BSC_CMI 50
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#define CYGNUM_HAL_INTERRUPT_IO_OEI 51
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#define CYGNUM_HAL_INTERRUPT_VAR_RESERVED 52 // just to catch bad assignments
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#undef CYGNUM_HAL_ISR_MAX
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#ifdef CYGNUM_HAL_ISR_PLF_MAX
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# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_ISR_PLF_MAX
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#else
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# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_VAR_RESERVED
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#endif
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// eCos vector this entry decodes to , actual HW interrupt vector
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#define CYGHWR_HAL_SH_SH2_CUSTOM_INTERRUPT_LAYOUT \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL0 , 1 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL1 , 2 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL2 , 3 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL3 , 4 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL4 , 5 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL5 , 6 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL6 , 7 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL7 , 8 ; \
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\
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exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC0_DEI0 , 9 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 10 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 11 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 12 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC1_DEI1 , 13 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 14 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 15 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 16 ; \
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| 235 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC2_DEI2 , 17 ; \
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| 236 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 18 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 19 ; \
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| 238 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 20 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC3_DEI3 , 21 ; \
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| 240 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 22 ; \
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| 241 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 23 ; \
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| 242 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 24 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0A , 25 ; \
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| 244 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0B , 26 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0C , 27 ; \
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| 246 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0D , 28 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0V , 29 ; \
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| 248 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 30 ; \
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| 249 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 31 ; \
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| 250 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 32 ; \
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| 251 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1A , 33 ; \
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| 252 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1B , 34 ; \
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| 253 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 35 ; \
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| 254 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 36 ; \
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| 255 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1V , 37 ; \
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| 256 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1U , 38 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 39 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 40 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2A , 41 ; \
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| 260 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2B , 42 ; \
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| 261 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 43 ; \
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| 262 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 44 ; \
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| 263 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2V , 45 ; \
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| 264 |
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2U , 46 ; \
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| 265 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 47 ; \
|
| 266 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 48 ; \
|
| 267 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3A , 49 ; \
|
| 268 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3B , 50 ; \
|
| 269 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3C , 51 ; \
|
| 270 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3D , 52 ; \
|
| 271 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3V , 53 ; \
|
| 272 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 54 ; \
|
| 273 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 55 ; \
|
| 274 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 56 ; \
|
| 275 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4A , 57 ; \
|
| 276 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4B , 58 ; \
|
| 277 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4C , 59 ; \
|
| 278 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4D , 60 ; \
|
| 279 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4V , 61 ; \
|
| 280 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 62 ; \
|
| 281 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 63 ; \
|
| 282 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 64 ; \
|
| 283 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_ERI0 , 65 ; \
|
| 284 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_RXI0 , 66 ; \
|
| 285 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_TXI0 , 67 ; \
|
| 286 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_TEI0 , 68 ; \
|
| 287 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_ERI1 , 69 ; \
|
| 288 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_RXI1 , 70 ; \
|
| 289 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_TXI1 , 71 ; \
|
| 290 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_TEI1 , 72 ; \
|
| 291 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_AD_ADI0 , 73 ; \
|
| 292 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_AD_ADI1 , 74 ; \
|
| 293 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 75 ; \
|
| 294 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 76 ; \
|
| 295 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_DTC_SWDTCE , 77 ; \
|
| 296 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 78 ; \
|
| 297 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 79 ; \
|
| 298 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 80 ; \
|
| 299 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_CMT0_CMI0 , 81 ; \
|
| 300 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 82 ; \
|
| 301 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 83 ; \
|
| 302 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 84 ; \
|
| 303 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_CMT1_CMI1 , 85 ; \
|
| 304 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 86 ; \
|
| 305 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 87 ; \
|
| 306 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 88 ; \
|
| 307 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_WDT_ITI , 89 ; \
|
| 308 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_BSC_CMI , 90 ; \
|
| 309 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 91 ; \
|
| 310 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 92 ; \
|
| 311 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_BSC_CMI , 93 ; \
|
| 312 |
|
|
.set vecno, CYGNUM_HAL_INTERRUPT_VAR_RESERVED ; \
|
| 313 |
|
|
.rept (256-CYGNUM_HAL_INTERRUPT_VAR_RESERVED) ; \
|
| 314 |
|
|
exception_vector_int vecno ; \
|
| 315 |
|
|
.set vecno, vecno+1 ; \
|
| 316 |
|
|
.endr
|
| 317 |
|
|
|
| 318 |
|
|
// The vector used by the Real time clock
|
| 319 |
|
|
#ifndef CYGNUM_HAL_INTERRUPT_RTC
|
| 320 |
|
|
# define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_CMT0_CMI0
|
| 321 |
|
|
#endif
|
| 322 |
|
|
|
| 323 |
|
|
#else
|
| 324 |
|
|
|
| 325 |
|
|
# error "No vectors defined for this INTC type"
|
| 326 |
|
|
|
| 327 |
|
|
#endif
|
| 328 |
|
|
|
| 329 |
|
|
//----------------------------------------------------------------------------
|
| 330 |
|
|
// Platform may provide extensions to the interrupt configuration functions
|
| 331 |
|
|
// via these macros. The first macro is put inside the functions's
|
| 332 |
|
|
// switch statements, the last two called as functions.
|
| 333 |
|
|
#ifndef CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF
|
| 334 |
|
|
# define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level)
|
| 335 |
|
|
# define CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vec)
|
| 336 |
|
|
# define CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vec)
|
| 337 |
|
|
#endif
|
| 338 |
|
|
|
| 339 |
|
|
#ifndef __ASSEMBLER__
|
| 340 |
|
|
//--------------------------------------------------------------------------
|
| 341 |
|
|
// Clock control, using Free-running Timer to match on compare register A
|
| 342 |
|
|
|
| 343 |
|
|
#include <cyg/hal/sh_regs.h> // register definitions
|
| 344 |
|
|
#include <cyg/hal/hal_io.h> // io macros
|
| 345 |
|
|
#include <cyg/infra/cyg_ass.h> // CYG_FAIL
|
| 346 |
|
|
|
| 347 |
|
|
#if defined(CYGARC_SH_MOD_FRT)
|
| 348 |
|
|
#define HAL_CLOCK_VAR_INITIALIZE( _period_ ) \
|
| 349 |
|
|
CYG_MACRO_START \
|
| 350 |
|
|
register cyg_uint8 _tier_; \
|
| 351 |
|
|
\
|
| 352 |
|
|
/* Disable interrupts while programming the timer */ \
|
| 353 |
|
|
HAL_READ_UINT8(CYGARC_REG_TIER, _tier_); \
|
| 354 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TIER, 0); \
|
| 355 |
|
|
\
|
| 356 |
|
|
/* Clear counter register */ \
|
| 357 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_FRC, 0); \
|
| 358 |
|
|
/* Set compare A register */ \
|
| 359 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TOCR, CYGARC_REG_TOCR_OLVLA); \
|
| 360 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_OCR, _period_); \
|
| 361 |
|
|
\
|
| 362 |
|
|
/* Enable match A counter clear */ \
|
| 363 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_FTCSR, CYGARC_REG_FTCSR_CCLRA); \
|
| 364 |
|
|
/* Set interrupt prescaling */ \
|
| 365 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TCR, \
|
| 366 |
|
|
((8==CYGHWR_HAL_SH_FRT_PRESCALE) ? \
|
| 367 |
|
|
CYGARC_REG_TCR_CLK_8 : \
|
| 368 |
|
|
(32==CYGHWR_HAL_SH_FRT_PRESCALE) ? \
|
| 369 |
|
|
CYGARC_REG_TCR_CLK_32: \
|
| 370 |
|
|
(128==CYGHWR_HAL_SH_FRT_PRESCALE) ? \
|
| 371 |
|
|
CYGARC_REG_TCR_CLK_128:CYGARC_REG_TCR_CLK_EXT)); \
|
| 372 |
|
|
\
|
| 373 |
|
|
\
|
| 374 |
|
|
CYG_MACRO_END
|
| 375 |
|
|
|
| 376 |
|
|
// HAL_CLOCK_VAR_INITIALIZE is called from hal_variant_init since the
|
| 377 |
|
|
// FRT is also used by the hal_delay_us code.
|
| 378 |
|
|
#define HAL_CLOCK_INITIALIZE( _period_ ) \
|
| 379 |
|
|
CYG_MACRO_START \
|
| 380 |
|
|
register cyg_uint8 _tier_; \
|
| 381 |
|
|
\
|
| 382 |
|
|
CYG_ASSERT((cyg_uint16)(_period_) < (cyg_uint16)0xfffe, \
|
| 383 |
|
|
"period too large for 16bit FRT"); \
|
| 384 |
|
|
\
|
| 385 |
|
|
/* Disable interrupts while programming the timer */ \
|
| 386 |
|
|
HAL_READ_UINT8(CYGARC_REG_TIER, _tier_); \
|
| 387 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TIER, 0); \
|
| 388 |
|
|
\
|
| 389 |
|
|
/* Set compare A register */ \
|
| 390 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TOCR, CYGARC_REG_TOCR_OLVLA); \
|
| 391 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_OCR, _period_); \
|
| 392 |
|
|
\
|
| 393 |
|
|
/* Enable interrupt */ \
|
| 394 |
|
|
_tier_ |= CYGARC_REG_TIER_OCIAE; \
|
| 395 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TIER, _tier_); \
|
| 396 |
|
|
\
|
| 397 |
|
|
CYG_MACRO_END
|
| 398 |
|
|
|
| 399 |
|
|
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
|
| 400 |
|
|
CYG_MACRO_START \
|
| 401 |
|
|
register cyg_uint8 _ftcsr_; \
|
| 402 |
|
|
\
|
| 403 |
|
|
/* Clear match flag */ \
|
| 404 |
|
|
HAL_READ_UINT8(CYGARC_REG_FTCSR, _ftcsr_); \
|
| 405 |
|
|
_ftcsr_ &= ~CYGARC_REG_FTCSR_OCFA; \
|
| 406 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_FTCSR, _ftcsr_); \
|
| 407 |
|
|
\
|
| 408 |
|
|
CYG_MACRO_END
|
| 409 |
|
|
|
| 410 |
|
|
#define HAL_CLOCK_READ( _pvalue_ ) \
|
| 411 |
|
|
CYG_MACRO_START \
|
| 412 |
|
|
register cyg_uint16 _frc_; \
|
| 413 |
|
|
\
|
| 414 |
|
|
HAL_READ_UINT16(CYGARC_REG_FRC, _frc_); \
|
| 415 |
|
|
\
|
| 416 |
|
|
*(_pvalue_) = _frc_; \
|
| 417 |
|
|
CYG_MACRO_END
|
| 418 |
|
|
|
| 419 |
|
|
#elif defined(CYGARC_SH_MOD_CMT)
|
| 420 |
|
|
|
| 421 |
|
|
/* Compare Match Timer 0 is used for the eCos kernel RTC */
|
| 422 |
|
|
#define HAL_CLOCK_VAR_INITIALIZE( _period_ ) \
|
| 423 |
|
|
CYG_MACRO_START \
|
| 424 |
|
|
register cyg_uint16 _tmp_; \
|
| 425 |
|
|
\
|
| 426 |
|
|
/* Disable timer while programming it */ \
|
| 427 |
|
|
HAL_READ_UINT16(CYGARC_REG_CMSTR, _tmp_); \
|
| 428 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ & ~CYGARC_REG_CMSTR_STR0); \
|
| 429 |
|
|
\
|
| 430 |
|
|
/* Clear counter register */ \
|
| 431 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCNT0, 0); \
|
| 432 |
|
|
/* Set compare 0 register */ \
|
| 433 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCOR0, _period_); \
|
| 434 |
|
|
\
|
| 435 |
|
|
/* Set prescaling and disable interrupts */ \
|
| 436 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCSR0, \
|
| 437 |
|
|
((8==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
| 438 |
|
|
CYGARC_REG_CMCSR_CLK_8 : \
|
| 439 |
|
|
(32==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
| 440 |
|
|
CYGARC_REG_CMCSR_CLK_32: \
|
| 441 |
|
|
(128==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
| 442 |
|
|
CYGARC_REG_CMCSR_CLK_128:CYGARC_REG_CMCSR_CLK_512)); \
|
| 443 |
|
|
\
|
| 444 |
|
|
/* Start timer */ \
|
| 445 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ | CYGARC_REG_CMSTR_STR0); \
|
| 446 |
|
|
\
|
| 447 |
|
|
CYG_MACRO_END
|
| 448 |
|
|
|
| 449 |
|
|
// HAL_CLOCK_VAR_INITIALIZE is called from hal_variant_init since the
|
| 450 |
|
|
// CMT0 is also used by the hal_delay_us code.
|
| 451 |
|
|
#define HAL_CLOCK_INITIALIZE( _period_ ) \
|
| 452 |
|
|
CYG_MACRO_START \
|
| 453 |
|
|
register cyg_uint16 _tmp_; \
|
| 454 |
|
|
\
|
| 455 |
|
|
CYG_ASSERT((cyg_uint16)(_period_) < (cyg_uint16)0xfffe, \
|
| 456 |
|
|
"period too large for 16bit CMT"); \
|
| 457 |
|
|
\
|
| 458 |
|
|
/* Disable timer while programming it */ \
|
| 459 |
|
|
HAL_READ_UINT16(CYGARC_REG_CMSTR, _tmp_); \
|
| 460 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ & ~CYGARC_REG_CMSTR_STR0); \
|
| 461 |
|
|
\
|
| 462 |
|
|
/* Clear counter register */ \
|
| 463 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCNT0, 0); \
|
| 464 |
|
|
/* Set compare 0 register */ \
|
| 465 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCOR0, _period_); \
|
| 466 |
|
|
\
|
| 467 |
|
|
/* Set prescaling and enable interrupts */ \
|
| 468 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCSR0, CYGARC_REG_CMCSR_CMIE | \
|
| 469 |
|
|
((8==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
| 470 |
|
|
CYGARC_REG_CMCSR_CLK_8 : \
|
| 471 |
|
|
(32==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
| 472 |
|
|
CYGARC_REG_CMCSR_CLK_32: \
|
| 473 |
|
|
(128==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
| 474 |
|
|
CYGARC_REG_CMCSR_CLK_128:CYGARC_REG_CMCSR_CLK_512)); \
|
| 475 |
|
|
\
|
| 476 |
|
|
/* Start timer */ \
|
| 477 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ | CYGARC_REG_CMSTR_STR0); \
|
| 478 |
|
|
\
|
| 479 |
|
|
CYG_MACRO_END
|
| 480 |
|
|
|
| 481 |
|
|
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
|
| 482 |
|
|
CYG_MACRO_START \
|
| 483 |
|
|
register cyg_uint16 _tmp_; \
|
| 484 |
|
|
\
|
| 485 |
|
|
/* Clear match flag */ \
|
| 486 |
|
|
HAL_READ_UINT16(CYGARC_REG_CMCSR0, _tmp_); \
|
| 487 |
|
|
_tmp_ &= ~CYGARC_REG_CMCSR_CMF; \
|
| 488 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCSR0, _tmp_); \
|
| 489 |
|
|
\
|
| 490 |
|
|
CYG_MACRO_END
|
| 491 |
|
|
|
| 492 |
|
|
#define HAL_CLOCK_READ( _pvalue_ ) \
|
| 493 |
|
|
CYG_MACRO_START \
|
| 494 |
|
|
register cyg_uint16 _tmp_; \
|
| 495 |
|
|
\
|
| 496 |
|
|
HAL_READ_UINT16(CYGARC_REG_CMCNT0, _tmp_); \
|
| 497 |
|
|
\
|
| 498 |
|
|
*(_pvalue_) = _tmp_; \
|
| 499 |
|
|
CYG_MACRO_END
|
| 500 |
|
|
|
| 501 |
|
|
|
| 502 |
|
|
|
| 503 |
|
|
#else
|
| 504 |
|
|
# error "No RTC handling defined"
|
| 505 |
|
|
#endif
|
| 506 |
|
|
|
| 507 |
|
|
|
| 508 |
|
|
|
| 509 |
|
|
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
|
| 510 |
|
|
#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_)
|
| 511 |
|
|
#endif
|
| 512 |
|
|
|
| 513 |
|
|
|
| 514 |
|
|
//----------------------------------------------------------------------------
|
| 515 |
|
|
// Reset.
|
| 516 |
|
|
#ifndef HAL_PLATFORM_RESET
|
| 517 |
|
|
#define HAL_PLATFORM_RESET() \
|
| 518 |
|
|
CYG_MACRO_START \
|
| 519 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_RSTCSR_W, CYGARC_REG_RSTCSR_W_RSTx_MAGIC|CYGARC_REG_RSTCSR_RSTE); \
|
| 520 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_WTCNT_W, CYGARC_REG_WTCNT_W_MAGIC|0xfe); \
|
| 521 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_WTCSR_W, CYGARC_REG_WTCSR_W_MAGIC|CYGARC_REG_WTCSR_TME|CYGARC_REG_WTCSR_WTIT); \
|
| 522 |
|
|
/* wait for it */ \
|
| 523 |
|
|
for(;;) ; \
|
| 524 |
|
|
CYG_MACRO_END
|
| 525 |
|
|
#else
|
| 526 |
|
|
#define HAL_PLATFORM_RESET()
|
| 527 |
|
|
#endif
|
| 528 |
|
|
|
| 529 |
|
|
#endif // __ASSEMBLER__
|
| 530 |
|
|
|
| 531 |
|
|
//--------------------------------------------------------------------------
|
| 532 |
|
|
#endif // ifndef CYGONCE_VAR_INTR_H
|
| 533 |
|
|
// End of var_intr.h
|
