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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sh/] [sh2/] [v2_0/] [src/] [var_misc.c] - Blame information for rev 174

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//==========================================================================
2 
//
3 
//      var_misc.c
4 
//
5 
//      HAL miscellaneous functions
6 
//
7 
//==========================================================================
8 
//####ECOSGPLCOPYRIGHTBEGIN####
9 
// -------------------------------------------
10 
// This file is part of eCos, the Embedded Configurable Operating System.
11 
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 
//
13 
// eCos is free software; you can redistribute it and/or modify it under
14 
// the terms of the GNU General Public License as published by the Free
15 
// Software Foundation; either version 2 or (at your option) any later version.
16 
//
17 
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20 
// for more details.
21 
//
22 
// You should have received a copy of the GNU General Public License along
23 
// with eCos; if not, write to the Free Software Foundation, Inc.,
24 
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25 
//
26 
// As a special exception, if other files instantiate templates or use macros
27 
// or inline functions from this file, or you compile this file and link it
28 
// with other works to produce a work based on this file, this file does not
29 
// by itself cause the resulting work to be covered by the GNU General Public
30 
// License. However the source code for this file must still be made available
31 
// in accordance with section (3) of the GNU General Public License.
32 
//
33 
// This exception does not invalidate any other reasons why a work based on
34 
// this file might be covered by the GNU General Public License.
35 
//
36 
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 
// at http://sources.redhat.com/ecos/ecos-license/
38 
// -------------------------------------------
39 
//####ECOSGPLCOPYRIGHTEND####
40 
//==========================================================================
41 
//#####DESCRIPTIONBEGIN####
42 
//
43 
// Author(s):    jskov
44 
// Contributors: jskov, jlarmour, nickg
45 
// Date:         2002-01-09
46 
// Purpose:      HAL miscellaneous functions
47 
// Description:  This file contains miscellaneous functions provided by the
48 
//               HAL.
49 
//
50 
//####DESCRIPTIONEND####
51 
//
52 
//===========================================================================
53 
 
54 
#include <pkgconf/hal.h>
55 
 
56 
#include <cyg/infra/cyg_type.h>
57 
#include <cyg/infra/cyg_trac.h>         // tracing macros
58 
#include <cyg/infra/cyg_ass.h>          // assertion macros
59 
#include <cyg/infra/diag.h>             // diag_printf
60 
 
61 
#include <cyg/hal/hal_arch.h>           // HAL header
62 
#include <cyg/hal/hal_cache.h>          // HAL cache
63 
#include <cyg/hal/hal_intr.h>           // HAL interrupts/exceptions
64 
 
65 
//---------------------------------------------------------------------------
66 
// Initial cache enabling
67 
 
68 
#ifdef CYGHWR_HAL_SH_CACHE_MODE_WRITE_BACK
69 
# define CACHE_MODE HAL_UCACHE_WRITEBACK_MODE
70 
#else
71 
# define CACHE_MODE HAL_UCACHE_WRITETHRU_MODE
72 
#endif
73 
 
74 
externC void
75 
cyg_var_enable_caches(void)
76 
{
77 
    // If relying on a ROM monitor do not invalidate the caches as the
78 
    // ROM monitor may have (non-synced) state in the caches.
79 
#if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
80 
    // Initialize cache.
81 
    HAL_UCACHE_INVALIDATE_ALL();
82 
 
83 
#ifdef HAL_UCACHE_WRITE_MODE
84 
    // Set cache modes
85 
    HAL_UCACHE_WRITE_MODE(CACHE_MODE);
86 
#endif
87 
#endif
88 
#ifdef CYGHWR_HAL_SH_CACHE_ENABLE
89 
    // Enable cache.
90 
    HAL_UCACHE_ENABLE();
91 
#endif
92 
}
93 
 
94 
//---------------------------------------------------------------------------
95 
// Interrupt function support
96 
 
97 
static void
98 
hal_interrupt_set_vectors(void)
99 
{
100 
#if (CYGARC_SH_MOD_INTC == 1)
101 
    // variant specific
102 
    HAL_WRITE_UINT16(CYGARC_REG_VCRDMA0,
103 
                     CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_DMAC0_TE);
104 
    HAL_WRITE_UINT16(CYGARC_REG_VCRDMA1,
105 
                     CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_DMAC1_TE);
106 
    HAL_WRITE_UINT16(CYGARC_REG_VCRWDT,
107 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_WDT_ITI)<<8) |
108 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_REF_CMI));
109 
 
110 
    HAL_WRITE_UINT16(CYGARC_REG_VCRA,
111 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_EDMAC_EINT)<<8);
112 
 
113 
    HAL_WRITE_UINT16(CYGARC_REG_VCRC,
114 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_FRT_ICI)<<8) |
115 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_FRT_OCI));
116 
    HAL_WRITE_UINT16(CYGARC_REG_VCRD,
117 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_FRT_OVI)<<8));
118 
    HAL_WRITE_UINT16(CYGARC_REG_VCRE,
119 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU0_TGI0A)<<8) |
120 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU0_TGI0B));
121 
    HAL_WRITE_UINT16(CYGARC_REG_VCRF,
122 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU0_TGI0C)<<8) |
123 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU0_TGI0D));
124 
    HAL_WRITE_UINT16(CYGARC_REG_VCRG,
125 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU0_TGI0V)<<8));
126 
    HAL_WRITE_UINT16(CYGARC_REG_VCRH,
127 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU1_TGI1A)<<8) |
128 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU1_TGI1B));
129 
    HAL_WRITE_UINT16(CYGARC_REG_VCRI,
130 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU1_TGI1V)<<8) |
131 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU1_TGI1U));
132 
    HAL_WRITE_UINT16(CYGARC_REG_VCRJ,
133 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU2_TGI2A)<<8) |
134 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU2_TGI2B));
135 
    HAL_WRITE_UINT16(CYGARC_REG_VCRK,
136 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU2_TGI2V)<<8) |
137 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU2_TGI2U));
138 
    HAL_WRITE_UINT16(CYGARC_REG_VCRL,
139 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF1_ERI1)<<8) |
140 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF1_RXI1));
141 
    HAL_WRITE_UINT16(CYGARC_REG_VCRM,
142 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF1_BRI1)<<8) |
143 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF1_TXI1));
144 
    HAL_WRITE_UINT16(CYGARC_REG_VCRN,
145 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF2_ERI2)<<8) |
146 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF2_RXI2));
147 
    HAL_WRITE_UINT16(CYGARC_REG_VCRO,
148 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF2_BRI2)<<8) |
149 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF2_TXI2));
150 
    HAL_WRITE_UINT16(CYGARC_REG_VCRP,
151 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO0_RERI0)<<8) |
152 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO0_TERI0));
153 
    HAL_WRITE_UINT16(CYGARC_REG_VCRQ,
154 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO0_RDFI0)<<8) |
155 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO0_TDEI0));
156 
    HAL_WRITE_UINT16(CYGARC_REG_VCRR,
157 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO1_RERI1)<<8) |
158 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO1_TERI1));
159 
    HAL_WRITE_UINT16(CYGARC_REG_VCRS,
160 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO1_RDFI1)<<8) |
161 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO1_TDEI1));
162 
    HAL_WRITE_UINT16(CYGARC_REG_VCRT,
163 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO2_RERI2)<<8) |
164 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO2_TERI2));
165 
    HAL_WRITE_UINT16(CYGARC_REG_VCRU,
166 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO2_RDFI2)<<8) |
167 
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO2_TDEI2));
168 
 
169 
#elif (CYGARC_SH_MOD_INTC == 2)
170 
    /* Hardwired vectors */
171 
#else
172 
# error "No priority handling for INTC variant"
173 
#endif
174 
}
175 
 
176 
externC cyg_uint8 cyg_hal_ILVL_table[];
177 
externC cyg_uint8 cyg_hal_IMASK_table[];
178 
 
179 
static void
180 
hal_interrupt_update_level(int vector)
181 
{
182 
    cyg_uint16 iprX;
183 
    int level;
184 
 
185 
    level = cyg_hal_IMASK_table[vector] ? cyg_hal_ILVL_table[vector] : 0;
186 
 
187 
    switch( (vector) ) {
188 
#if (CYGARC_SH_MOD_INTC == 1)
189 
        /* IPRA */
190 
    case CYGNUM_HAL_INTERRUPT_DMAC0_TE:
191 
    case CYGNUM_HAL_INTERRUPT_DMAC1_TE:
192 
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
193 
        iprX &= ~CYGARC_REG_IPRA_DMAC_MASK;
194 
        iprX |= (level)*CYGARC_REG_IPRA_DMAC_PRI1;
195 
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
196 
        break;
197 
    case CYGNUM_HAL_INTERRUPT_WDT_ITI:
198 
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
199 
        iprX &= ~CYGARC_REG_IPRA_WDT_MASK;
200 
        iprX |= (level)*CYGARC_REG_IPRA_WDT_PRI1;
201 
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
202 
        break;
203 
 
204 
        /* This vector can not be configured */
205 
    case CYGNUM_HAL_INTERRUPT_REF_CMI:
206 
        break;
207 
 
208 
        /* IPRB */
209 
    case CYGNUM_HAL_INTERRUPT_EDMAC_EINT:
210 
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
211 
        iprX &= ~CYGARC_REG_IPRB_EDMAC_MASK;
212 
        iprX |= (level)*CYGARC_REG_IPRB_EDMAC_PRI1;
213 
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
214 
        break;
215 
    case CYGNUM_HAL_INTERRUPT_FRT_ICI:
216 
    case CYGNUM_HAL_INTERRUPT_FRT_OCI:
217 
    case CYGNUM_HAL_INTERRUPT_FRT_OVI:
218 
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
219 
        iprX &= ~CYGARC_REG_IPRB_FRT_MASK;
220 
        iprX |= (level)*CYGARC_REG_IPRB_FRT_PRI1;
221 
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
222 
        break;
223 
 
224 
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
225 
        /* IPRC */
226 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
227 
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
228 
        iprX &= ~CYGARC_REG_IPRC_IRQ0_MASK;
229 
        iprX |= (level)*CYGARC_REG_IPRC_IRQ0_PRI1;
230 
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
231 
        break;
232 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
233 
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
234 
        iprX &= ~CYGARC_REG_IPRC_IRQ1_MASK;
235 
        iprX |= (level)*CYGARC_REG_IPRC_IRQ1_PRI1;
236 
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
237 
        break;
238 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
239 
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
240 
        iprX &= ~CYGARC_REG_IPRC_IRQ2_MASK;
241 
        iprX |= (level)*CYGARC_REG_IPRC_IRQ2_PRI1;
242 
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
243 
        break;
244 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
245 
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
246 
        iprX &= ~CYGARC_REG_IPRC_IRQ3_MASK;
247 
        iprX |= (level)*CYGARC_REG_IPRC_IRQ3_PRI1;
248 
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
249 
        break;
250 
#else
251 
    case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL3:
252 
        /* Cannot change levels */
253 
        break;
254 
#endif
255 
        /* IPRD */
256 
    case CYGNUM_HAL_INTERRUPT_TPU0_TGI0A:
257 
    case CYGNUM_HAL_INTERRUPT_TPU0_TGI0B:
258 
    case CYGNUM_HAL_INTERRUPT_TPU0_TGI0C:
259 
    case CYGNUM_HAL_INTERRUPT_TPU0_TGI0D:
260 
    case CYGNUM_HAL_INTERRUPT_TPU0_TGI0V:
261 
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
262 
        iprX &= ~CYGARC_REG_IPRD_TPU0_MASK;
263 
        iprX |= (level)*CYGARC_REG_IPRD_TPU0_PRI1;
264 
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
265 
        break;
266 
    case CYGNUM_HAL_INTERRUPT_TPU1_TGI1A:
267 
    case CYGNUM_HAL_INTERRUPT_TPU1_TGI1B:
268 
    case CYGNUM_HAL_INTERRUPT_TPU1_TGI1V:
269 
    case CYGNUM_HAL_INTERRUPT_TPU1_TGI1U:
270 
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
271 
        iprX &= ~CYGARC_REG_IPRD_TPU1_MASK;
272 
        iprX |= (level)*CYGARC_REG_IPRD_TPU1_PRI1;
273 
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
274 
        break;
275 
    case CYGNUM_HAL_INTERRUPT_TPU2_TGI2A:
276 
    case CYGNUM_HAL_INTERRUPT_TPU2_TGI2B:
277 
    case CYGNUM_HAL_INTERRUPT_TPU2_TGI2V:
278 
    case CYGNUM_HAL_INTERRUPT_TPU2_TGI2U:
279 
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
280 
        iprX &= ~CYGARC_REG_IPRD_TPU2_MASK;
281 
        iprX |= (level)*CYGARC_REG_IPRD_TPU2_PRI1;
282 
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
283 
        break;
284 
    case CYGNUM_HAL_INTERRUPT_SCIF1_ERI1:
285 
    case CYGNUM_HAL_INTERRUPT_SCIF1_RXI1:
286 
    case CYGNUM_HAL_INTERRUPT_SCIF1_BRI1:
287 
    case CYGNUM_HAL_INTERRUPT_SCIF1_TXI1:
288 
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
289 
        iprX &= ~CYGARC_REG_IPRD_SCIF1_MASK;
290 
        iprX |= (level)*CYGARC_REG_IPRD_SCIF1_PRI1;
291 
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
292 
        break;
293 
 
294 
        /* IPRE */
295 
    case CYGNUM_HAL_INTERRUPT_SCIF2_ERI2:
296 
    case CYGNUM_HAL_INTERRUPT_SCIF2_RXI2:
297 
    case CYGNUM_HAL_INTERRUPT_SCIF2_BRI2:
298 
    case CYGNUM_HAL_INTERRUPT_SCIF2_TXI2:
299 
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
300 
        iprX &= ~CYGARC_REG_IPRE_SCIF2_MASK;
301 
        iprX |= (level)*CYGARC_REG_IPRE_SCIF2_PRI1;
302 
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
303 
        break;
304 
    case CYGNUM_HAL_INTERRUPT_SIO0_RERI0:
305 
    case CYGNUM_HAL_INTERRUPT_SIO0_TERI0:
306 
    case CYGNUM_HAL_INTERRUPT_SIO0_RDFI0:
307 
    case CYGNUM_HAL_INTERRUPT_SIO0_TDEI0:
308 
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
309 
        iprX &= ~CYGARC_REG_IPRE_SIO0_MASK;
310 
        iprX |= (level)*CYGARC_REG_IPRE_SIO0_PRI1;
311 
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
312 
        break;
313 
    case CYGNUM_HAL_INTERRUPT_SIO1_RERI1:
314 
    case CYGNUM_HAL_INTERRUPT_SIO1_TERI1:
315 
    case CYGNUM_HAL_INTERRUPT_SIO1_RDFI1:
316 
    case CYGNUM_HAL_INTERRUPT_SIO1_TDEI1:
317 
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
318 
        iprX &= ~CYGARC_REG_IPRE_SIO1_MASK;
319 
        iprX |= (level)*CYGARC_REG_IPRE_SIO1_PRI1;
320 
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
321 
        break;
322 
    case CYGNUM_HAL_INTERRUPT_SIO2_RERI2:
323 
    case CYGNUM_HAL_INTERRUPT_SIO2_TERI2:
324 
    case CYGNUM_HAL_INTERRUPT_SIO2_RDFI2:
325 
    case CYGNUM_HAL_INTERRUPT_SIO2_TDEI2:
326 
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
327 
        iprX &= ~CYGARC_REG_IPRE_SIO2_MASK;
328 
        iprX |= (level)*CYGARC_REG_IPRE_SIO2_PRI1;
329 
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
330 
        break;
331 
#elif (CYGARC_SH_MOD_INTC == 2)
332 
 
333 
        /* IPRA */
334 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
335 
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
336 
        iprX &= ~CYGARC_REG_IPRA_IRQ0_MASK;
337 
        iprX |= (level)*CYGARC_REG_IPRA_IRQ0_PRI1;
338 
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
339 
        break;
340 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
341 
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
342 
        iprX &= ~CYGARC_REG_IPRA_IRQ1_MASK;
343 
        iprX |= (level)*CYGARC_REG_IPRA_IRQ1_PRI1;
344 
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
345 
        break;
346 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
347 
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
348 
        iprX &= ~CYGARC_REG_IPRA_IRQ2_MASK;
349 
        iprX |= (level)*CYGARC_REG_IPRA_IRQ2_PRI1;
350 
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
351 
        break;
352 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
353 
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
354 
        iprX &= ~CYGARC_REG_IPRA_IRQ3_MASK;
355 
        iprX |= (level)*CYGARC_REG_IPRA_IRQ3_PRI1;
356 
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
357 
        break;
358 
 
359 
        /* IPRB */
360 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
361 
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
362 
        iprX &= ~CYGARC_REG_IPRB_IRQ4_MASK;
363 
        iprX |= (level)*CYGARC_REG_IPRB_IRQ4_PRI1;
364 
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
365 
        break;
366 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
367 
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
368 
        iprX &= ~CYGARC_REG_IPRB_IRQ5_MASK;
369 
        iprX |= (level)*CYGARC_REG_IPRB_IRQ5_PRI1;
370 
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
371 
        break;
372 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ6:
373 
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
374 
        iprX &= ~CYGARC_REG_IPRB_IRQ6_MASK;
375 
        iprX |= (level)*CYGARC_REG_IPRB_IRQ6_PRI1;
376 
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
377 
        break;
378 
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ7:
379 
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
380 
        iprX &= ~CYGARC_REG_IPRB_IRQ7_MASK;
381 
        iprX |= (level)*CYGARC_REG_IPRB_IRQ7_PRI1;
382 
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
383 
        break;
384 
 
385 
        /* IPRB */
386 
    case CYGNUM_HAL_INTERRUPT_DMAC0_DEI0:
387 
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
388 
        iprX &= ~CYGARC_REG_IPRC_DMAC0_MASK;
389 
        iprX |= (level)*CYGARC_REG_IPRC_DMAC0_PRI1;
390 
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
391 
        break;
392 
    case CYGNUM_HAL_INTERRUPT_DMAC1_DEI1:
393 
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
394 
        iprX &= ~CYGARC_REG_IPRC_DMAC1_MASK;
395 
        iprX |= (level)*CYGARC_REG_IPRC_DMAC1_PRI1;
396 
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
397 
        break;
398 
    case CYGNUM_HAL_INTERRUPT_DMAC2_DEI2:
399 
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
400 
        iprX &= ~CYGARC_REG_IPRC_DMAC2_MASK;
401 
        iprX |= (level)*CYGARC_REG_IPRC_DMAC2_PRI1;
402 
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
403 
        break;
404 
    case CYGNUM_HAL_INTERRUPT_DMAC3_DEI3:
405 
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
406 
        iprX &= ~CYGARC_REG_IPRC_DMAC3_MASK;
407 
        iprX |= (level)*CYGARC_REG_IPRC_DMAC3_PRI1;
408 
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
409 
        break;
410 
 
411 
        /* IPRD */
412 
    case CYGNUM_HAL_INTERRUPT_MTU0_TGI0A:
413 
    case CYGNUM_HAL_INTERRUPT_MTU0_TGI0B:
414 
    case CYGNUM_HAL_INTERRUPT_MTU0_TGI0C:
415 
    case CYGNUM_HAL_INTERRUPT_MTU0_TGI0D:
416 
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
417 
        iprX &= ~CYGARC_REG_IPRD_MTU0A_MASK;
418 
        iprX |= (level)*CYGARC_REG_IPRD_MTU0A_PRI1;
419 
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
420 
        break;
421 
    case CYGNUM_HAL_INTERRUPT_MTU0_TGI0V:
422 
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
423 
        iprX &= ~CYGARC_REG_IPRD_MTU0B_MASK;
424 
        iprX |= (level)*CYGARC_REG_IPRD_MTU0B_PRI1;
425 
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
426 
        break;
427 
    case CYGNUM_HAL_INTERRUPT_MTU1_TGI1A:
428 
    case CYGNUM_HAL_INTERRUPT_MTU1_TGI1B:
429 
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
430 
        iprX &= ~CYGARC_REG_IPRD_MTU1A_MASK;
431 
        iprX |= (level)*CYGARC_REG_IPRD_MTU1A_PRI1;
432 
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
433 
        break;
434 
    case CYGNUM_HAL_INTERRUPT_MTU1_TGI1V:
435 
    case CYGNUM_HAL_INTERRUPT_MTU1_TGI1U:
436 
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
437 
        iprX &= ~CYGARC_REG_IPRD_MTU1B_MASK;
438 
        iprX |= (level)*CYGARC_REG_IPRD_MTU1B_PRI1;
439 
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
440 
        break;
441 
 
442 
        /* IPRE */
443 
    case CYGNUM_HAL_INTERRUPT_MTU2_TGI2A:
444 
    case CYGNUM_HAL_INTERRUPT_MTU2_TGI2B:
445 
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
446 
        iprX &= ~CYGARC_REG_IPRE_MTU2A_MASK;
447 
        iprX |= (level)*CYGARC_REG_IPRE_MTU2A_PRI1;
448 
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
449 
        break;
450 
    case CYGNUM_HAL_INTERRUPT_MTU2_TGI2V:
451 
    case CYGNUM_HAL_INTERRUPT_MTU2_TGI2U:
452 
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
453 
        iprX &= ~CYGARC_REG_IPRE_MTU2B_MASK;
454 
        iprX |= (level)*CYGARC_REG_IPRE_MTU2B_PRI1;
455 
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
456 
        break;
457 
    case CYGNUM_HAL_INTERRUPT_MTU3_TGI3A:
458 
    case CYGNUM_HAL_INTERRUPT_MTU3_TGI3B:
459 
    case CYGNUM_HAL_INTERRUPT_MTU3_TGI3C:
460 
    case CYGNUM_HAL_INTERRUPT_MTU3_TGI3D:
461 
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
462 
        iprX &= ~CYGARC_REG_IPRE_MTU3A_MASK;
463 
        iprX |= (level)*CYGARC_REG_IPRE_MTU3A_PRI1;
464 
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
465 
        break;
466 
    case CYGNUM_HAL_INTERRUPT_MTU3_TGI3V:
467 
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
468 
        iprX &= ~CYGARC_REG_IPRE_MTU3B_MASK;
469 
        iprX |= (level)*CYGARC_REG_IPRE_MTU3B_PRI1;
470 
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
471 
        break;
472 
 
473 
        /* IPRF */
474 
    case CYGNUM_HAL_INTERRUPT_MTU4_TGI4A:
475 
    case CYGNUM_HAL_INTERRUPT_MTU4_TGI4B:
476 
    case CYGNUM_HAL_INTERRUPT_MTU4_TGI4C:
477 
    case CYGNUM_HAL_INTERRUPT_MTU4_TGI4D:
478 
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
479 
        iprX &= ~CYGARC_REG_IPRF_MTU4A_MASK;
480 
        iprX |= (level)*CYGARC_REG_IPRF_MTU4A_PRI1;
481 
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
482 
        break;
483 
    case CYGNUM_HAL_INTERRUPT_MTU4_TGI4V:
484 
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
485 
        iprX &= ~CYGARC_REG_IPRF_MTU4B_MASK;
486 
        iprX |= (level)*CYGARC_REG_IPRF_MTU4B_PRI1;
487 
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
488 
        break;
489 
    case CYGNUM_HAL_INTERRUPT_SCI0_ERI0:
490 
    case CYGNUM_HAL_INTERRUPT_SCI0_RXI0:
491 
    case CYGNUM_HAL_INTERRUPT_SCI0_TXI0:
492 
    case CYGNUM_HAL_INTERRUPT_SCI0_TEI0:
493 
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
494 
        iprX &= ~CYGARC_REG_IPRF_SCI0_MASK;
495 
        iprX |= (level)*CYGARC_REG_IPRF_SCI0_PRI1;
496 
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
497 
        break;
498 
    case CYGNUM_HAL_INTERRUPT_SCI1_ERI1:
499 
    case CYGNUM_HAL_INTERRUPT_SCI1_RXI1:
500 
    case CYGNUM_HAL_INTERRUPT_SCI1_TXI1:
501 
    case CYGNUM_HAL_INTERRUPT_SCI1_TEI1:
502 
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
503 
        iprX &= ~CYGARC_REG_IPRF_SCI1_MASK;
504 
        iprX |= (level)*CYGARC_REG_IPRF_SCI1_PRI1;
505 
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
506 
        break;
507 
 
508 
        /* IPRG */
509 
    case CYGNUM_HAL_INTERRUPT_AD_ADI0:
510 
    case CYGNUM_HAL_INTERRUPT_AD_ADI1:
511 
        HAL_READ_UINT16(CYGARC_REG_IPRG, iprX);
512 
        iprX &= ~CYGARC_REG_IPRG_AD_MASK;
513 
        iprX |= (level)*CYGARC_REG_IPRG_AD_PRI1;
514 
        HAL_WRITE_UINT16(CYGARC_REG_IPRG, iprX);
515 
        break;
516 
    case CYGNUM_HAL_INTERRUPT_DTC_SWDTCE:
517 
        HAL_READ_UINT16(CYGARC_REG_IPRG, iprX);
518 
        iprX &= ~CYGARC_REG_IPRG_DTC_MASK;
519 
        iprX |= (level)*CYGARC_REG_IPRG_DTC_PRI1;
520 
        HAL_WRITE_UINT16(CYGARC_REG_IPRG, iprX);
521 
        break;
522 
    case CYGNUM_HAL_INTERRUPT_CMT0_CMI0:
523 
        HAL_READ_UINT16(CYGARC_REG_IPRG, iprX);
524 
        iprX &= ~CYGARC_REG_IPRG_CMT0_MASK;
525 
        iprX |= (level)*CYGARC_REG_IPRG_CMT0_PRI1;
526 
        HAL_WRITE_UINT16(CYGARC_REG_IPRG, iprX);
527 
        break;
528 
    case CYGNUM_HAL_INTERRUPT_CMT1_CMI1:
529 
        HAL_READ_UINT16(CYGARC_REG_IPRG, iprX);
530 
        iprX &= ~CYGARC_REG_IPRG_CMT1_MASK;
531 
        iprX |= (level)*CYGARC_REG_IPRG_CMT1_PRI1;
532 
        HAL_WRITE_UINT16(CYGARC_REG_IPRG, iprX);
533 
        break;
534 
 
535 
        /* IPRH */
536 
    case CYGNUM_HAL_INTERRUPT_WDT_ITI:
537 
    case CYGNUM_HAL_INTERRUPT_BSC_CMI:
538 
        HAL_READ_UINT16(CYGARC_REG_IPRH, iprX);
539 
        iprX &= ~CYGARC_REG_IPRH_WDT_MASK;
540 
        iprX |= (level)*CYGARC_REG_IPRH_WDT_PRI1;
541 
        HAL_WRITE_UINT16(CYGARC_REG_IPRH, iprX);
542 
        break;
543 
    case CYGNUM_HAL_INTERRUPT_IO_OEI:
544 
        HAL_READ_UINT16(CYGARC_REG_IPRH, iprX);
545 
        iprX &= ~CYGARC_REG_IPRH_IO_MASK;
546 
        iprX |= (level)*CYGARC_REG_IPRH_IO_PRI1;
547 
        HAL_WRITE_UINT16(CYGARC_REG_IPRH, iprX);
548 
        break;
549 
 
550 
 
551 
#else
552 
# error "No hal_interrupt_update_level handling for INTC type"
553 
#endif
554 
 
555 
    // Platform extensions
556 
    CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vector, level)
557 
 
558 
    default:
559 
        CYG_FAIL("Unknown interrupt vector");
560 
        break;
561 
    }
562 
}
563 
 
564 
void
565 
hal_interrupt_set_level(int vector, int level)
566 
{
567 
    CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level");
568 
    CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector)
569 
                && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector");
570 
 
571 
    cyg_hal_ILVL_table[vector] = level;
572 
 
573 
    hal_interrupt_update_level(vector);
574 
}
575 
 
576 
void
577 
hal_interrupt_mask(int vector)
578 
{
579 
    switch( (vector) ) {
580 
    case CYGNUM_HAL_INTERRUPT_NMI:
581 
        /* fall through */
582 
    case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL_MAX:
583 
        /* Normally can only be masked by fiddling Imask in SR,
584 
           but some platforms use external interrupt controller,
585 
           so allow regular handling. */
586 
        /* fall through */
587 
#if (CYGARC_SH_MOD_INTC == 1)
588 
    case CYGNUM_HAL_INTERRUPT_DMAC0_TE ... CYGNUM_HAL_ISR_MAX:
589 
#elif (CYGARC_SH_MOD_INTC == 2)
590 
    case CYGNUM_HAL_INTERRUPT_DMAC0_DEI0 ... CYGNUM_HAL_ISR_MAX:
591 
#else
592 
# error "Cannot unmask for INTC"
593 
#endif
594 
        cyg_hal_IMASK_table[vector] = 0;
595 
        hal_interrupt_update_level(vector);
596 
        break;
597 
    default:
598 
        CYG_FAIL("Unknown interrupt vector");
599 
        break;
600 
    }
601 
}
602 
 
603 
void
604 
hal_interrupt_unmask(int vector)
605 
{
606 
    switch( (vector) ) {
607 
    case CYGNUM_HAL_INTERRUPT_NMI:
608 
        /* fall through */
609 
    case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL_MAX:
610 
        /* Normally can only be masked by fiddling Imask in SR,
611 
           but some platforms use external interrupt controller,
612 
           so allow regular handling. */
613 
        /* fall through */
614 
#if (CYGARC_SH_MOD_INTC == 1)
615 
    case CYGNUM_HAL_INTERRUPT_DMAC0_TE ... CYGNUM_HAL_ISR_MAX:
616 
#elif (CYGARC_SH_MOD_INTC == 2)
617 
    case CYGNUM_HAL_INTERRUPT_DMAC0_DEI0 ... CYGNUM_HAL_ISR_MAX:
618 
#else
619 
# error "Cannot unmask for INTC"
620 
#endif
621 
        cyg_hal_IMASK_table[vector] = 1;
622 
        hal_interrupt_update_level(vector);
623 
        break;
624 
    default:
625 
        CYG_FAIL("Unknown interrupt vector");
626 
        break;
627 
    }
628 
}
629 
 
630 
void
631 
hal_interrupt_acknowledge(int vector)
632 
{
633 
#if (CYGARC_SH_MOD_INTC == 1)
634 
    if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
635 
         && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ3) {
636 
 
637 
        cyg_uint8 irqcsr;
638 
 
639 
        HAL_READ_UINT8(CYGARC_REG_IRQCSR, irqcsr);
640 
        switch ( vector ) {
641 
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
642 
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
643 
            irqcsr &= ~CYGARC_REG_IRQCSR_IRQ0F;
644 
            break;
645 
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
646 
            irqcsr &= ~CYGARC_REG_IRQCSR_IRQ1F;
647 
            break;
648 
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
649 
            irqcsr &= ~CYGARC_REG_IRQCSR_IRQ2F;
650 
            break;
651 
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
652 
            irqcsr &= ~CYGARC_REG_IRQCSR_IRQ3F;
653 
            break;
654 
#endif
655 
        default:
656 
            CYG_FAIL("Unhandled interrupt vector");
657 
        }
658 
        HAL_WRITE_UINT8(CYGARC_REG_IRQCSR, irqcsr);
659 
    }
660 
#elif (CYGARC_SH_MOD_INTC == 2)
661 
    if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
662 
         && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ7) {
663 
        cyg_uint16 isr;
664 
        cyg_uint16 mask = ~(1<<(7-(vector - CYGNUM_HAL_INTERRUPT_IRQ_IRQ0)));
665 
 
666 
        HAL_READ_UINT16(CYGARC_REG_ISR, isr);
667 
        isr &= mask;
668 
        HAL_WRITE_UINT16(CYGARC_REG_ISR, isr);
669 
    }
670 
#else
671 
# error "No hal_interrupt_acknowledge code for this INTC"
672 
#endif
673 
 
674 
    CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vector);
675 
}
676 
 
677 
void
678 
hal_interrupt_configure(int vector, int level, int up)
679 
{
680 
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
681 
#if (CYGARC_SH_MOD_INTC == 1)
682 
    if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
683 
         && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ3) {
684 
 
685 
        cyg_uint8 irqcsr, ss, mask;
686 
        ss = 0;
687 
        mask = CYGARC_REG_IRQCSR_IRQ_mask;
688 
        if (level) {
689 
            ss = CYGARC_REG_IRQCSR_IRQ_LOWLEVEL;
690 
            CYG_ASSERT(!(up), "Cannot trigger on high level!");
691 
        } else {
692 
            if (up)
693 
                ss = CYGARC_REG_IRQCSR_IRQ_RISING;
694 
            else
695 
                ss = CYGARC_REG_IRQCSR_IRQ_FALLING;
696 
        }
697 
 
698 
        switch( (vector) ) {
699 
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
700 
            ss <<= CYGARC_REG_IRQCSR_IRQ3_shift;
701 
            mask <<= CYGARC_REG_IRQCSR_IRQ3_shift;
702 
            break;
703 
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
704 
            ss <<= CYGARC_REG_IRQCSR_IRQ2_shift;
705 
            mask <<= CYGARC_REG_IRQCSR_IRQ2_shift;
706 
            break;
707 
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
708 
            ss <<= CYGARC_REG_IRQCSR_IRQ1_shift;
709 
            mask <<= CYGARC_REG_IRQCSR_IRQ1_shift;
710 
            break;
711 
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
712 
            ss <<= CYGARC_REG_IRQCSR_IRQ0_shift;
713 
            mask <<= CYGARC_REG_IRQCSR_IRQ0_shift;
714 
            break;
715 
        default:
716 
            CYG_FAIL("Unhandled interrupt vector");
717 
        }
718 
 
719 
        HAL_READ_UINT8(CYGARC_REG_IRQCSR, irqcsr);
720 
        irqcsr &= ~mask;
721 
        irqcsr |= ss;
722 
        HAL_WRITE_UINT8(CYGARC_REG_IRQCSR, irqcsr);
723 
    }
724 
#endif
725 
#endif
726 
 
727 
    CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vector, level, up);
728 
}
729 
 
730 
//---------------------------------------------------------------------------
731 
void
732 
hal_variant_init(void)
733 
{
734 
    HAL_CLOCK_VAR_INITIALIZE(CYGNUM_HAL_RTC_PERIOD);
735 
 
736 
    hal_interrupt_set_vectors();
737 
}
738 
 
739 
//---------------------------------------------------------------------------
740 
// Low-level delay (in microseconds)
741 
 
742 
#ifdef CYGARC_SH_MOD_FRT
743 
void
744 
hal_delay_us(int usecs)
745 
{
746 
    cyg_uint16 val1, val2;
747 
    cyg_int32 diff, clocks, wrap;
748 
 
749 
    /* Read compare A register */
750 
    HAL_WRITE_UINT8(CYGARC_REG_TOCR, CYGARC_REG_TOCR_OLVLA);
751 
    HAL_READ_UINT16(CYGARC_REG_OCR, val1);
752 
    wrap = (cyg_int32)val1;
753 
 
754 
    clocks = CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/CYGHWR_HAL_SH_RTC_PRESCALE/1000*usecs/1000;
755 
 
756 
    HAL_READ_UINT16(CYGARC_REG_FRC, val1);
757 
    while (clocks > 0) {
758 
        HAL_READ_UINT16(CYGARC_REG_FRC, val2);
759 
 
760 
        diff = (cyg_int32)val1 - (cyg_int32)val2;
761 
        if (diff > 0)
762 
            clocks += (diff-wrap);
763 
        else
764 
            clocks += diff;
765 
 
766 
        val1 = val2;
767 
    }
768 
}
769 
#elif defined(CYGARC_SH_MOD_CMT)
770 
void
771 
hal_delay_us(int usecs)
772 
{
773 
    cyg_uint16 val1, val2;
774 
    cyg_int32 diff, clocks, wrap;
775 
 
776 
    /* Read compare 0 register */
777 
    HAL_READ_UINT16(CYGARC_REG_CMCOR0, val1);
778 
    wrap = (cyg_int32)val1;
779 
 
780 
    clocks = CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/CYGHWR_HAL_SH_RTC_PRESCALE/1000*usecs/1000;
781 
 
782 
    HAL_READ_UINT16(CYGARC_REG_CMCNT0, val1);
783 
    while (clocks > 0) {
784 
        HAL_READ_UINT16(CYGARC_REG_CMCNT0, val2);
785 
 
786 
        diff = (cyg_int32)val1 - (cyg_int32)val2;
787 
        if (diff > 0)
788 
            clocks += (diff-wrap);
789 
        else
790 
            clocks += diff;
791 
 
792 
        val1 = val2;
793 
    }
794 
}
795 
#else
796 
# error "No hal_delay_us implementation"
797 
#endif
798 
 
799 
 
800 
//---------------------------------------------------------------------------
801 
// End of hal_misc.c

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