| 1 |
27 |
unneback |
##==========================================================================
|
| 2 |
|
|
##
|
| 3 |
|
|
## variant.S
|
| 4 |
|
|
##
|
| 5 |
|
|
## SH2 variant assembly code
|
| 6 |
|
|
##
|
| 7 |
|
|
##==========================================================================
|
| 8 |
|
|
#####ECOSGPLCOPYRIGHTBEGIN####
|
| 9 |
|
|
## -------------------------------------------
|
| 10 |
|
|
## This file is part of eCos, the Embedded Configurable Operating System.
|
| 11 |
|
|
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
| 12 |
|
|
##
|
| 13 |
|
|
## eCos is free software; you can redistribute it and/or modify it under
|
| 14 |
|
|
## the terms of the GNU General Public License as published by the Free
|
| 15 |
|
|
## Software Foundation; either version 2 or (at your option) any later version.
|
| 16 |
|
|
##
|
| 17 |
|
|
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
| 18 |
|
|
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 19 |
|
|
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 20 |
|
|
## for more details.
|
| 21 |
|
|
##
|
| 22 |
|
|
## You should have received a copy of the GNU General Public License along
|
| 23 |
|
|
## with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 24 |
|
|
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
| 25 |
|
|
##
|
| 26 |
|
|
## As a special exception, if other files instantiate templates or use macros
|
| 27 |
|
|
## or inline functions from this file, or you compile this file and link it
|
| 28 |
|
|
## with other works to produce a work based on this file, this file does not
|
| 29 |
|
|
## by itself cause the resulting work to be covered by the GNU General Public
|
| 30 |
|
|
## License. However the source code for this file must still be made available
|
| 31 |
|
|
## in accordance with section (3) of the GNU General Public License.
|
| 32 |
|
|
##
|
| 33 |
|
|
## This exception does not invalidate any other reasons why a work based on
|
| 34 |
|
|
## this file might be covered by the GNU General Public License.
|
| 35 |
|
|
##
|
| 36 |
|
|
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
| 37 |
|
|
## at http://sources.redhat.com/ecos/ecos-license/
|
| 38 |
|
|
## -------------------------------------------
|
| 39 |
|
|
#####ECOSGPLCOPYRIGHTEND####
|
| 40 |
|
|
##==========================================================================
|
| 41 |
|
|
#######DESCRIPTIONBEGIN####
|
| 42 |
|
|
##
|
| 43 |
|
|
## Author(s): jskov
|
| 44 |
|
|
## Contributors: jskov
|
| 45 |
|
|
## Date: 2002-01-09
|
| 46 |
|
|
## Purpose: SH2 misc assembly code
|
| 47 |
|
|
######DESCRIPTIONEND####
|
| 48 |
|
|
##
|
| 49 |
|
|
##==========================================================================
|
| 50 |
|
|
|
| 51 |
|
|
#include
|
| 52 |
|
|
#include
|
| 53 |
|
|
|
| 54 |
|
|
#include
|
| 55 |
|
|
#include
|
| 56 |
|
|
|
| 57 |
|
|
#include
|
| 58 |
|
|
|
| 59 |
|
|
#---------------------------------------------------------------------------
|
| 60 |
|
|
# Cache operations
|
| 61 |
|
|
# These need to be written in assembly to ensure they do not rely on data
|
| 62 |
|
|
# in cachable space (i.e., code must use registers exclusively, not the stack).
|
| 63 |
|
|
|
| 64 |
|
|
#if (CYGARC_SH_MOD_CAC == 1)
|
| 65 |
|
|
# This macro must be used at the top of each cache function. It ensures
|
| 66 |
|
|
# that the code gets executed from a shadow region where caching is disabled
|
| 67 |
|
|
# (0x20000000).
|
| 68 |
|
|
.macro GOTO_NONCACHED_SHADOW
|
| 69 |
|
|
mova 10f,r0
|
| 70 |
|
|
mov.l $MASK,r1
|
| 71 |
|
|
and r1,r0
|
| 72 |
|
|
mov.l $BASE,r1
|
| 73 |
|
|
or r1,r0
|
| 74 |
|
|
jmp @r0
|
| 75 |
|
|
nop
|
| 76 |
|
|
.align 2
|
| 77 |
|
|
10:
|
| 78 |
|
|
.endm
|
| 79 |
|
|
|
| 80 |
|
|
FUNC_START(cyg_hal_cache_enable)
|
| 81 |
|
|
GOTO_NONCACHED_SHADOW
|
| 82 |
|
|
mov.l $CYGARC_REG_CCR,r1
|
| 83 |
|
|
mov.b @r1,r0
|
| 84 |
|
|
mov #CYGARC_REG_CCR_CE,r2
|
| 85 |
|
|
or r2,r0
|
| 86 |
|
|
mov.b r0,@r1
|
| 87 |
|
|
nop
|
| 88 |
|
|
rts
|
| 89 |
|
|
nop
|
| 90 |
|
|
|
| 91 |
|
|
FUNC_START(cyg_hal_cache_disable)
|
| 92 |
|
|
GOTO_NONCACHED_SHADOW
|
| 93 |
|
|
mov.l $CYGARC_REG_CCR,r1
|
| 94 |
|
|
mov.b @r1,r0
|
| 95 |
|
|
mov #CYGARC_REG_CCR_CE,r2
|
| 96 |
|
|
not r2,r2
|
| 97 |
|
|
and r2,r0
|
| 98 |
|
|
mov.b r0,@r1
|
| 99 |
|
|
nop
|
| 100 |
|
|
rts
|
| 101 |
|
|
nop
|
| 102 |
|
|
|
| 103 |
|
|
# FIXME: Doc sez we need to disable cache before purging - but only to avoid
|
| 104 |
|
|
# messing with the instruction fetches. Since they happen via the non-cached
|
| 105 |
|
|
# reflection, try to make do without disable/contidional-enable.
|
| 106 |
|
|
FUNC_START(cyg_hal_cache_invalidate_all)
|
| 107 |
|
|
GOTO_NONCACHED_SHADOW
|
| 108 |
|
|
mov.l $CYGARC_REG_CCR,r1
|
| 109 |
|
|
mov.b @r1,r0
|
| 110 |
|
|
mov #CYGARC_REG_CCR_CP,r2
|
| 111 |
|
|
or r2,r0
|
| 112 |
|
|
mov.b r0,@r1
|
| 113 |
|
|
nop ! Nothing in the docs suggest we need
|
| 114 |
|
|
nop ! nops here, but without them, the
|
| 115 |
|
|
nop ! CPU crashes.
|
| 116 |
|
|
rts
|
| 117 |
|
|
nop
|
| 118 |
|
|
|
| 119 |
|
|
# Sync the cache by forcing read-misses twice for each line
|
| 120 |
|
|
# (doing it only once could leave dirty data if it happened
|
| 121 |
|
|
# to coincided with the "flush" area used)
|
| 122 |
|
|
FUNC_START(cyg_hal_cache_sync)
|
| 123 |
|
|
GOTO_NONCACHED_SHADOW
|
| 124 |
|
|
mov.l $CYGARC_REG_CACHE_ADDRESS_BASE,r1
|
| 125 |
|
|
mov.l $CYGARC_REG_CACHE_ADDRESS_TOP,r2
|
| 126 |
|
|
mov.l $CYGARC_REG_CACHE_ADDRESS_STEP,r3
|
| 127 |
|
|
1: cmp/hi r1,r2
|
| 128 |
|
|
bf 2f
|
| 129 |
|
|
mov.l @r1,r0
|
| 130 |
|
|
bra 1b
|
| 131 |
|
|
add r3,r1 ! delay slot!
|
| 132 |
|
|
2: nop
|
| 133 |
|
|
rts
|
| 134 |
|
|
nop
|
| 135 |
|
|
|
| 136 |
|
|
FUNC_START(cyg_hal_cache_write_mode)
|
| 137 |
|
|
GOTO_NONCACHED_SHADOW
|
| 138 |
|
|
# Mode argument in r4.
|
| 139 |
|
|
# Read current state and mask out the caching mode bit
|
| 140 |
|
|
mov.l $CYGARC_REG_CCR,r1
|
| 141 |
|
|
mov.b @r1,r3
|
| 142 |
|
|
mov #CYGARC_REG_CCR_WB,r2
|
| 143 |
|
|
and r2,r4
|
| 144 |
|
|
not r2,r2
|
| 145 |
|
|
and r2,r3
|
| 146 |
|
|
# Or in the new setting and restore to CCR
|
| 147 |
|
|
or r4,r3
|
| 148 |
|
|
mov.b r3,@r1
|
| 149 |
|
|
nop
|
| 150 |
|
|
rts
|
| 151 |
|
|
nop
|
| 152 |
|
|
|
| 153 |
|
|
.align 2
|
| 154 |
|
|
$CYGARC_REG_CACHE_ADDRESS_BASE:
|
| 155 |
|
|
.long 0
|
| 156 |
|
|
$CYGARC_REG_CACHE_ADDRESS_TOP:
|
| 157 |
|
|
.long (HAL_UCACHE_SIZE*2)
|
| 158 |
|
|
$CYGARC_REG_CACHE_ADDRESS_STEP:
|
| 159 |
|
|
.long HAL_UCACHE_LINE_SIZE
|
| 160 |
|
|
$CYGARC_REG_CCR:
|
| 161 |
|
|
.long CYGARC_REG_CCR
|
| 162 |
|
|
|
| 163 |
|
|
$MASK:
|
| 164 |
|
|
.long 0x1fffffff ! mask off top 3 bits
|
| 165 |
|
|
$BASE:
|
| 166 |
|
|
.long 0x20000000 ! base of non-cachable memory
|
| 167 |
|
|
|
| 168 |
|
|
#elif (CYGARC_SH_MOD_CAC == 2)
|
| 169 |
|
|
|
| 170 |
|
|
FUNC_START(cyg_hal_cache_enable)
|
| 171 |
|
|
mov.l $CYGARC_REG_CCR,r1
|
| 172 |
|
|
mov.w @r1,r0
|
| 173 |
|
|
mov #CYGARC_REG_CCR_CE,r2
|
| 174 |
|
|
or r2,r0
|
| 175 |
|
|
mov.w r0,@r1
|
| 176 |
|
|
nop
|
| 177 |
|
|
rts
|
| 178 |
|
|
nop
|
| 179 |
|
|
|
| 180 |
|
|
FUNC_START(cyg_hal_cache_disable)
|
| 181 |
|
|
mov.l $CYGARC_REG_CCR,r1
|
| 182 |
|
|
mov.w @r1,r0
|
| 183 |
|
|
mov #CYGARC_REG_CCR_CE,r2
|
| 184 |
|
|
not r2,r2
|
| 185 |
|
|
and r2,r0
|
| 186 |
|
|
mov.w r0,@r1
|
| 187 |
|
|
nop
|
| 188 |
|
|
rts
|
| 189 |
|
|
nop
|
| 190 |
|
|
|
| 191 |
|
|
FUNC_START(cyg_hal_cache_invalidate_all)
|
| 192 |
|
|
mov.l $CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_BASE,r1
|
| 193 |
|
|
mov.l $CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_TOP,r2
|
| 194 |
|
|
mov #0,r0
|
| 195 |
|
|
1: cmp/eq r1,r2
|
| 196 |
|
|
bt 2f
|
| 197 |
|
|
mov.l r0,@r1
|
| 198 |
|
|
bra 1b
|
| 199 |
|
|
add #4,r1
|
| 200 |
|
|
2: nop
|
| 201 |
|
|
rts
|
| 202 |
|
|
nop
|
| 203 |
|
|
|
| 204 |
|
|
.align 2
|
| 205 |
|
|
$CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_BASE:
|
| 206 |
|
|
.long CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_BASE
|
| 207 |
|
|
$CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_TOP:
|
| 208 |
|
|
.long CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_TOP
|
| 209 |
|
|
$CYGARC_REG_CCR:
|
| 210 |
|
|
.long CYGARC_REG_CCR
|
| 211 |
|
|
#else
|
| 212 |
|
|
# error "No cache operators for INTC type"
|
| 213 |
|
|
#endif
|
| 214 |
|
|
.data
|
| 215 |
|
|
|
| 216 |
|
|
SYM_DEF(cyg_hal_ILVL_table)
|
| 217 |
|
|
# The first entries in the table have static priorities.
|
| 218 |
|
|
|
| 219 |
|
|
.byte 0xf // NMI
|
| 220 |
|
|
.byte 0xf // LVL0
|
| 221 |
|
|
.byte 0xe // LVL1
|
| 222 |
|
|
.byte 0xd // LVL2
|
| 223 |
|
|
.byte 0xc // LVL3
|
| 224 |
|
|
.byte 0xb // LVL4
|
| 225 |
|
|
.byte 0xa // LVL5
|
| 226 |
|
|
.byte 0x9 // LVL6
|
| 227 |
|
|
.byte 0x8 // LVL7
|
| 228 |
|
|
#ifdef CYGNUM_HAL_INTERRUPT_LVL14
|
| 229 |
|
|
.byte 0x7 // LVL8
|
| 230 |
|
|
.byte 0x6 // LVL9
|
| 231 |
|
|
.byte 0x5 // LVL10
|
| 232 |
|
|
.byte 0x4 // LVL11
|
| 233 |
|
|
.byte 0x3 // LVL12
|
| 234 |
|
|
.byte 0x2 // LVL13
|
| 235 |
|
|
.byte 0x1 // LVL14
|
| 236 |
|
|
#endif
|
| 237 |
|
|
|
| 238 |
|
|
# The rest of the table consists of programmable levels, maintained
|
| 239 |
|
|
# by the HAL_INTERRUPT_SET_LEVEL macro.
|
| 240 |
|
|
# These default to the highest level so that a spurious
|
| 241 |
|
|
# interrupt cause the IPL to be suddenly lowered to allow all
|
| 242 |
|
|
# interrupts. This should give a better chance at tracking down
|
| 243 |
|
|
# the problem.
|
| 244 |
|
|
.rept (CYGNUM_HAL_ISR_MAX- CYGNUM_HAL_INTERRUPT_LVL_MAX)
|
| 245 |
|
|
.byte 0xf
|
| 246 |
|
|
.endr
|
| 247 |
|
|
|
| 248 |
|
|
# All interrupts are masked initally. Set to 1 to enable.
|
| 249 |
|
|
SYM_DEF(cyg_hal_IMASK_table)
|
| 250 |
|
|
.rept (CYGNUM_HAL_ISR_MAX)
|
| 251 |
|
|
.byte 0x0
|
| 252 |
|
|
.endr
|
