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//=============================================================================
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//
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// mod_regs_cpg.h
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//
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// CPG (clock pulse generator) Module register definitions
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors:jskov
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// Date: 2000-10-30
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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//--------------------------------------------------------------------------
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// Oscillator control registers
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#define CYGARC_REG_FRQCR 0xffffff80
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#define CYGARC_REG_WTCNT 0xffffff84 // read 8bit, write 16bit
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#define CYGARC_REG_WTCSR 0xffffff86 // read 8bit, write 16bit
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#define CYGARC_REG_WTCNT_WRITE 0x5a00 // top 8bit value for write
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#define CYGARC_REG_WTCSR_WRITE 0xa500 // top 8bit value for write
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#define CYGARC_REG_WTCSR_TME 0x80 // timer enable
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#define CYGARC_REG_WTCSR_WT_IT 0x40 // watchdog(1)/interval(0)
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#define CYGARC_REG_WTCSR_RSTS 0x20 // manual(1)/poweron(0)
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#define CYGARC_REG_WTCSR_WOVF 0x10 // watchdog overflow
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#define CYGARC_REG_WTCSR_IOVF 0x08 // interval overflow
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#define CYGARC_REG_WTCSR_CKS2 0x04 // clock select 2
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#define CYGARC_REG_WTCSR_CKS1 0x02 // clock select 1
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#define CYGARC_REG_WTCSR_CKS0 0x01 // clock select 0
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#define CYGARC_REG_WTCSR_CKSx_MASK 0x07 // clock select mask
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// This is the period (in us) between watchdog reset and overflow.
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// Note: We use max timeout delay for now.
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#define CYGARC_REG_WTCSR_CKSx_SETTING 0x07 // max delay
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#define CYGARC_REG_WTCSR_PERIOD ((1000000000/(CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/4096))*256)
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// Translate various CDL clock configurations to register equivalents
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// for the various CPG versions
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#if (CYGARC_SH_MOD_CPG == 1) // ---------------------------- V1
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// PLL1
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#if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) || (CYGHWR_HAL_SH_OOC_PLL_1 == 1)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x0000
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#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 2)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x0010
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#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x0020
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#else
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# error "Unsupported PLL1 setting"
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#endif
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// Divider1
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#if (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0000
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 2)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0004
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 4)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0008
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#else
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# error "Unsupported Divider1 setting"
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#endif
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// Divider2
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#if (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 1)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0000
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 2)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0001
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 4)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0002
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#else
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# error "Unsupported Divider1 setting"
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#endif
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// CKOEN - set in all modes but 7
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#if (CYGHWR_HAL_SH_OOC_CLOCK_MODE != 7)
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# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0100
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#else
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# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000
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#endif
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#elif (CYGARC_SH_MOD_CPG == 2) // ---------------------------- V2
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// PLL1
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#if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) || (CYGHWR_HAL_SH_OOC_PLL_1 == 1)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x0000
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#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 2)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x0010
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#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x0020
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#else
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# error "Unsupported PLL1 setting"
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#endif
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// Divider1
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#if (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0000
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 2)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0004
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 4)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0008
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#else
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# error "Unsupported Divider1 setting"
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#endif
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// Divider2
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#if (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 1)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0000
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 2)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0001
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 4)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0002
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#else
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# error "Unsupported Divider1 setting"
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#endif
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// CKOEN - set in all modes but 2
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#if (CYGHWR_HAL_SH_OOC_CLOCK_MODE != 2)
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# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0100
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#else
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# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000
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#endif
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#elif (CYGARC_SH_MOD_CPG == 3) // ---------------------------- V3
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// PLL1
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#if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) || (CYGHWR_HAL_SH_OOC_PLL_1 == 1)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x0000
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#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 2)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x0010
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#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 3)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x8000
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#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x0020
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#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 6)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x8010
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#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 8)
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# define CYGARC_REG_FRQCR_INIT_PLL1 0x0030
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#else
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# error "Unsupported PLL1 setting"
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#endif
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// Divider1
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#if (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0000
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 2)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0004
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 3)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x4000
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 4)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0008
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#else
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# error "Unsupported Divider1 setting"
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#endif
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// Divider2
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#if (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 1)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0000
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 2)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0001
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 3)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2000
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 4)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0002
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#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 6)
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# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2002
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#else
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# error "Unsupported Divider2 setting"
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#endif
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// CKOEN - set in modes 0-2
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#if (CYGHWR_HAL_SH_OOC_CLOCK_MODE <= 2)
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# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0100
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#else
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# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000
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#endif
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#else
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# error "Unsupported CPG version"
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#endif
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// Init value
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#define CYGARC_REG_FRQCR_INIT (CYGARC_REG_FRQCR_INIT_PLL1|CYGARC_REG_FRQCR_INIT_DIVIDER1|CYGARC_REG_FRQCR_INIT_DIVIDER2|CYGARC_REG_FRQCR_INIT_CKOEN)
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