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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sh/] [sh4/] [v2_0/] [include/] [mod_regs_dma.h] - Blame information for rev 773

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//=============================================================================
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//
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//      mod_regs_dma.h
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//
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//      DMA (direct memory access) Module register definitions
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):   jskov
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// Contributors:jskov
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// Date:        2000-10-30
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//              
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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//--------------------------------------------------------------------------
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// DMA Controller registers
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#define CYGARC_REG_SAR0                 0xa4000020
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#define CYGARC_REG_DAR0                 0xa4000024
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#define CYGARC_REG_DMATCR0              0xa4000028
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#define CYGARC_REG_CHCR0                0xa400002c
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#define CYGARC_REG_SAR1                 0xa4000030
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#define CYGARC_REG_DAR1                 0xa4000034
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#define CYGARC_REG_DMATCR1              0xa4000038
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#define CYGARC_REG_CHCR1                0xa400003c
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#define CYGARC_REG_SAR2                 0xa4000040
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#define CYGARC_REG_DAR2                 0xa4000044
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#define CYGARC_REG_DMATCR2              0xa4000048
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#define CYGARC_REG_CHCR2                0xa400004c
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#define CYGARC_REG_SAR3                 0xa4000050
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#define CYGARC_REG_DAR3                 0xa4000054
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#define CYGARC_REG_DMATCR3              0xa4000058
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#define CYGARC_REG_CHCR3                0xa400005c
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#define CYGARC_REG_DMAOR                0xa4000060
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// Offsets from base register
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#define CYGARC_REG_SAR                  0x00
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#define CYGARC_REG_DAR                  0x04
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#define CYGARC_REG_DMATCR               0x08
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#define CYGARC_REG_CHCR                 0x0c
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// DMA Channel Control Register. If there's a digit suffix to CHCR the flag
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// is only valid in the listed channels.
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#define CYGARC_REG_CHCR3_DI             0x00100000 // direct/indirect selection
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#define CYGARC_REG_CHCR2_RO             0x00080000 // source address reload
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#define CYGARC_REG_CHCR01_RL            0x00040000 // request check level
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#define CYGARC_REG_CHCR01_AM            0x00020000 // acknowledge mode
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#define CYGARC_REG_CHCR01_AL            0x00010000 // acknowledge level
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#define CYGARC_REG_CHCR_DM1             0x00008000 // destination address mode
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#define CYGARC_REG_CHCR_DM0             0x00004000
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#define CYGARC_REG_CHCR_SM1             0x00002000 // source address mode
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#define CYGARC_REG_CHCR_SM0             0x00001000
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#define CYGARC_REG_CHCR_RS3             0x00000800 // resource select
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#define CYGARC_REG_CHCR_RS2             0x00000400
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#define CYGARC_REG_CHCR_RS1             0x00000200
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#define CYGARC_REG_CHCR_RS0             0x00000100
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#define CYGARC_REG_CHCR01_DS            0x00000040 // DREQ select
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#define CYGARC_REG_CHCR_TM              0x00000020 // transmit mode
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#define CYGARC_REG_CHCR_TS1             0x00000010 // transmit size
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#define CYGARC_REG_CHCR_TS0             0x00000008
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#define CYGARC_REG_CHCR_IE              0x00000004 // interrupt enable
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#define CYGARC_REG_CHCR_TE              0x00000002 // transfer end
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#define CYGARC_REG_CHCR_DE              0x00000001 // DMAC enable
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// Resource select options
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#define CYGARC_REG_CHCR_RS_EXT_DUAL     0x00000000
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#define CYGARC_REG_CHCR_RS_EXT_EX_DAC   0x00000100
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#define CYGARC_REG_CHCR_RS_EXT_DAC_EX   0x00000300
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#define CYGARC_REG_CHCR_RS_AUTO         0x00000400
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#define CYGARC_REG_CHCR_RS_IRDA_TX      0x00000a00
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#define CYGARC_REG_CHCR_RS_IRDA_RX      0x00000b00
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#define CYGARC_REG_CHCR_RS_SCIF_TX      0x00000c00
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#define CYGARC_REG_CHCR_RS_SCIF_RX      0x00000d00
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#define CYGARC_REG_CHCR_RS_AD           0x00000e00
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#define CYGARC_REG_CHCR_RS_CMT          0x00000f00
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// DMA Operation Register
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#define CYGARC_REG_DMAOR_PR1            0x0200     // priority level
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#define CYGARC_REG_DMAOR_PR0            0x0100
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#define CYGARC_REG_DMAOR_AE             0x0004     // address error flag
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#define CYGARC_REG_DMAOR_NMIF           0x0002     // NMI flag
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#define CYGARC_REG_DMAOR_DME            0x0001     // DMA master enable

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