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#ifndef CYGONCE_HAL_VARIANT_INC
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#define CYGONCE_HAL_VARIANT_INC
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##=============================================================================
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##
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## variant.inc
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##
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## SH4 variant assembler header file
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): jskov
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## Contributors:jskov
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## Date: 2000-10-30
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## Purpose: SH4 variant definitions and init code
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## Description: This file contains various definitions and macros that are
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## useful for writing assembly code for the SH3 CPU family.
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## Usage:
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## #include
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## ...
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##
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#include
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#===========================================================================
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## SR initialization value
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## zero all bits except:
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## MD = Processor operation mode field (privileged mode)
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## I0-3 = Mask out all interrupts but NMI.
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##
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## When saving or restoring the state of an exception or interrupt, the bit
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## CYGARC_REG_SR_RB is also set, switching the register bank. When this bit
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## is set, interrupts must be disabled.
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##
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## Note: We could also use the BL bit to prevent interrupts, but that would
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## also prevent the use of breakpoints.
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#define CYG_SR (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK)
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#define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB)
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##-----------------------------------------------------------------------------
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## Hardware init macros
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#ifndef CYGPKG_HAL_SH_POST_RESET_INIT
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.macro hal_post_reset_init
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# Initialize CPU
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mov.l $nCYG_SR,r1 ! Put CPU in a well-known state
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ldc r1,sr
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mov #0,r0
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mov.l $nCYGARC_REG_CCR,r1 ! Disable cache
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mov.l r0,@r1
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mov.l $nCYGARC_REG_MMUCR,r1 ! Disable MMU
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mov.l r0,@r1
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mov.l $nCYGARC_REG_BBRA,r1 ! Disable UBC Channel A
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mov.w r0,@r1
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mov.l $nCYGARC_REG_BBRB,r1 ! Disable UBC Channel B
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mov.w r0,@r1
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mov.l $nCYGARC_REG_BRCR,r1 ! Reset UBC common register
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mov.w r0,@r1
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mov.l $CYGARC_REG_TSTR,r1 ! Disable timers
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mov.b r0,@r1
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mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources
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mov.w r0,@r1
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mov.l $CYGARC_REG_IPRB,r1
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mov.w r0,@r1
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mov.l $CYGARC_REG_IPRC,r1
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mov.w r0,@r1
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#if (CYGARC_SH_MOD_INTC == 2)
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mov.l $CYGARC_REG_IPRD,r1
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mov.w r0,@r1
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#endif
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mov.w $nCYG_WTCSR,r0 ! Clear watchdog
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mov.l $nCYGARC_REG_WTCSR,r1
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mov.w r0,@r1
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mov.w $nCYG_ICR_INIT,r0
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mov.l $CYGARC_REG_ICR,r1 ! Set interrupt controller to IRQ mode
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mov.w r0,@r1
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# Initialize VBR if necessary
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#if !defined(CYG_HAL_STARTUP_RAM) || \
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( defined(CYG_HAL_STARTUP_RAM) && \
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!defined(CYGSEM_HAL_USE_ROM_MONITOR))
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mov.l $_reset,r1 ! Set VBR
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ldc r1,vbr
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#endif
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bra 1f
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nop
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$nCYG_WTCSR:
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.word 0xa500 ! clear all CSR bits
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.align 2
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$nCYG_SR:
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.long CYG_SR
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$nCYGARC_REG_CCR:
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.long CYGARC_REG_CCR
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$nCYGARC_REG_MMUCR:
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.long CYGARC_REG_MMUCR
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$nCYGARC_REG_BBRA:
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.long CYGARC_REG_BBRA
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$nCYGARC_REG_BBRB:
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.long CYGARC_REG_BBRB
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$nCYGARC_REG_BRCR:
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.long CYGARC_REG_BRCR
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$CYGARC_REG_TSTR:
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.long CYGARC_REG_TSTR
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$CYGARC_REG_IPRA:
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.long CYGARC_REG_IPRA
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$CYGARC_REG_IPRB:
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.long CYGARC_REG_IPRB
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$CYGARC_REG_IPRC:
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.long CYGARC_REG_IPRC
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#if (CYGARC_SH_MOD_INTC == 2)
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$CYGARC_REG_IPRD:
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.long CYGARC_REG_IPRD
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#endif
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$nCYGARC_REG_WTCSR:
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.long CYGARC_REG_WTCSR
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$CYGARC_REG_ICR:
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.long CYGARC_REG_ICR
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SYM_PTR_REF(_reset)
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# Data below only need word alignment
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$nCYG_ICR_INIT:
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.word CYGARC_REG_ICR_INIT
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1:
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.endm
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#define CYGPKG_HAL_SH_POST_RESET_INIT
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#endif
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##-----------------------------------------------------------------------------
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## Interrupt decode macros
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.macro hal_intc_decode tmp,inum
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mov.l 1f,\tmp
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mov.l @\tmp,\inum
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mov #-5,\tmp ! divide cause by 0x20
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shld \tmp,\inum
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bra 2f
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add #-14,\inum ! adjust so NMI becomes 0
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.align 2
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1: .long CYGARC_REG_INTEVT
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2:
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.endm
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#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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.macro hal_intc_translate inum,vnum
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mov #0,\vnum ! Just vector zero is supported
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.endm
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#else
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.macro hal_intc_translate inum,vnum
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mov \inum,\vnum ! Vector == interrupt number
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shll2 \vnum ! get from vector number to ISR index
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.endm
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#endif
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#------------------------------------------------------------------------------
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#endif // CYGONCE_HAL_VARIANT_INC
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# end of variant.inc
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