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/*=============================================================================
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//
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// vectors.S
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//
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// SPARC vectors and bootup code
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt
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// Contributors:hmt
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// Date: 1998-12-15
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// Purpose: SPARC vector code
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// Description: This file contains the code which hangs off SPARC vectors
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// including reset; it handles register under/overflow as well
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// as bootup, anything else is deferred to the default interrupt
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// or exception vsrs respectively. See vec_[ix]vsr.S ...
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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!-----------------------------------------------------------------------------
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// .file "vectors.S"
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!-----------------------------------------------------------------------------
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#include
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#include
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#include
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#include CYGBLD_HAL_PLATFORM_H // Platform config file
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#ifdef CYGPKG_KERNEL
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# include
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#else
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# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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#endif
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#if defined( CYGPKG_HAL_SPARCLITE_SIM ) || \
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defined( CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK ) || \
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defined( CYGPKG_HAL_SPARC_LEON ) || \
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defined( CYGPKG_HAL_SPARC_ERC32 )
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#define BOOTUPSTACK_IS_INTERRUPTSTACK
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#endif
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//#define CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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#ifndef CYGHWR_HAL_SPARC_HAS_ASR17
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#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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#error Single Vector Trapping (SVT) demands ASR17
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#endif
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#endif
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#ifdef CYG_HAL_STARTUP_ROM
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# ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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! ROM startup and Single Vector Trapping demands a copy to RAM.
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! Otherwise it may be configured in, but it is not required.
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# ifndef CYGIMP_HAL_SPARC_COPY_VECTORS_TO_RAM
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# define CYGIMP_HAL_SPARC_COPY_VECTORS_TO_RAM
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# endif
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# endif
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#endif
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!------------------------------------------------------------------------
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#include
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#define DELAYS_AFTER_WRPSR_SAME_WINDOW
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#define DELAYS_AFTER_WRWIM
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!------------------------------------------------------------------------
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#ifdef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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.macro VECTOR_EXCEPTION
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.p2align 4
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rd %tbr, %l3
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rd %psr, %l0
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ba __entry_exception
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and %l3, TT_MASK, %l4
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.endm
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.macro VECTOR_INTERRUPT level
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.p2align 4
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rd %psr, %l0
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mov \level << 2, %l5
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ba __entry_interrupt
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mov \level << 4, %l4
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.endm
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.macro VECTOR_CODE_WIM name
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.p2align 4
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ba __entry_\name
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rd %wim, %l0
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.endm
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#endif // CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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!------------------------------------------------------------------------
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! The start of the code; this is the entry point:
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.section ".vectors","ax"
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.global rom_vectors
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rom_vectors:
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.global reset_vector
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reset_vector:
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! this code goes to the real reset handler, it will be
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! overwritten by the start of vectoring handler...
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b genuine_reset
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nop
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! usually drop through to:
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#ifdef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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ba __entry_exception ! reset becomes an exception
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and %l3, TT_MASK, %l4 ! once we are running
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VECTOR_EXCEPTION ! 1
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VECTOR_EXCEPTION ! 2
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VECTOR_EXCEPTION ! 3
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VECTOR_EXCEPTION ! 4
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VECTOR_CODE_WIM wover ! 5 window overflow
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VECTOR_CODE_WIM wunder ! 6 window underflow
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VECTOR_EXCEPTION ! 7
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VECTOR_EXCEPTION ! 8
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VECTOR_EXCEPTION ! 9
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VECTOR_EXCEPTION ! 10
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VECTOR_EXCEPTION ! 11
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VECTOR_EXCEPTION ! 12
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VECTOR_EXCEPTION ! 13
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VECTOR_EXCEPTION ! 14
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VECTOR_EXCEPTION ! 15
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VECTOR_EXCEPTION ! 16
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VECTOR_INTERRUPT 1 ! 17 interrupt_level_1
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VECTOR_INTERRUPT 2 ! 18 interrupt_level_2
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VECTOR_INTERRUPT 3 ! 19 interrupt_level_3
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VECTOR_INTERRUPT 4 ! 20 interrupt_level_4
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VECTOR_INTERRUPT 5 ! 21 interrupt_level_5
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VECTOR_INTERRUPT 6 ! 22 interrupt_level_6
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VECTOR_INTERRUPT 7 ! 23 interrupt_level_7
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VECTOR_INTERRUPT 8 ! 24 interrupt_level_8
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VECTOR_INTERRUPT 9 ! 25 interrupt_level_9
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VECTOR_INTERRUPT 10 ! 26 interrupt_level_10
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VECTOR_INTERRUPT 11 ! 27 interrupt_level_11
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VECTOR_INTERRUPT 12 ! 28 interrupt_level_12
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VECTOR_INTERRUPT 13 ! 29 interrupt_level_13
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VECTOR_INTERRUPT 14 ! 30 interrupt_level_14
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VECTOR_INTERRUPT 15 ! 31 interrupt_level_15
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VECTOR_EXCEPTION ! 32
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VECTOR_EXCEPTION ! 33
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VECTOR_EXCEPTION ! 34
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VECTOR_EXCEPTION ! 35
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VECTOR_EXCEPTION ! 36
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VECTOR_EXCEPTION ! 37
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VECTOR_EXCEPTION ! 38
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VECTOR_EXCEPTION ! 39
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| 203 |
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.rept 216 ! 40-255 is 216 of them
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VECTOR_EXCEPTION ! whichever
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.endr
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#endif // CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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real_vector:
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! here,locals have been set up as follows:
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! %l0 = psr
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! %l1 = pc
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! %l2 = npc
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! %l3 = tbr
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and %l3, TT_IS_INTR_MASK, %l4
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cmp %l4, TT_IS_INTR_VALUE
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bne not_an_interrupt ! delay slot does not matter
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! here be the pre-vector interrupt handler
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interrupt:
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and %l3, 0x0f0, %l4 ! get an interrupt number out
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srl %l4, 2, %l5 ! to a word address offset
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#endif // !CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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__entry_interrupt:
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sethi %hi(hal_vsr_table), %l6
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or %l6, %lo(hal_vsr_table), %l6
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ld [ %l6 + %l5 ], %l6 ! get vector in %l6
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jmp %l6 ! and go there
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srl %l4, 4, %l3 ! vector number into %l3: so that
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! interrupts and exceptions/traps
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! have the same API to VSRs
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| 231 |
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#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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not_an_interrupt:
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and %l3, TT_MASK, %l4
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cmp %l4, (TRAP_WUNDER << TT_SHL)
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bne,a not_window_underflow
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cmp %l4, (TRAP_WOVER << TT_SHL) ! (if taken)
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! here be the window underflow handler:
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| 241 |
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window_underflow:
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| 242 |
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! CWP is trap handler
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| 243 |
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! CWP + 1 is trapped RESTORE instruction
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! CWP + 2 is invalid context which must be restored
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! CWP + 3 is next invalid context
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| 247 |
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wr %l0, %psr ! restore the condition flags
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! (CWP is unchanged)
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| 249 |
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! the following instructions delay enough; no need for NOPs
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| 250 |
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rd %wim, %l0 ! get the wim
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| 251 |
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#endif // !CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
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| 252 |
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__entry_wunder:
|
| 253 |
|
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sll %l0, 1, %l3 ! Rotate wim left
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| 254 |
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srl %l0, __WINSIZE-1, %l0
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| 255 |
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wr %l0, %l3, %wim ! Install the new wim
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| 256 |
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|
| 257 |
|
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#ifdef DELAYS_AFTER_WRWIM
|
| 258 |
|
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nop ! are these delays needed?
|
| 259 |
|
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nop ! (following restore uses wim)
|
| 260 |
|
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nop
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| 261 |
|
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#endif
|
| 262 |
|
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restore ! Users window
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| 263 |
|
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restore ! Her callers window (now valid)
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| 264 |
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|
| 265 |
|
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ldd [%sp + 0 * 4], %l0 ! restore L & I registers
|
| 266 |
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ldd [%sp + 2 * 4], %l2
|
| 267 |
|
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ldd [%sp + 4 * 4], %l4
|
| 268 |
|
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ldd [%sp + 6 * 4], %l6
|
| 269 |
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|
|
| 270 |
|
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ldd [%sp + 8 * 4], %i0
|
| 271 |
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ldd [%sp + 10 * 4], %i2
|
| 272 |
|
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ldd [%sp + 12 * 4], %i4
|
| 273 |
|
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ldd [%sp + 14 * 4], %i6
|
| 274 |
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|
| 275 |
|
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save ! Back to trap window
|
| 276 |
|
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save
|
| 277 |
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|
| 278 |
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jmp %l1
|
| 279 |
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rett %l2
|
| 280 |
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|
| 281 |
|
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#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
|
| 282 |
|
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not_window_underflow:
|
| 283 |
|
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bne,a not_window_overflow
|
| 284 |
|
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srl %l4, 4, %l4 ! (if taken)
|
| 285 |
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|
|
| 286 |
|
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! here be the window overflow handler:
|
| 287 |
|
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window_overflow:
|
| 288 |
|
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! CWP + 1 is caller whose SAVE bounced
|
| 289 |
|
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! CWP is trap handler = invalid window
|
| 290 |
|
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! CWP - 1 is next invalid window which needs to be saved
|
| 291 |
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|
| 292 |
|
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wr %l0, %psr ! restore the condition flags
|
| 293 |
|
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! (CWP is unchanged)
|
| 294 |
|
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! the following instructions delay enough; no need for NOPs
|
| 295 |
|
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rd %wim, %l0
|
| 296 |
|
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#endif // !CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
|
| 297 |
|
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__entry_wover:
|
| 298 |
|
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mov %g1, %l3 ! Save g1, we use it to hold the wim
|
| 299 |
|
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srl %l0, 1, %g1 ! Rotate wim right
|
| 300 |
|
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sll %l0, __WINSIZE-1, %l0
|
| 301 |
|
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or %l0, %g1, %g1
|
| 302 |
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|
| 303 |
|
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save ! Slip into next window
|
| 304 |
|
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mov %g1, %wim ! Install the new wim
|
| 305 |
|
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! (invalidates current window!)
|
| 306 |
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|
|
| 307 |
|
|
std %l0, [%sp + 0 * 4] ! save L & I registers
|
| 308 |
|
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std %l2, [%sp + 2 * 4]
|
| 309 |
|
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std %l4, [%sp + 4 * 4]
|
| 310 |
|
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std %l6, [%sp + 6 * 4]
|
| 311 |
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|
| 312 |
|
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std %i0, [%sp + 8 * 4]
|
| 313 |
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std %i2, [%sp + 10 * 4]
|
| 314 |
|
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std %i4, [%sp + 12 * 4]
|
| 315 |
|
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std %i6, [%sp + 14 * 4]
|
| 316 |
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|
| 317 |
|
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restore ! Go back to trap window.
|
| 318 |
|
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mov %l3, %g1 ! Restore %g1
|
| 319 |
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|
|
| 320 |
|
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jmpl %l1, %g0
|
| 321 |
|
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rett %l2
|
| 322 |
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|
| 323 |
|
|
#ifdef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
|
| 324 |
|
|
// ADDITIONAL code to provide an entry point:
|
| 325 |
|
|
__entry_exception:
|
| 326 |
|
|
srl %l4, 4, %l4
|
| 327 |
|
|
#endif // CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
|
| 328 |
|
|
not_window_overflow:
|
| 329 |
|
|
! from here on in, %l4 is the trap number in clear
|
| 330 |
|
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cmp %l4, 128
|
| 331 |
|
|
bge 1f
|
| 332 |
|
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mov 0, %l5 ! offset 0 for user traps
|
| 333 |
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|
|
| 334 |
|
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cmp %l4, 36 ! coprocessor special case
|
| 335 |
|
|
beq 1f
|
| 336 |
|
|
mov 4, %l5 ! ...treated as FP, code 4
|
| 337 |
|
|
|
| 338 |
|
|
cmp %l4, 10
|
| 339 |
|
|
bge 1f
|
| 340 |
|
|
mov 10, %l5 ! offset 10 for "others"
|
| 341 |
|
|
|
| 342 |
|
|
! if we are here, the trap number is 1-9 inclusive
|
| 343 |
|
|
! so put it in %l5 and drop through...
|
| 344 |
|
|
mov %l4, %l5
|
| 345 |
|
|
1:
|
| 346 |
|
|
or %l5, 16, %l5 ! offset into table is 16... for traps.
|
| 347 |
|
|
sll %l5, 2, %l5 ! to a word address offset
|
| 348 |
|
|
sethi %hi(hal_vsr_table), %l6
|
| 349 |
|
|
or %l6, %lo(hal_vsr_table), %l6
|
| 350 |
|
|
ld [ %l6 + %l5 ], %l6 ! get vector in %l6
|
| 351 |
|
|
jmp %l6 ! and go there
|
| 352 |
|
|
srl %l5, 2, %l3 ! vector number into %l3: so that
|
| 353 |
|
|
! interrupts and exceptions/traps
|
| 354 |
|
|
! have the same API to VSRs
|
| 355 |
|
|
! NB that~s eCos vector number not TRAP number above.
|
| 356 |
|
|
|
| 357 |
|
|
! and that is the end of the pre-vector trap handler
|
| 358 |
|
|
|
| 359 |
|
|
.global rom_vectors_end
|
| 360 |
|
|
rom_vectors_end:
|
| 361 |
|
|
|
| 362 |
|
|
! these instructions are copied into the reset vector
|
| 363 |
|
|
! after startup to _not_ branch to the genuine_reset code below
|
| 364 |
|
|
real_vector_instructions:
|
| 365 |
|
|
rd %tbr, %l3
|
| 366 |
|
|
rd %psr, %l0
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
|
| 370 |
|
|
! genuine reset code called from time zero:
|
| 371 |
|
|
genuine_reset: ! set psr, mask interrupts & traps
|
| 372 |
|
|
sethi %hi(reset_vector), %g1
|
| 373 |
|
|
andn %g1, 0xfff, %g1 ! should not be needed
|
| 374 |
|
|
wr %g1, %tbr ! Traps are at reset_vector
|
| 375 |
|
|
wr %g0, 0xfc0 + __WIN_INIT, %psr ! mode = prevMode = S, CWP=7
|
| 376 |
|
|
wr %g0, 0, %wim ! No invalid windows (yet)
|
| 377 |
|
|
#ifdef CYGHWR_HAL_SPARC_HAS_ASR17
|
| 378 |
|
|
#ifdef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
|
| 379 |
|
|
wr %g0, 0, %asr17 ! Multiple vector trapping
|
| 380 |
|
|
#else
|
| 381 |
|
|
wr %g0, 1, %asr17 ! Single vector trapping
|
| 382 |
|
|
#endif // !CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
|
| 383 |
|
|
#endif // CYGHWR_HAL_SPARC_HAS_ASR17
|
| 384 |
|
|
nop
|
| 385 |
|
|
nop
|
| 386 |
|
|
nop
|
| 387 |
|
|
|
| 388 |
|
|
// INCLUDE PLATFORM BOOT
|
| 389 |
|
|
|
| 390 |
|
|
// This should set up RAM and caches, and calm down any external interrupt
|
| 391 |
|
|
// sources. Also copy two instructions from real_vector_instructions
|
| 392 |
|
|
// into reset_vector, then invalidate the instruction cache.
|
| 393 |
|
|
|
| 394 |
|
|
#include
|
| 395 |
|
|
|
| 396 |
|
|
// halboot.si returns with %sp all set, in sleb versions.
|
| 397 |
|
|
// (though we override if there is an interrupt stack)
|
| 398 |
|
|
|
| 399 |
|
|
led 0x80
|
| 400 |
|
|
|
| 401 |
|
|
! now set up a stack and initial frame linkage
|
| 402 |
|
|
! so as to be able to make C function calls:
|
| 403 |
|
|
! current window is 7, the highest, so we store a
|
| 404 |
|
|
! saved frame thingy that refers to itself in the stack,
|
| 405 |
|
|
! then another which is valid and drop into main from there.
|
| 406 |
|
|
|
| 407 |
|
|
#ifdef BOOTUPSTACK_IS_INTERRUPTSTACK
|
| 408 |
|
|
sethi %hi(cyg_interrupt_stack), %i6
|
| 409 |
|
|
or %i6, %lo(cyg_interrupt_stack), %i6
|
| 410 |
|
|
#endif
|
| 411 |
|
|
andn %i6, 7, %i6 ! round fp down to double alignment
|
| 412 |
|
|
mov 0, %i7 ! null return address
|
| 413 |
|
|
sethi %hi(0xb51ac000), %i0 ! "BStac" pattern
|
| 414 |
|
|
or %i0, 24, %i0
|
| 415 |
|
|
or %i0, 1, %i1
|
| 416 |
|
|
or %i0, 2, %i2
|
| 417 |
|
|
or %i0, 3, %i3
|
| 418 |
|
|
or %i0, 4, %i4
|
| 419 |
|
|
or %i0, 5, %i5
|
| 420 |
|
|
|
| 421 |
|
|
sethi %hi(0xb51ac000), %l0 ! "BStac" pattern
|
| 422 |
|
|
or %l0, 16, %l0
|
| 423 |
|
|
or %l0, 1, %l1
|
| 424 |
|
|
or %l0, 2, %l2
|
| 425 |
|
|
or %l0, 3, %l3
|
| 426 |
|
|
or %l0, 4, %l4
|
| 427 |
|
|
or %l0, 5, %l5
|
| 428 |
|
|
or %l0, 6, %l6
|
| 429 |
|
|
or %l0, 7, %l7
|
| 430 |
|
|
|
| 431 |
|
|
sub %fp, 16 * 4, %sp ! Stack pointer
|
| 432 |
|
|
|
| 433 |
|
|
led 0x90
|
| 434 |
|
|
|
| 435 |
|
|
std %l0, [%sp + 0 * 4] ! save L & I registers
|
| 436 |
|
|
std %l2, [%sp + 2 * 4] ! into new stack frame
|
| 437 |
|
|
std %l4, [%sp + 4 * 4]
|
| 438 |
|
|
std %l6, [%sp + 6 * 4]
|
| 439 |
|
|
|
| 440 |
|
|
led 0x91
|
| 441 |
|
|
|
| 442 |
|
|
std %i0, [%sp + 8 * 4]
|
| 443 |
|
|
std %i2, [%sp + 10 * 4]
|
| 444 |
|
|
std %i4, [%sp + 12 * 4]
|
| 445 |
|
|
std %i6, [%sp + 14 * 4]
|
| 446 |
|
|
|
| 447 |
|
|
led 0x92
|
| 448 |
|
|
|
| 449 |
|
|
sethi %hi(0xb0010000), %o0 ! "Boot" pattern
|
| 450 |
|
|
or %o0, 8, %o0
|
| 451 |
|
|
or %o0, 1, %o1
|
| 452 |
|
|
or %o0, 2, %o2
|
| 453 |
|
|
or %o0, 3, %o3
|
| 454 |
|
|
or %o0, 4, %o4
|
| 455 |
|
|
or %o0, 5, %o5
|
| 456 |
|
|
|
| 457 |
|
|
led 0x98
|
| 458 |
|
|
|
| 459 |
|
|
wr %g0, __WIM_INIT, %wim ! Window 7 (current) is invalid
|
| 460 |
|
|
nop
|
| 461 |
|
|
nop
|
| 462 |
|
|
nop
|
| 463 |
|
|
|
| 464 |
|
|
led 0x99
|
| 465 |
|
|
|
| 466 |
|
|
sethi %hi(0xb0010000), %g1 ! "Boot" pattern
|
| 467 |
|
|
or %g1, 2, %g2
|
| 468 |
|
|
or %g1, 3, %g3
|
| 469 |
|
|
or %g1, 4, %g4
|
| 470 |
|
|
or %g1, 5, %g5
|
| 471 |
|
|
or %g1, 6, %g6
|
| 472 |
|
|
or %g1, 7, %g7
|
| 473 |
|
|
or %g1, 1, %g1
|
| 474 |
|
|
|
| 475 |
|
|
led 0xa0
|
| 476 |
|
|
|
| 477 |
|
|
wr %g0, 0xfe0 + __WIN_INIT, %psr
|
| 478 |
|
|
nop ! Enable traps:
|
| 479 |
|
|
nop ! set psr, _do_ mask interrupts
|
| 480 |
|
|
nop ! mode = prevMode = S, CWP=7
|
| 481 |
|
|
|
| 482 |
|
|
led 0xb0
|
| 483 |
|
|
|
| 484 |
|
|
! now we can start calling out and running C code!
|
| 485 |
|
|
.extern cyg_hal_start
|
| 486 |
|
|
call cyg_hal_start ! puts return address in %o7
|
| 487 |
|
|
or %g1, 1, %g1
|
| 488 |
|
|
|
| 489 |
|
|
loop_forever:
|
| 490 |
|
|
ta 1
|
| 491 |
|
|
b loop_forever ! if it returns
|
| 492 |
|
|
nop
|
| 493 |
|
|
|
| 494 |
|
|
|
| 495 |
|
|
!---------------------------------------------------------------------------
|
| 496 |
|
|
! hal_vsr_table...
|
| 497 |
|
|
|
| 498 |
|
|
.section ".data"
|
| 499 |
|
|
.balign 4
|
| 500 |
|
|
.global hal_vsr_table
|
| 501 |
|
|
hal_vsr_table:
|
| 502 |
|
|
.rept 16
|
| 503 |
|
|
.word hal_default_interrupt_vsr
|
| 504 |
|
|
.endr
|
| 505 |
|
|
.rept 11
|
| 506 |
|
|
.word hal_default_exception_vsr
|
| 507 |
|
|
.endr
|
| 508 |
|
|
|
| 509 |
|
|
!---------------------------------------------------------------------------
|
| 510 |
|
|
! Bootup stack (only needed explicitly in sim)
|
| 511 |
|
|
|
| 512 |
|
|
#ifdef BOOTUPSTACK_IS_INTERRUPTSTACK
|
| 513 |
|
|
.section ".bss"
|
| 514 |
|
|
|
| 515 |
|
|
#ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
|
| 516 |
|
|
#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096
|
| 517 |
|
|
#endif
|
| 518 |
|
|
.balign 16
|
| 519 |
|
|
.global cyg_interrupt_stack_base
|
| 520 |
|
|
cyg_interrupt_stack_base:
|
| 521 |
|
|
.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
|
| 522 |
|
|
.byte 0
|
| 523 |
|
|
.endr
|
| 524 |
|
|
.balign 16
|
| 525 |
|
|
.global cyg_interrupt_stack
|
| 526 |
|
|
cyg_interrupt_stack:
|
| 527 |
|
|
.long 0,0,0,0,0,0,0,0 ! here be secret state stored
|
| 528 |
|
|
#endif
|
| 529 |
|
|
|
| 530 |
|
|
!------------------------------------------------------------------------
|
| 531 |
|
|
! Define a section that reserves space at the start of RAM for the
|
| 532 |
|
|
! vectors to be copied into, for ROM start only.
|
| 533 |
|
|
|
| 534 |
|
|
.section ".ram_vectors","awx",@nobits
|
| 535 |
|
|
#ifdef CYGIMP_HAL_SPARC_COPY_VECTORS_TO_RAM
|
| 536 |
|
|
! need a space at base of RAM for copied vector/trampoline code
|
| 537 |
|
|
.align 0x1000
|
| 538 |
|
|
.space 8 ! for fencepost errors
|
| 539 |
|
|
.space (rom_vectors_end - rom_vectors)
|
| 540 |
|
|
#endif // CYGIMP_HAL_SPARC_COPY_VECTORS_TO_RAM
|
| 541 |
|
|
|
| 542 |
|
|
!------------------------------------------------------------------------
|
| 543 |
|
|
! end of vectors.S
|
