OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sparclite/] [arch/] [v2_0/] [include/] [hal_arch.h] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_HAL_ARCH_H
2
#define CYGONCE_HAL_ARCH_H
3
 
4
//==========================================================================
5
//
6
//      hal_arch.h
7
//
8
//      Architecture specific abstractions
9
//
10
//==========================================================================
11
//####ECOSGPLCOPYRIGHTBEGIN####
12
// -------------------------------------------
13
// This file is part of eCos, the Embedded Configurable Operating System.
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
//==========================================================================
44
//#####DESCRIPTIONBEGIN####
45
//
46
// Author(s):    nickg, gthomas, hmt
47
// Contributors: nickg, gthomas, hmt
48
// Date:         1999-02-20
49
// Purpose:      Define architecture abstractions
50
// Usage:        #include <cyg/hal/hal_arch.h>
51
// 
52
//####DESCRIPTIONEND####
53
//
54
//==========================================================================
55
 
56
#include <pkgconf/hal.h>
57
#include <pkgconf/hal_sparclite.h>
58
 
59
#include <cyg/infra/cyg_type.h>
60
 
61
#include <cyg/hal/hal_intr.h>           // HAL_DISABLE_INTERRUPTS
62
 
63
//--------------------------------------------------------------------------
64
// Processor saved states:
65
//
66
// All these structures must be doubleword (64 bit) aligned.
67
// The code that creates them on the stack will ensure this is so.
68
 
69
#define HAL_THREAD_CONTEXT_GLOBAL_BASE 0
70
#define HAL_THREAD_CONTEXT_OUT_BASE    8
71
#define HAL_THREAD_CONTEXT_LOCAL_BASE 16
72
#define HAL_THREAD_CONTEXT_IN_BASE    24
73
 
74
typedef struct
75
{
76
    // this is the save structure found at *(stack_ptr) always, note that
77
    // i[6] is the frame pointer is the previous stack pointer, and
78
    // o[6] is the stack pointer is the next frame pointer,
79
    // so they form a linked list back up the call stack.
80
    cyg_uint32  l[8];                                   /* Locals r16-r23 */
81
    cyg_uint32  i[8];                                   /* Ins    r24-r31 */
82
} HAL_SavedWindow;
83
 
84
typedef struct
85
{
86
    // Window save at stack pointer
87
    HAL_SavedWindow li;
88
//16
89
    // This is the rest of the save state:
90
    //   NOTE: g[0] is used for the CWP, for %g0 == 0.  Also note that the
91
    //   assembler routines must load/store it in the right order.
92
    cyg_uint32  g[8] ;                                  /* Globals r0- r7 */
93
    cyg_uint32  o[8] ;                                  /* Outs    r8-r15 */
94
//32 words in size
95
 
96
// There is no need to save any other state; for example, condition codes,
97
// the PC and NextPC, and Y, are preserved in local registers in the trap
98
// handling window and so preserved in the caller stack frame as viewed
99
// from an ISR.  Note that the VSR is jumped to with those locals being set
100
// up (and Y in situ), and it must preserve them itself before calling any
101
// subsequent handlers (ISRs).
102
 
103
} HAL_SavedRegisters;
104
 
105
 
106
typedef struct
107
{
108
    // Window save at stack pointer
109
    HAL_SavedWindow li;
110
    cyg_uint32      composite_return_ptr;          /* structure returns */
111
    cyg_uint32      spill_args[6];                 /* for callee to store */
112
    cyg_uint32      spare;                         /* keep this 64-bits   */
113
} HAL_FrameStructure;
114
 
115
 
116
//--------------------------------------------------------------------------
117
// Exception handling function.
118
// This function is defined by the kernel according to this prototype. It is
119
// invoked from the HAL to deal with any CPU exceptions that the HAL does
120
// not want to deal with itself. It usually invokes the kernel's exception
121
// delivery mechanism.
122
 
123
externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
124
 
125
//--------------------------------------------------------------------------
126
// Bit manipulation macros
127
 
128
#define HAL_LSBIT_INDEX(index, mask)            \
129
    CYG_MACRO_START                             \
130
    asm volatile (                              \
131
        "scan   %1, 0, %%l7;"                   \
132
        "mov    31, %0;"                        \
133
        "sub    %0, %%l7, %0"                   \
134
        : "=r"(index)                           \
135
        : "r"(mask & ~(mask-1))                 \
136
        : "l7"                                  \
137
        );                                      \
138
CYG_MACRO_END
139
 
140
#define HAL_MSBIT_INDEX(index, mask)            \
141
    CYG_MACRO_START                             \
142
    asm volatile (                              \
143
        "scan   %1, 0, %%l7;"                   \
144
        "mov    31, %0;"                        \
145
        "sub    %0, %%l7, %0"                   \
146
        : "=r"(index)                           \
147
        : "r"(mask)                             \
148
        : "l7"                                  \
149
        );                                      \
150
CYG_MACRO_END
151
 
152
 
153
//--------------------------------------------------------------------------
154
// Context Initialization
155
// Initialize the context of a thread.
156
// Arguments:
157
// _sparg_ name of variable containing current sp, will be written with new sp
158
// _thread_ thread object address, passed as argument to entry point
159
// _entry_ entry point address.
160
// _id_ bit pattern used in initializing registers, for debugging.
161
 
162
externC CYG_ADDRESS
163
hal_thread_init_context(  CYG_WORD sparg,
164
                          CYG_WORD thread,
165
                          CYG_WORD entry,
166
                          CYG_WORD id );
167
 
168
#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )         \
169
CYG_MACRO_START                                                             \
170
    _sparg_ = hal_thread_init_context( (CYG_WORD)(_sparg_),                 \
171
                                       (CYG_WORD)(_thread_),                \
172
                                       (CYG_WORD)(_entry_),                 \
173
                                       (CYG_WORD)(_id_) );                  \
174
CYG_MACRO_END
175
 
176
//---------------------------------------------------------------------------
177
// Context switch macros.
178
// The arguments are pointers to locations where the stack pointer
179
// of the current thread is to be stored, and from where the sp of the
180
// next thread is to be fetched.
181
 
182
externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
183
externC void hal_thread_load_context( CYG_ADDRESS to )
184
    __attribute__ ((noreturn));
185
 
186
#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_)                    \
187
        hal_thread_switch_context((CYG_ADDRESS)_tspptr_,                \
188
                                  (CYG_ADDRESS)_fspptr_);
189
 
190
#define HAL_THREAD_LOAD_CONTEXT(_tspptr_)                               \
191
        hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
192
 
193
 
194
//---------------------------------------------------------------------------
195
// Execution reorder barrier.
196
// When optimizing the compiler can reorder code. In multithreaded systems
197
// where the order of actions is vital, this can sometimes cause problems.
198
// This macro may be inserted into places where reordering should not happen.
199
 
200
#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
201
 
202
//---------------------------------------------------------------------------
203
// Breakpoint support
204
// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
205
// if executed.
206
// HAL_BREAKINST is the value of the breakpoint instruction and 
207
// HAL_BREAKINST_SIZE is its size in bytes.
208
 
209
#define HAL_BREAKPOINT(_label_)                \
210
asm volatile (" .globl  " #_label_ ";"         \
211
              #_label_":"                      \
212
              "ta 1"                           \
213
    );
214
 
215
#define HAL_BREAKINST           {0x91,0xd0,0x20,0x01}
216
#define HAL_BREAKINST_SIZE      4
217
 
218
//---------------------------------------------------------------------------
219
// Thread register state manipulation for GDB support.
220
 
221
// Translate a stack pointer as saved by the thread context macros above into
222
// a pointer to a HAL_SavedRegisters structure.
223
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ )  \
224
        (_regs_) = (HAL_SavedRegisters *)(_sp_)
225
 
226
// Routines in icontext.c used here because they're quite large for
227
// the SPARClite (note param order):
228
externC void
229
cyg_hal_sparc_get_gdb_regs( void *gdb_regset,
230
                            HAL_SavedRegisters *eCos_regset );
231
 
232
externC void
233
cyg_hal_sparc_set_gdb_regs( HAL_SavedRegisters *eCos_regset,
234
                            void *gdb_regset );
235
 
236
 
237
// Copy a set of registers from a HAL_SavedRegisters structure into a GDB
238
// ordered array.
239
#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ )              \
240
    CYG_MACRO_START                                             \
241
        cyg_hal_sparc_get_gdb_regs( (_aregval_), (_regs_) );    \
242
CYG_MACRO_END
243
 
244
// Copy a GDB ordered array into a HAL_SavedRegisters structure.
245
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ )             \
246
    CYG_MACRO_START                                             \
247
        cyg_hal_sparc_set_gdb_regs( (_regs_), (_aregval_) );    \
248
CYG_MACRO_END
249
 
250
//---------------------------------------------------------------------------
251
// HAL setjmp
252
 
253
#define CYGARC_JMP_BUF_SIZE 32 // (words)
254
 
255
// this too must be doubleword aligned (64 bit)
256
 
257
typedef cyg_uint64 hal_jmp_buf[ CYGARC_JMP_BUF_SIZE / 2 ];
258
 
259
externC int hal_setjmp(hal_jmp_buf env);
260
externC void hal_longjmp(hal_jmp_buf env, int val);
261
 
262
//---------------------------------------------------------------------------
263
// Flush Register Windows
264
//
265
// This is implemented as trap 3 in some SPARC systems.
266
// This macro is only for use from normal, foreground code.
267
// (including exception handlers and the like)
268
 
269
#define HAL_FLUSH_REGISTERS_TO_STACK()                                      \
270
    CYG_MACRO_START                                                         \
271
    cyg_uint32 _saveintr_;                                                  \
272
    HAL_DISABLE_INTERRUPTS( _saveintr_ ); /* leave traps on */              \
273
    asm volatile (                                                          \
274
        /* force out all our callers register sets onto the stack        */ \
275
        /* if necessary: the system will handily take care of this for   */ \
276
        /* us as follows:                                                */ \
277
        "save   %%sp, -16 * 4, %%sp;"   /* need all these to preserve    */ \
278
        "save   %%sp, -16 * 4, %%sp;"   /* the linked list property...   */ \
279
        "save   %%sp, -16 * 4, %%sp;"                                       \
280
        "save   %%sp, -16 * 4, %%sp;"                                       \
281
        "save   %%sp, -16 * 4, %%sp;"                                       \
282
        "save   %%sp, -16 * 4, %%sp;"                                       \
283
        "restore;"                                                          \
284
        "restore;"                                                          \
285
        "restore;"                                                          \
286
        "restore;"                                                          \
287
        "restore;"                                                          \
288
        "restore"                                                           \
289
        /* six of these is correct; a seventh would force out the        */ \
290
        /* current set that we are using right now.  Note that minimal   */ \
291
        /* space is allowed on stack for locals and ins in case this     */ \
292
        /* sequence itself gets interrupted and recurses too deep.       */ \
293
        :                                                                   \
294
        :                                                                   \
295
        : "memory"                                                          \
296
        );                                                                  \
297
    HAL_RESTORE_INTERRUPTS( _saveintr_ );                                   \
298
CYG_MACRO_END
299
 
300
//---------------------------------------------------------------------------
301
// Idle thread code.
302
// This macro is called in the idle thread loop, and gives the HAL the
303
// chance to insert code. Typical idle thread behaviour might be to halt the
304
// processor.
305
 
306
//externC void hal_idle_thread_action(cyg_uint32 loop_count);
307
 
308
#ifndef HAL_IDLE_THREAD_ACTION
309
#define HAL_IDLE_THREAD_ACTION(_count_) \
310
      /* Cyg_Clock::real_time_clock->tick() */
311
#endif
312
 
313
//---------------------------------------------------------------------------
314
 
315
// Minimal and sensible stack sizes: the intention is that applications
316
// will use these to provide a stack size in the first instance prior to
317
// proper analysis.  Idle thread stack should be this big.
318
 
319
//    THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
320
//           THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
321
// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
322
 
323
// We define quite large stack needs for SPARClite, for it requires 576
324
// bytes (144 words) to process an interrupt and thread-switch, and
325
// momentarily, but needed in case of recursive interrupts, it needs 208
326
// words - if a sequence of saves to push out other regsets is interrupted.
327
 
328
// This is not a config option because it should not be adjusted except
329
// under "enough rope" sort of disclaimers.
330
 
331
// A minimal, optimized stack frame is 24 words, but even -O2 code seems to
332
// place a few locals in the locals area: round this up to provide a
333
// sensible overestimate:
334
#define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 32)
335
 
336
// Stack needed for a context switch: this is implicit in the estimate for
337
// interrupts so not explicitly used below:
338
#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 32)
339
 
340
// Interrupt + call to ISR, interrupt_end() and the DSR
341
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
342
    ((208 * 4) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
343
 
344
// And we have lots of registers so no particular amount is added in for
345
// typical local variable usage.
346
 
347
// Typically we have 4 nestable interrupt sources, clock, serialin,
348
// serialout, (and NMI button, but you want it to not destroy context):
349
 
350
#define CYGNUM_HAL_STACK_SIZE_MINIMUM \
351
        (4 * CYGNUM_HAL_STACK_INTERRUPT_SIZE + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
352
 
353
#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
354
        (CYGNUM_HAL_STACK_SIZE_MINIMUM + 8 * CYGNUM_HAL_STACK_FRAME_SIZE)
355
 
356
//--------------------------------------------------------------------------
357
// Macros for switching context between two eCos instances (jump from
358
// code in ROM to code in RAM or vice versa).
359
#define CYGARC_HAL_SAVE_GP()
360
#define CYGARC_HAL_RESTORE_GP()
361
 
362
//-----------------------------------------------------------------------------
363
 
364
#endif // CYGONCE_HAL_ARCH_H
365
// End of hal_arch.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.