OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sparclite/] [sim/] [v2_0/] [include/] [hal_cache.h] - Blame information for rev 249

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_HAL_CACHE_H
2
#define CYGONCE_HAL_CACHE_H
3
 
4
//=============================================================================
5
//
6
//      hal_cache.h
7
//
8
//      HAL Cache control support (such as it is in the simulator)
9
//
10
//=============================================================================
11
//####ECOSGPLCOPYRIGHTBEGIN####
12
// -------------------------------------------
13
// This file is part of eCos, the Embedded Configurable Operating System.
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
//=============================================================================
44
//#####DESCRIPTIONBEGIN####
45
//
46
// Author(s):   nickg, gthomas, hmt
47
// Contributors:        nickg, gthomas, hmt
48
// Date:        1999-01-28
49
// Purpose:     Define Interrupt support
50
// Description: The macros defined here provide the HAL APIs for handling
51
//              the caches.
52
//              
53
// Usage:
54
//              #include <cyg/hal/hal_cache.h>
55
//              ...
56
//              
57
//
58
//####DESCRIPTIONEND####
59
//
60
//=============================================================================
61
 
62
#include <pkgconf/hal.h>
63
#include <pkgconf/hal_sparclite.h>
64
 
65
#include <cyg/infra/cyg_type.h>
66
 
67
//-----------------------------------------------------------------------------
68
// SPARClite cache macros
69
 
70
//-----------------------------------------------------------------------------
71
// Cache dimensions
72
 
73
// Data cache
74
#define HAL_DCACHE_SIZE                 0x800    // Size of data cache in bytes
75
#define HAL_DCACHE_LINE_SIZE            4        // Size of a data cache line
76
#define HAL_DCACHE_WAYS                 4        // Associativity of the cache
77
 
78
// Instruction cache
79
#define HAL_ICACHE_SIZE                 0x800    // Size of cache in bytes
80
#define HAL_ICACHE_LINE_SIZE            4        // Size of a cache line
81
#define HAL_ICACHE_WAYS                 4        // Associativity of the cache
82
 
83
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
84
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
85
 
86
//-----------------------------------------------------------------------------
87
// Global control of data cache
88
 
89
// Enable the data cache
90
#define HAL_DCACHE_ENABLE()
91
// Disable the data cache
92
#define HAL_DCACHE_DISABLE()
93
// Invalidate the entire cache
94
#define HAL_DCACHE_INVALIDATE_ALL()
95
// Synchronize the contents of the cache with memory.
96
#define HAL_DCACHE_SYNC() 
97
 
98
// Set the data cache refill burst size
99
//#define HAL_DCACHE_BURST_SIZE(_size_)
100
 
101
// Set the data cache write mode
102
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
103
 
104
//#define HAL_DCACHE_WRITETHRU_MODE       0
105
//#define HAL_DCACHE_WRITEBACK_MODE       1
106
 
107
// Load the contents of the given address range into the data cache
108
// and then lock the cache so that it stays there.
109
//#define HAL_DCACHE_LOCK(_base_, _size_)
110
 
111
// Undo a previous lock operation
112
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
113
 
114
// Unlock entire cache
115
//#define HAL_DCACHE_UNLOCK_ALL()
116
 
117
//-----------------------------------------------------------------------------
118
// Data cache line control
119
 
120
// Allocate cache lines for the given address range without reading its
121
// contents from memory.
122
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
123
 
124
// Write dirty cache lines to memory and invalidate the cache entries
125
// for the given address range.
126
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
127
 
128
// Invalidate cache lines in the given range without writing to memory.
129
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
130
 
131
// Write dirty cache lines to memory for the given address range.
132
//#define HAL_DCACHE_STORE( _base_ , _size_ )
133
 
134
// Preread the given range into the cache with the intention of reading
135
// from it later.
136
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
137
 
138
// Preread the given range into the cache with the intention of writing
139
// to it later.
140
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
141
 
142
// Allocate and zero the cache lines associated with the given range.
143
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
144
 
145
//-----------------------------------------------------------------------------
146
// Global control of Instruction cache - use Data cache controls since they
147
// are not separatable.
148
 
149
// Enable the instruction cache
150
#define HAL_ICACHE_ENABLE()      HAL_DCACHE_ENABLE()
151
 
152
// Disable the instruction cache
153
#define HAL_ICACHE_DISABLE()     HAL_DCACHE_DISABLE()
154
 
155
// Invalidate the entire cache
156
#define HAL_ICACHE_INVALIDATE_ALL()  HAL_DCACHE_SYNC();  HAL_DCACHE_INVALIDATE_ALL()
157
 
158
// Synchronize the contents of the cache with memory.
159
#define HAL_ICACHE_SYNC()
160
 
161
// Set the instruction cache refill burst size
162
//#define HAL_ICACHE_BURST_SIZE(_size_)
163
 
164
// Load the contents of the given address range into the instruction cache
165
// and then lock the cache so that it stays there.
166
//#define HAL_ICACHE_LOCK(_base_, _size_)
167
 
168
// Undo a previous lock operation
169
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
170
 
171
// Unlock entire cache
172
//#define HAL_ICACHE_UNLOCK_ALL()
173
 
174
//-----------------------------------------------------------------------------
175
// Instruction cache line control
176
 
177
// Invalidate cache lines in the given range without writing to memory.
178
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
179
 
180
//-----------------------------------------------------------------------------
181
#endif // ifndef CYGONCE_HAL_CACHE_H
182
// End of hal_cache.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.