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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sparclite/] [sim/] [v2_0/] [include/] [pkgconf/] [mlt_sparclite_sim_ram.h] - Blame information for rev 174

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// eCos memory layout - Fri Oct 20 08:18:20 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x2000000)
#define CYGMEM_REGION_ram_SIZE (0x80000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x2080000 - (size_t) CYG_LABEL_NAME (__heap1))

Line No.	Rev	Author	Line
1	27	unneback	`// eCos memory layout - Fri Oct 20 08:18:20 2000`
2
3			`// This is a generated file - do not edit`
4
5			`#ifndef __ASSEMBLER__`
6			`#include <cyg/infra/cyg_type.h>`
7			`#include <stddef.h>`
8
9			`#endif`
10			`#define CYGMEM_REGION_ram (0x2000000)`
11			`#define CYGMEM_REGION_ram_SIZE (0x80000)`
12			`#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R \| CYGMEM_REGION_ATTR_W)`
13			`#ifndef __ASSEMBLER__`
14			`extern char CYG_LABEL_NAME (__heap1) [];`
15			`#endif`
16			`#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))`
17			`#define CYGMEM_SECTION_heap1_SIZE (0x2080000 - (size_t) CYG_LABEL_NAME (__heap1))`

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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sparclite/] [sim/] [v2_0/] [include/] [pkgconf/] [mlt_sparclite_sim_ram.h] - Blame information for rev 174