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#ifndef CYGONCE_HAL_CACHE_H
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#define CYGONCE_HAL_CACHE_H
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//=============================================================================
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//
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// hal_cache.h
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//
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// HAL Cache control support (such as it is in the simulator)
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg, gthomas, hmt
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// Contributors: nickg, gthomas, hmt
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// Date: 1999-01-28
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// the caches.
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//
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// Usage:
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// #include <cyg/hal/hal_cache.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <pkgconf/hal_sparclite.h>
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#include <cyg/infra/cyg_type.h>
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//-----------------------------------------------------------------------------
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// SPARClite cache macros
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// The MB6863x Control Registers are in Address Space 1:
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#define HAL_SPARC_ASI_1_READ( addr, res ) \
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asm volatile( \
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"lda [ %1 ] 1, %0" \
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: "=r"(res) \
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: "r"(addr) \
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);
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#define HAL_SPARC_ASI_1_WRITE( addr, val ) \
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asm volatile( \
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"sta %0, [ %1 ] 1" \
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: \
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: "r"(val),"r"(addr) \
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);
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#define HAL_SPARC_MMCR_CBIR 0x00 // Cache/BusInterfaceUnit Control
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#define HAL_SPARC_MMCR_LCR 0x04 // Lock Control Register
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#define HAL_SPARC_MMCR_LCSR 0x08 // Lock Control Save Reg
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#define HAL_SPARC_MMCR_CSR 0x0c // Cache Status Reg
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#define HAL_SPARC_MMCR_RLCR 0x10 // Restore Lock Control Register
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#define HAL_SPARC_MMCR_CBIR_ICE 0x01 // Instruction Cache Enable
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#define HAL_SPARC_MMCR_CBIR_GICL 0x02 // Global IC Lock
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#define HAL_SPARC_MMCR_CBIR_DCE 0x04 // Data CE
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#define HAL_SPARC_MMCR_CBIR_GDCL 0x08 // G Data CE
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#define HAL_SPARC_MMCR_CBIR_PBE 0x10 // Prefetch Buffer Enable
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#define HAL_SPARC_MMCR_CBIR_WBE 0x20 // Write BE
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//-----------------------------------------------------------------------------
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// Cache dimensions
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// These definitions are suitable for any MB8683x processor:
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// The largest possible cachesize and "ways",
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// the smallest possible line size.
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// This gives values that can correctly manipulate the cache by
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// jumping on memory.
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// Data cache
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#define HAL_DCACHE_SIZE 0x2000 // Size of data cache in bytes
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#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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#define HAL_DCACHE_WAYS 2 // Associativity of the cache
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// Instruction cache
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#define HAL_ICACHE_SIZE 0x2000 // Size of cache in bytes
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#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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#define HAL_ICACHE_WAYS 2 // Associativity of the cache
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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//-----------------------------------------------------------------------------
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// Global control of data cache
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// Enable the data cache
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#define HAL_DCACHE_ENABLE() CYG_MACRO_START \
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int _v_; \
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HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \
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_v_ |= HAL_SPARC_MMCR_CBIR_DCE; \
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HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \
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asm volatile ( "nop; nop; nop; nop;" ); \
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CYG_MACRO_END
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// Disable the data cache
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#define HAL_DCACHE_DISABLE() CYG_MACRO_START \
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int _v_; \
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HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \
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_v_ &=~ HAL_SPARC_MMCR_CBIR_DCE; \
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HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \
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asm volatile ( "nop; nop; nop; nop;" ); \
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CYG_MACRO_END
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// Invalidate the entire cache
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#define HAL_DCACHE_INVALIDATE_ALL() CYG_MACRO_START \
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asm volatile ( \
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"set 3, %%l0;" \
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"set 0x00001000, %%l1;" \
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"set 0x80001000, %%l2;" \
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"sta %%l0, [ %%l1 ] 0x0e;" \
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"sta %%l0, [ %%l2 ] 0x0e;" \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop" : : : "l0","l1","l2" ); \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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#define HAL_DCACHE_SYNC() CYG_MACRO_START \
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/* read 8k from the ROM; that should do it... */ \
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volatile cyg_uint32 *_p_ = (cyg_uint32 *)0; \
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volatile cyg_uint32 *_q_ = (cyg_uint32 *)HAL_DCACHE_SIZE; \
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volatile cyg_uint32 _tmp_; \
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for ( ; _p_ < _q_; _p_ ++ ) _tmp_ = *_q_; \
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CYG_MACRO_END
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// Query the state of the data cache
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#define HAL_DCACHE_IS_ENABLED(_state_) CYG_MACRO_START \
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int _v_; \
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HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \
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(_state_) = (0 != (_v_ & HAL_SPARC_MMCR_CBIR_DCE)); \
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CYG_MACRO_END
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// Set the data cache refill burst size
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//#define HAL_DCACHE_BURST_SIZE(_size_)
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// Set the data cache write mode
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//#define HAL_DCACHE_WRITE_MODE( _mode_ )
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//#define HAL_DCACHE_WRITETHRU_MODE 0
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//#define HAL_DCACHE_WRITEBACK_MODE 1
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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//#define HAL_DCACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_DCACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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//#define HAL_DCACHE_UNLOCK_ALL()
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//-----------------------------------------------------------------------------
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// Data cache line control
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// Allocate cache lines for the given address range without reading its
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// contents from memory.
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//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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// Write dirty cache lines to memory and invalidate the cache entries
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// for the given address range.
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//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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// Invalidate cache lines in the given range without writing to memory.
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//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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// Write dirty cache lines to memory for the given address range.
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//#define HAL_DCACHE_STORE( _base_ , _size_ )
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// Preread the given range into the cache with the intention of reading
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// from it later.
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//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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// Preread the given range into the cache with the intention of writing
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// to it later.
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//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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// Allocate and zero the cache lines associated with the given range.
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//#define HAL_DCACHE_ZERO( _base_ , _size_ )
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache - use Data cache controls since they
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// are not separatable.
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// Enable the data cache
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#define HAL_ICACHE_ENABLE() CYG_MACRO_START \
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int _v_; \
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HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \
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_v_ |= HAL_SPARC_MMCR_CBIR_ICE; \
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HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \
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asm volatile ( "nop; nop; nop; nop;" ); \
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CYG_MACRO_END
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// Disable the data cache
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#define HAL_ICACHE_DISABLE() CYG_MACRO_START \
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int _v_; \
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HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \
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_v_ &=~ HAL_SPARC_MMCR_CBIR_ICE; \
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HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \
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asm volatile ( "nop; nop; nop; nop;" ); \
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CYG_MACRO_END
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// Invalidate the entire cache
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#define HAL_ICACHE_INVALIDATE_ALL() CYG_MACRO_START \
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asm volatile ( \
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"set 3, %%l0;" \
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"set 0x00001000, %%l1;" \
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"set 0x80001000, %%l2;" \
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"sta %%l0, [ %%l1 ] 0x0c;" \
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"sta %%l0, [ %%l2 ] 0x0c;" \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop" : : : "l0","l1","l2" ); \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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#define HAL_ICACHE_SYNC() CYG_MACRO_START \
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HAL_DCACHE_SYNC(); /* Ensure data is in memory */ \
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HAL_ICACHE_INVALIDATE_ALL(); /* Pick up new memory contents */ \
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CYG_MACRO_END
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// Query the state of the instruction cache
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#define HAL_ICACHE_IS_ENABLED(_state_) CYG_MACRO_START \
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int _v_; \
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HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \
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(_state_) = (0 != (_v_ & HAL_SPARC_MMCR_CBIR_ICE)); \
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CYG_MACRO_END
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// Set the instruction cache refill burst size
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//#define HAL_ICACHE_BURST_SIZE(_size_)
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// Load the contents of the given address range into the instruction cache
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// and then lock the cache so that it stays there.
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//#define HAL_ICACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_ICACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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//#define HAL_ICACHE_UNLOCK_ALL()
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//-----------------------------------------------------------------------------
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// Instruction cache line control
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// Invalidate cache lines in the given range without writing to memory.
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//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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//-----------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_CACHE_H
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// End of hal_cache.h
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