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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sparclite/] [sleb/] [v2_0/] [include/] [hal_cpu.h] - Blame information for rev 390

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#ifndef CYGONCE_HAL_SPARCLITE_HAL_CPU_H
2
#define CYGONCE_HAL_SPARCLITE_HAL_CPU_H
3
// ====================================================================
4
//
5
//      hal_cpu.h
6
//
7
//      HAL CPU architecture file for MB8683x
8
//
9
// ====================================================================
10
//####ECOSGPLCOPYRIGHTBEGIN####
11
// -------------------------------------------
12
// This file is part of eCos, the Embedded Configurable Operating System.
13
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14
//
15
// eCos is free software; you can redistribute it and/or modify it under
16
// the terms of the GNU General Public License as published by the Free
17
// Software Foundation; either version 2 or (at your option) any later version.
18
//
19
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
21
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
22
// for more details.
23
//
24
// You should have received a copy of the GNU General Public License along
25
// with eCos; if not, write to the Free Software Foundation, Inc.,
26
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27
//
28
// As a special exception, if other files instantiate templates or use macros
29
// or inline functions from this file, or you compile this file and link it
30
// with other works to produce a work based on this file, this file does not
31
// by itself cause the resulting work to be covered by the GNU General Public
32
// License. However the source code for this file must still be made available
33
// in accordance with section (3) of the GNU General Public License.
34
//
35
// This exception does not invalidate any other reasons why a work based on
36
// this file might be covered by the GNU General Public License.
37
//
38
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39
// at http://sources.redhat.com/ecos/ecos-license/
40
// -------------------------------------------
41
//####ECOSGPLCOPYRIGHTEND####
42
// ====================================================================
43
//#####DESCRIPTIONBEGIN####
44
//
45
// Author(s):           Red Hat
46
// Contributors:        Red Hat, hmt
47
// Date:                1999-03-01
48
// Purpose:             MB8683x SPARClite CPU symbols
49
// Description:
50
//
51
//####DESCRIPTIONEND####
52
//
53
// ====================================================================
54
 
55
 
56
// NOTE: THIS FILE HAS NOT BEEN "CLEANED UP" WRT NAMESPACE USE
57
//
58
//        it is only used internally to the SLEB HAL
59
//
60
// it should not be exported by inclusion in API header files
61
//
62
 
63
#ifndef __ASSEMBLER__
64
/*
65
 *  Register numbers. These are assumed to match the
66
 *  register numbers used by GDB.
67
 */
68
enum __regnames {
69
    REG_G0,     REG_G1,     REG_G2,     REG_G3,
70
    REG_G4,     REG_G5,     REG_G6,     REG_G7,
71
    REG_O0,     REG_O1,     REG_O2,     REG_O3,
72
    REG_O4,     REG_O5,     REG_SP,     REG_O7,
73
    REG_L0,     REG_L1,     REG_L2,     REG_L3,
74
    REG_L4,     REG_L5,     REG_L6,     REG_L7,
75
    REG_I0,     REG_I1,     REG_I2,     REG_I3,
76
    REG_I4,     REG_I5,     REG_FP,     REG_I7,
77
 
78
    REG_F0,     REG_F1,     REG_F2,     REG_F3,
79
    REG_F4,     REG_F5,     REG_F6,     REG_F7,
80
    REG_F8,     REG_F9,     REG_F10,    REG_F11,
81
    REG_F12,    REG_F13,    REG_F14,    REG_F15,
82
    REG_F16,    REG_F17,    REG_F18,    REG_F19,
83
    REG_F20,    REG_F21,    REG_F22,    REG_F23,
84
    REG_F24,    REG_F25,    REG_F26,    REG_F27,
85
    REG_F28,    REG_F29,    REG_F30,    REG_F31,
86
 
87
    REG_Y,      REG_PSR,    REG_WIM,    REG_TBR,
88
    REG_PC,     REG_NPC,    REG_FPSR,   REG_CPSR,
89
    REG_DIA1,   REG_DIA2,   REG_DDA1,   REG_DDA2,
90
    REG_DDV1,   REG_DDV2,   REG_DCR,    REG_DSR,
91
 
92
    REG_LAST
93
};
94
#endif
95
 
96
#ifdef __ASSEMBLER__
97
/*
98
 * Macros to glue together two tokens.
99
 */
100
#ifdef __STDC__
101
#define XGLUE(a,b) a##b
102
#else
103
#define XGLUE(a,b) a/**/b
104
#endif
105
 
106
#define GLUE(a,b) XGLUE(a,b)
107
 
108
#ifdef NEED_UNDERSCORE
109
#define SYM_NAME(name) GLUE(_,name)
110
 
111
        .macro FUNC_START name
112
        .align 4
113
        .globl _\name
114
        .type  _\name,#function
115
        .proc   04
116
    _\name:
117
        .endm
118
 
119
        .macro FUNC_END name
120
    .LL_\name:
121
        .size _\name,.LL_\name - _\name
122
        .endm
123
 
124
#else
125
#define SYM_NAME(name) name
126
 
127
        .macro FUNC_START name
128
        .align 4
129
        .globl \name
130
        .type  \name,#function
131
        .proc   04
132
    \name:
133
        .endm
134
 
135
        .macro FUNC_END name
136
    .LL\name:
137
        .size \name,.LL\name - \name
138
        .endm
139
 
140
#endif
141
 
142
#endif /* __ASSEMBLER__ */
143
 
144
/*
145
 *  breakpoint opcode.
146
 */
147
#define BREAKPOINT_OPCODE       0x91d02001
148
 
149
/*
150
 *  inline asm statement to cause breakpoint.
151
 */
152
#define BREAKPOINT()    asm volatile ("ta 1\n")
153
 
154
/*
155
 * Core Exception vectors.
156
 */
157
#define BSP_EXC_IACCESS     0
158
#define BSP_EXC_ILL         1
159
#define BSP_EXC_IPRIV       2
160
#define BSP_EXC_FPDIS       3
161
#define BSP_EXC_WINOVF      4
162
#define BSP_EXC_WINUND      5
163
#define BSP_EXC_ALIGN       6
164
#define BSP_EXC_DACCESS     7
165
#define BSP_EXC_TAGOVF      8
166
#define BSP_EXC_INT1        9
167
#define BSP_EXC_INT2       10
168
#define BSP_EXC_INT3       11
169
#define BSP_EXC_INT4       12
170
#define BSP_EXC_INT5       13
171
#define BSP_EXC_INT6       14
172
#define BSP_EXC_INT7       15
173
#define BSP_EXC_INT8       16
174
#define BSP_EXC_INT9       17
175
#define BSP_EXC_INT10      18
176
#define BSP_EXC_INT11      19
177
#define BSP_EXC_INT12      20
178
#define BSP_EXC_INT13      21
179
#define BSP_EXC_INT14      22
180
#define BSP_EXC_INT15      23
181
#define BSP_EXC_CPDIS      24
182
#define BSP_EXC_BREAK      25
183
#define BSP_EXC_WINFLUSH   26
184
#define BSP_EXC_SYSCALL    27
185
#define BSP_EXC_DEBUG      28
186
#define BSP_EXC_TRAP       29
187
 
188
#define BSP_MAX_EXCEPTIONS 30
189
 
190
#define BSP_VEC_MT_DEBUG   30
191
#define BSP_VEC_STUB_ENTRY 31
192
#define BSP_VEC_BSPDATA    32
193
 
194
#define NUM_VTAB_ENTRIES   33
195
 
196
#define CPU_WINSIZE 8
197
 
198
/*
199
 * Exception frame offsets.
200
 */
201
#define GPR_SIZE 4
202
#define FPR_SIZE 4
203
#define PTR_BYTES 4
204
 
205
/* Leave room for locals + hidden arg + arg spill + dword align */
206
#define FR_BIAS   ((16+1+6+1)*GPR_SIZE)
207
 
208
#define FR_G0     FR_BIAS
209
#define FR_G1     (FR_G0 + GPR_SIZE)
210
#define FR_G2     (FR_G1 + GPR_SIZE)
211
#define FR_G3     (FR_G2 + GPR_SIZE)
212
#define FR_G4     (FR_G3 + GPR_SIZE)
213
#define FR_G5     (FR_G4 + GPR_SIZE)
214
#define FR_G6     (FR_G5 + GPR_SIZE)
215
#define FR_G7     (FR_G6 + GPR_SIZE)
216
#define FR_O0     (FR_G7 + GPR_SIZE)
217
#define FR_O1     (FR_O0 + GPR_SIZE)
218
#define FR_O2     (FR_O1 + GPR_SIZE)
219
#define FR_O3     (FR_O2 + GPR_SIZE)
220
#define FR_O4     (FR_O3 + GPR_SIZE)
221
#define FR_O5     (FR_O4 + GPR_SIZE)
222
#define FR_O6     (FR_O5 + GPR_SIZE)
223
#define FR_SP     FR_O6
224
#define FR_O7     (FR_SP + GPR_SIZE)
225
#define FR_L0     (FR_O7 + GPR_SIZE)
226
#define FR_L1     (FR_L0 + GPR_SIZE)
227
#define FR_L2     (FR_L1 + GPR_SIZE)
228
#define FR_L3     (FR_L2 + GPR_SIZE)
229
#define FR_L4     (FR_L3 + GPR_SIZE)
230
#define FR_L5     (FR_L4 + GPR_SIZE)
231
#define FR_L6     (FR_L5 + GPR_SIZE)
232
#define FR_L7     (FR_L6 + GPR_SIZE)
233
#define FR_I0     (FR_L7 + GPR_SIZE)
234
#define FR_I1     (FR_I0 + GPR_SIZE)
235
#define FR_I2     (FR_I1 + GPR_SIZE)
236
#define FR_I3     (FR_I2 + GPR_SIZE)
237
#define FR_I4     (FR_I3 + GPR_SIZE)
238
#define FR_I5     (FR_I4 + GPR_SIZE)
239
#define FR_I6     (FR_I5 + GPR_SIZE)
240
#define FR_FP     FR_I6
241
#define FR_I7     (FR_FP + GPR_SIZE)
242
 
243
#define FR_FREG0  (FR_I7 + GPR_SIZE)
244
#define FR_FREG1  (FR_FREG0 + FPR_SIZE)
245
#define FR_FREG2  (FR_FREG1 + FPR_SIZE)
246
#define FR_FREG3  (FR_FREG2 + FPR_SIZE)
247
#define FR_FREG4  (FR_FREG3 + FPR_SIZE)
248
#define FR_FREG5  (FR_FREG4 + FPR_SIZE)
249
#define FR_FREG6  (FR_FREG5 + FPR_SIZE)
250
#define FR_FREG7  (FR_FREG6 + FPR_SIZE)
251
#define FR_FREG8  (FR_FREG7 + FPR_SIZE)
252
#define FR_FREG9  (FR_FREG8 + FPR_SIZE)
253
#define FR_FREG10 (FR_FREG9 + FPR_SIZE)
254
#define FR_FREG11 (FR_FREG10 + FPR_SIZE)
255
#define FR_FREG12 (FR_FREG11 + FPR_SIZE)
256
#define FR_FREG13 (FR_FREG12 + FPR_SIZE)
257
#define FR_FREG14 (FR_FREG13 + FPR_SIZE)
258
#define FR_FREG15 (FR_FREG14 + FPR_SIZE)
259
#define FR_FREG16 (FR_FREG15 + FPR_SIZE)
260
#define FR_FREG17 (FR_FREG16 + FPR_SIZE)
261
#define FR_FREG18 (FR_FREG17 + FPR_SIZE)
262
#define FR_FREG19 (FR_FREG18 + FPR_SIZE)
263
#define FR_FREG20 (FR_FREG19 + FPR_SIZE)
264
#define FR_FREG21 (FR_FREG20 + FPR_SIZE)
265
#define FR_FREG22 (FR_FREG21 + FPR_SIZE)
266
#define FR_FREG23 (FR_FREG22 + FPR_SIZE)
267
#define FR_FREG24 (FR_FREG23 + FPR_SIZE)
268
#define FR_FREG25 (FR_FREG24 + FPR_SIZE)
269
#define FR_FREG26 (FR_FREG25 + FPR_SIZE)
270
#define FR_FREG27 (FR_FREG26 + FPR_SIZE)
271
#define FR_FREG28 (FR_FREG27 + FPR_SIZE)
272
#define FR_FREG29 (FR_FREG28 + FPR_SIZE)
273
#define FR_FREG30 (FR_FREG29 + FPR_SIZE)
274
#define FR_FREG31 (FR_FREG30 + FPR_SIZE)
275
 
276
#define FR_Y      (FR_FREG31 + FPR_SIZE)
277
#define FR_PSR    (FR_Y      + GPR_SIZE)
278
#define FR_WIM    (FR_PSR    + GPR_SIZE)
279
#define FR_TBR    (FR_WIM    + GPR_SIZE)
280
#define FR_PC     (FR_TBR    + GPR_SIZE)
281
#define FR_NPC    (FR_PC     + GPR_SIZE)
282
#define FR_FPSR   (FR_NPC    + GPR_SIZE)
283
#define FR_CPSR   (FR_FPSR   + GPR_SIZE)
284
#define FR_DIA1   (FR_CPSR   + GPR_SIZE)
285
#define FR_DIA2   (FR_DIA1   + GPR_SIZE)
286
#define FR_DDA1   (FR_DIA2   + GPR_SIZE)
287
#define FR_DDA2   (FR_DDA1   + GPR_SIZE)
288
#define FR_DDV1   (FR_DDA2   + GPR_SIZE)
289
#define FR_DDV2   (FR_DDV1   + GPR_SIZE)
290
#define FR_DCR    (FR_DDV2   + GPR_SIZE)
291
#define FR_DSR    (FR_DCR    + GPR_SIZE)
292
#define FR_ASR17  (FR_DSR    + GPR_SIZE)
293
 
294
#define EX_STACK_SIZE (FR_ASR17 + GPR_SIZE)
295
 
296
#ifndef __ASSEMBLER__
297
/*
298
 *  How registers are stored for exceptions.
299
 */
300
typedef struct
301
{
302
    unsigned long _g0;
303
    unsigned long _g1;
304
    unsigned long _g2;
305
    unsigned long _g3;
306
    unsigned long _g4;
307
    unsigned long _g5;
308
    unsigned long _g6;
309
    unsigned long _g7;
310
    unsigned long _o0;
311
    unsigned long _o1;
312
    unsigned long _o2;
313
    unsigned long _o3;
314
    unsigned long _o4;
315
    unsigned long _o5;
316
    unsigned long _sp;
317
    unsigned long _o7;
318
    unsigned long _l0;
319
    unsigned long _l1;
320
    unsigned long _l2;
321
    unsigned long _l3;
322
    unsigned long _l4;
323
    unsigned long _l5;
324
    unsigned long _l6;
325
    unsigned long _l7;
326
    unsigned long _i0;
327
    unsigned long _i1;
328
    unsigned long _i2;
329
    unsigned long _i3;
330
    unsigned long _i4;
331
    unsigned long _i5;
332
    unsigned long _fp;
333
    unsigned long _i7;
334
 
335
    unsigned long _fpr[32];
336
 
337
    unsigned long _y;
338
    unsigned long _psr;
339
    unsigned long _wim;
340
    unsigned long _tbr;
341
 
342
    unsigned long _pc;
343
    unsigned long _npc;
344
    unsigned long _fpsr;
345
    unsigned long _cpsr;
346
    unsigned long _dia1;
347
    unsigned long _dia2;
348
    unsigned long _dda1;
349
    unsigned long _dda2;
350
    unsigned long _ddv1;
351
    unsigned long _ddv2;
352
    unsigned long _dcr;
353
    unsigned long _dsr;
354
 
355
    unsigned long _asr17;
356
 
357
} ex_regs_t;
358
 
359
/*
360
 *  How gdb expects registers to be stored.
361
 */
362
typedef struct
363
{
364
    unsigned long _g0;
365
    unsigned long _g1;
366
    unsigned long _g2;
367
    unsigned long _g3;
368
    unsigned long _g4;
369
    unsigned long _g5;
370
    unsigned long _g6;
371
    unsigned long _g7;
372
    unsigned long _o0;
373
    unsigned long _o1;
374
    unsigned long _o2;
375
    unsigned long _o3;
376
    unsigned long _o4;
377
    unsigned long _o5;
378
    unsigned long _sp;
379
    unsigned long _o7;
380
    unsigned long _l0;
381
    unsigned long _l1;
382
    unsigned long _l2;
383
    unsigned long _l3;
384
    unsigned long _l4;
385
    unsigned long _l5;
386
    unsigned long _l6;
387
    unsigned long _l7;
388
    unsigned long _i0;
389
    unsigned long _i1;
390
    unsigned long _i2;
391
    unsigned long _i3;
392
    unsigned long _i4;
393
    unsigned long _i5;
394
    unsigned long _fp;
395
    unsigned long _i7;
396
    unsigned long _fpr[32];
397
    unsigned long _y;
398
    unsigned long _psr;
399
    unsigned long _wim;
400
    unsigned long _tbr;
401
    unsigned long _pc;
402
    unsigned long _npc;
403
    unsigned long _fpsr;
404
    unsigned long _cpsr;
405
    unsigned long _dia1;
406
    unsigned long _dia2;
407
    unsigned long _dda1;
408
    unsigned long _dda2;
409
    unsigned long _ddv1;
410
    unsigned long _ddv2;
411
    unsigned long _dcr;
412
    unsigned long _dsr;
413
} gdb_regs_t;
414
 
415
 
416
extern void __dcache_flush(void *addr, int nbytes);
417
extern void __icache_flush(void *addr, int nbytes);
418
extern int  __dcache_disable(void);
419
extern void __dcache_enable(void);
420
extern void __icache_disable(void);
421
extern void __icache_enable(void);
422
 
423
 
424
#endif /* !__ASSEMBLER__ */
425
 
426
 
427
#define PSR_INIT 0xfa7
428
 
429
 
430
/*
431
 * Memory-mapped (ASI=1) registers for MB8683x series.
432
 */
433
#define CBIR    0x00000000
434
#define LCR     0x00000004
435
#define LCSR    0x00000008
436
#define CSR     0x0000000C
437
#define RLCR    0x00000010
438
#define BCR     0x00000020
439
#define SSCR    0x00000080
440
 
441
#define SPGMR   0x00000120
442
#define ARSR1   0x00000124
443
#define ARSR2   0x00000128
444
#define ARSR3   0x0000012C
445
#define ARSR4   0x00000130
446
#define ARSR5   0x00000134
447
#define AMR0    0x00000140
448
#define AMR1    0x00000144
449
#define AMR2    0x00000148
450
#define AMR3    0x0000014C
451
#define AMR4    0x00000150
452
#define AMR5    0x00000154
453
#define WSSR0   0x00000160
454
#define WSSR1   0x00000164
455
#define WSSR2   0x00000168
456
#define BWCR    0x0000016C
457
#define REFTMR  0x00000174
458
#define DRLD    0x00000178
459
#define VER2    0x00020000
460
#define SLPMD   0x00020004
461
 
462
/* CBIR bit fields */
463
#define CBIR_ICEN    0x01  /* Icache enable */
464
#define CBIR_ICLOCK  0x02  /* Icache lock   */
465
#define CBIR_DCEN    0x04  /* Dcache enable */
466
#define CBIR_DCLOCK  0x08  /* Dcache lock   */
467
#define CBIR_PBEN    0x10  /* Prefetch Buffer enable */
468
#define CBIR_WBEN    0x20  /* Write Buffer enable */
469
 
470
/* LCR bit fields */
471
#define LCR_ILOCK    0x01  /* Icache Auto-lock enable */
472
#define LCR_DLOCK    0x02  /* Dcache Auto-lock enable */
473
 
474
/* WSSRn bit fields */
475
#define WSSR_OVERRIDE 1
476
#define WSSR_SINGLE   2
477
#define WSSR_WAITEN   4
478
 
479
#define WSSR_CNT1_SHIFT 8
480
#define WSSR_CNT2_SHIFT 3
481
#define WSSR_CS0_SHIFT  6
482
#define WSSR_CS1_SHIFT  19
483
 
484
#define WSSR_SUBVAL(c1,c2,flags) (((c1)<<8)|((c2)<<3)|(flags))
485
#define WSSR_VAL(c1b,c2b,flagsb,c1a,c2a,flagsa) \
486
           ((WSSR_SUBVAL(c1b,c2b,flagsb)<<19)|(WSSR_SUBVAL(c1a,c2a,flagsa)<<6))
487
 
488
#define SPGMR_VAL(asi,addr) (((asi)<<23)|(((addr)>>9)&0x007ffffe))
489
#define ARSR_VAL(asi,base)  ((((asi)&0xff)<<23)|(((base)>>9)&0x007ffffe))
490
#define AMR_VAL(asi,base)   (((~(asi))<<23)|(((~(base))>>9)&0x007fffff))
491
 
492
/* SSCR bit fields */
493
#define SSCR_TIMER  0x04
494
#define SSCR_WAIT   0x08
495
#define SSCR_CS     0x10
496
#define SSCR_SAMEPG 0x20
497
#define SSCR_DRAM   0x40
498
#define SSCR_BURST  0x80
499
 
500
/* BCR bit fields */
501
#define BCR_IBE   1
502
#define BCR_DBE   2
503
 
504
 
505
/* DRAM Controller registers as offsets into CS3 space */
506
#define DBANKR  0x20
507
#define DTIMR   0x24
508
 
509
/* DBANKR bit fields */
510
#define DBANKR_512K     0
511
#define DBANKR_1M       1
512
#define DBANKR_2M       2
513
#define DBANKR_4M       3
514
#define DBANKR_8M       4
515
#define DBANKR_16M      5
516
#define DBANKR_32M      6
517
#define DBANKR_64M      7
518
#define DBANKR_CA9      (2<<4)
519
#define DBANKR_CA10     (3<<4)
520
#define DBANKR_CA11     (4<<4)
521
#define DBANKR_CA12     (5<<4)
522
#define DBANKR_4C1W     (0<<7)  /* 4CAS/1WE */
523
#define DBANKR_1C4W     (1<<7)  /* 1CAS/4WE */
524
#define DBANKR_EDO      (1<<8)
525
#define DBANKR_SA01     (1<<9)
526
#define DBANKR_SA02     (2<<9)
527
#define DBANKR_SA04     (3<<9)
528
 
529
/* DTIMR bit fields */
530
#define DTIMR_RP1     0
531
#define DTIMR_RP2     1
532
#define DTIMR_CAS1    (0<<1)
533
#define DTIMR_CAS2    (1<<1)
534
#define DTIMR_CBR1    (0<<2)
535
#define DTIMR_CBR2    (1<<2)
536
#define DTIMR_CBR3    (2<<2)
537
#define DTIMR_RPS2    (0<<4)
538
#define DTIMR_RPS4    (1<<4)
539
 
540
 
541
/* -------------------------------------------------------------------*/
542
#endif  /* CYGONCE_HAL_SPARCLITE_HAL_CPU_H */
543
/* EOF hal_cpu.h */

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