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#ifndef CYGONCE_HAL_HAL_HWIO_H
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#define CYGONCE_HAL_HAL_HWIO_H
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/*=============================================================================
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//
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// hal_hwio.h
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//
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// HAL Support for IO to platform-specific devices
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt
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// Contributors: hmt
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// Date: 1999-01-11
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// Purpose: HAL Support for IO to platform-specific devices
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// Description: Macros to access the 86940 SPARClite companion chip
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// Usage: #include <cyg/hal/hal_hwio.h>
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <pkgconf/system.h>
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#include <pkgconf/hal.h>
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#include <pkgconf/hal_sparclite.h>
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#include <pkgconf/hal_sparclite_sleb.h>
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#include <cyg/infra/cyg_type.h>
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/*---------------------------------------------------------------------------*/
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/* MB86940 flags and the like */
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/* Interrupt trigger modes. */
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#define HAL_SPARC_86940_TRIG_LEVEL_H 0 /* trigger on high level */
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#define HAL_SPARC_86940_TRIG_LEVEL_L 1 /* trigger on low level */
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#define HAL_SPARC_86940_TRIG_EDGE_H 2 /* trigger on rising edge */
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#define HAL_SPARC_86940_TRIG_EDGE_L 3 /* trigger on falling edge */
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/* Timer prescaler register values */
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#define HAL_SPARC_86940_PRS_EXTCLK 0x8000
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#define HAL_SPARC_86940_PRS_ODIV1 (0<<8)
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#define HAL_SPARC_86940_PRS_ODIV2 (1<<8)
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#define HAL_SPARC_86940_PRS_ODIV4 (2<<8)
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#define HAL_SPARC_86940_PRS_ODIV8 (3<<8)
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#define HAL_SPARC_86940_PRS_ODIV16 (4<<8)
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#define HAL_SPARC_86940_PRS_ODIV32 (5<<8)
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#define HAL_SPARC_86940_PRS_ODIV64 (6<<8)
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#define HAL_SPARC_86940_PRS_ODIV128 (7<<8)
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/* Timer control register values */
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#define HAL_SPARC_86940_TCR_CE (1<<11)
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#define HAL_SPARC_86940_TCR_CLKINT (0<<9)
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#define HAL_SPARC_86940_TCR_CLKEXT (1<<9)
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#define HAL_SPARC_86940_TCR_CLKPRS (2<<9)
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#define HAL_SPARC_86940_TCR_CLKRSVD (3<<9)
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#define HAL_SPARC_86940_TCR_OUTSAME (0<<7)
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#define HAL_SPARC_86940_TCR_OUTHIGH (1<<7)
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#define HAL_SPARC_86940_TCR_OUTLOW (2<<7)
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#define HAL_SPARC_86940_TCR_OUTC3 (3<<7)
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#define HAL_SPARC_86940_TCR_INV (1<<6)
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#define HAL_SPARC_86940_TCR_PER_INT (0<<3)
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#define HAL_SPARC_86940_TCR_TO_INT (1<<3)
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#define HAL_SPARC_86940_TCR_SQWAVE (2<<3)
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#define HAL_SPARC_86940_TCR_SW_WATCH (3<<3)
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#define HAL_SPARC_86940_TCR_HW_WATCH (4<<3)
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#define HAL_SPARC_86940_TCR_LEVEL_L 0
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#define HAL_SPARC_86940_TCR_LEVEL_H 1
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#define HAL_SPARC_86940_TCR_EDGE_H 2
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#define HAL_SPARC_86940_TCR_EDGE_L 3
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#define HAL_SPARC_86940_TCR_EDGE 4
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/* serial mode register values */
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#define HAL_SPARC_86940_SER_STOP0 (0<<6)
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#define HAL_SPARC_86940_SER_STOP1 (1<<6)
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#define HAL_SPARC_86940_SER_STOP1_5 (2<<6)
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#define HAL_SPARC_86940_SER_STOP2 (3<<6)
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#define HAL_SPARC_86940_SER_NO_PARITY (0<<4)
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#define HAL_SPARC_86940_SER_ODD_PARITY (1<<4)
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#define HAL_SPARC_86940_SER_EVEN_PARITY (3<<4)
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#define HAL_SPARC_86940_SER_5BITS (0<<2)
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#define HAL_SPARC_86940_SER_6BITS (1<<2)
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#define HAL_SPARC_86940_SER_7BITS (2<<2)
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#define HAL_SPARC_86940_SER_8BITS (3<<2)
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#define HAL_SPARC_86940_SER_MODE_SYNCH 0
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#define HAL_SPARC_86940_SER_DIV1_CLK 1
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#define HAL_SPARC_86940_SER_DIV16_CLK 2
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#define HAL_SPARC_86940_SER_DIV64_CLK 3
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/* serial command register (asynch) */
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#define HAL_SPARC_86940_SER_CMD_EHM (1<<7)
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#define HAL_SPARC_86940_SER_CMD_IRST (1<<6)
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#define HAL_SPARC_86940_SER_CMD_RTS (1<<5)
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#define HAL_SPARC_86940_SER_CMD_EFR (1<<4)
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#define HAL_SPARC_86940_SER_CMD_BREAK (1<<3)
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#define HAL_SPARC_86940_SER_CMD_RXEN (1<<2)
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#define HAL_SPARC_86940_SER_CMD_DTR (1<<1)
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#define HAL_SPARC_86940_SER_CMD_TXEN (1<<0)
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/* serial status register */
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#define HAL_SPARC_86940_SER_STAT_DSR (1<<7)
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#define HAL_SPARC_86940_SER_STAT_BREAK (1<<6)
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#define HAL_SPARC_86940_SER_STAT_FERR (1<<5)
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#define HAL_SPARC_86940_SER_STAT_OERR (1<<4)
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#define HAL_SPARC_86940_SER_STAT_PERR (1<<3)
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#define HAL_SPARC_86940_SER_STAT_TXEMP (1<<2)
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#define HAL_SPARC_86940_SER_STAT_RXRDY (1<<1)
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#define HAL_SPARC_86940_SER_STAT_TXRDY (1<<0)
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#define HAL_SPARC_86940_CHIP_ASI 4
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#define HAL_SPARC_86940_CHIP_BASE 0x10000000
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#define HAL_SPARC_86940_REGADDR_SHIFT 2
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#define HAL_SPARC_86940_REGVAL_SHIFT 16
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/*---------------------------------------------------------------------------*/
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/* Register addresses */
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// The "interesting" IO parts are in Address Space Four:
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#define HAL_SPARC_ASI_4_READ( addr, res ) \
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asm volatile( \
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"lda [ %1 ] 4, %0" \
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: "=r"(res) \
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: "r"(addr) \
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);
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#define HAL_SPARC_ASI_4_WRITE( addr, val ) \
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asm volatile( \
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"sta %0, [ %1 ] 4" \
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: \
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: "r"(val),"r"(addr) \
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);
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#define HAL_SPARC_86940_BASE (0x10000000) // in ASI 4
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// The 86940 is connected to the upper 16 bits!
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#define HAL_SPARC_86940_READ( reg, result ) CYG_MACRO_START \
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cyg_uint32 hires; \
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HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires ); \
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hires >>= 16; \
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result = hires; \
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CYG_MACRO_END
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// THIS IS ONLY HERE FOR DEBUGGING:
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// The 86940 is connected to the upper 16 bits!
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// And seems to be an unreliable deprecated thing...
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// so read it 3 times and believe the majority.
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#define HAL_SPARC_86940_READ3( reg, result ) CYG_MACRO_START \
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cyg_uint32 hires1; \
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cyg_uint32 hires2; \
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cyg_uint32 hires3; \
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HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires1 ); \
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HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires2 ); \
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HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires3 ); \
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result = ((hires1&hires2)|(hires1&hires3)|(hires2&hires3)) >> 16; \
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CYG_MACRO_END
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#define HAL_SPARC_86940_WRITE( reg, value ) CYG_MACRO_START \
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cyg_uint32 hival = (value) << 16; \
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HAL_SPARC_ASI_4_WRITE( reg + HAL_SPARC_86940_BASE, hival ); \
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CYG_MACRO_END
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// Registers are at word offsets
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#define HAL_SPARC_86940_REG_SDTR0_TXDATA ( 0x08 * 4 )
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#define HAL_SPARC_86940_REG_SDTR0_RXDATA ( 0x08 * 4 )
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#define HAL_SPARC_86940_REG_SDTR0_STAT ( 0x09 * 4 )
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#define HAL_SPARC_86940_REG_SDTR0_CTRL ( 0x09 * 4 )
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#define HAL_SPARC_86940_REG_SDTR1_TXDATA ( 0x0c * 4 )
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#define HAL_SPARC_86940_REG_SDTR1_RXDATA ( 0x0c * 4 )
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#define HAL_SPARC_86940_REG_SDTR1_STAT ( 0x0d * 4 )
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#define HAL_SPARC_86940_REG_SDTR1_CTRL ( 0x0d * 4 )
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#define HAL_SPARC_86940_REG_PRS0 ( 0x10 * 4 )
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#define HAL_SPARC_86940_REG_TCR0 ( 0x11 * 4 )
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#define HAL_SPARC_86940_REG_RELOAD0 ( 0x12 * 4 )
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#define HAL_SPARC_86940_REG_CNT0 ( 0x13 * 4 )
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#define HAL_SPARC_86940_REG_PRS1 ( 0x14 * 4 )
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#define HAL_SPARC_86940_REG_TCR1 ( 0x15 * 4 )
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#define HAL_SPARC_86940_REG_RELOAD1 ( 0x16 * 4 )
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#define HAL_SPARC_86940_REG_CNT1 ( 0x17 * 4 )
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#define HAL_SPARC_86940_REG_TCR2 ( 0x19 * 4 )
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#define HAL_SPARC_86940_REG_RELOAD2 ( 0x1A * 4 )
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#define HAL_SPARC_86940_REG_CNT2 ( 0x1B * 4 )
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#define HAL_SPARC_86940_REG_TCR3 ( 0x1D * 4 )
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#define HAL_SPARC_86940_REG_RELOAD3 ( 0x1E * 4 )
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#define HAL_SPARC_86940_REG_CNT3 ( 0x1F * 4 )
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// Glue together to access them neatly
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#define HAL_SPARC_86940_SDTR0_TXDATA_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR0_TXDATA, v )
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#define HAL_SPARC_86940_SDTR0_RXDATA_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR0_RXDATA, r )
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#define HAL_SPARC_86940_SDTR0_STAT_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR0_STAT, r )
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#define HAL_SPARC_86940_SDTR0_CTRL_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR0_CTRL, v )
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#define HAL_SPARC_86940_SDTR1_TXDATA_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR1_TXDATA, v )
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#define HAL_SPARC_86940_SDTR1_RXDATA_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR1_RXDATA, r )
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#define HAL_SPARC_86940_SDTR1_STAT_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR1_STAT, r )
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#define HAL_SPARC_86940_SDTR1_CTRL_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR1_CTRL, v )
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#define HAL_SPARC_86940_PRS0_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_PRS0, r )
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#define HAL_SPARC_86940_PRS0_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_PRS0, v )
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#define HAL_SPARC_86940_TCR0_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR0, r )
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#define HAL_SPARC_86940_TCR0_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR0, v )
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#define HAL_SPARC_86940_RELOAD0_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD0, r )
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#define HAL_SPARC_86940_RELOAD0_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD0, v )
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#define HAL_SPARC_86940_CNT0_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT0, r )
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#define HAL_SPARC_86940_CNT0_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT0, v )
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#define HAL_SPARC_86940_PRS1_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_PRS1, r )
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#define HAL_SPARC_86940_PRS1_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_PRS1, v )
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| 266 |
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#define HAL_SPARC_86940_TCR1_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR1, r )
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| 268 |
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#define HAL_SPARC_86940_TCR1_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR1, v )
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| 271 |
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#define HAL_SPARC_86940_RELOAD1_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD1, r )
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#define HAL_SPARC_86940_RELOAD1_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD1, v )
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| 275 |
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| 276 |
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#define HAL_SPARC_86940_CNT1_READ( r ) \
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| 277 |
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT1, r )
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| 278 |
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#define HAL_SPARC_86940_CNT1_WRITE( v ) \
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| 279 |
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT1, v )
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| 280 |
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| 281 |
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#define HAL_SPARC_86940_TCR2_READ( r ) \
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| 282 |
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR2, r )
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| 283 |
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#define HAL_SPARC_86940_TCR2_WRITE( v ) \
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| 284 |
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR2, v )
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| 285 |
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| 286 |
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#define HAL_SPARC_86940_RELOAD2_READ( r ) \
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| 287 |
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD2, r )
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| 288 |
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#define HAL_SPARC_86940_RELOAD2_WRITE( v ) \
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| 289 |
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD2, v )
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| 290 |
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| 291 |
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#define HAL_SPARC_86940_CNT2_READ( r ) \
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| 292 |
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT2, r )
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| 293 |
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#define HAL_SPARC_86940_CNT2_WRITE( v ) \
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| 294 |
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT2, v )
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| 295 |
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| 296 |
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#define HAL_SPARC_86940_TCR3_READ( r ) \
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| 297 |
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR3, r )
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| 298 |
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#define HAL_SPARC_86940_TCR3_WRITE( v ) \
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| 299 |
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR3, v )
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| 300 |
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| 301 |
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#define HAL_SPARC_86940_RELOAD3_READ( r ) \
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| 302 |
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD3, r )
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| 303 |
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#define HAL_SPARC_86940_RELOAD3_WRITE( v ) \
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| 304 |
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD3, v )
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| 305 |
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| 306 |
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#define HAL_SPARC_86940_CNT3_READ( r ) \
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| 307 |
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT3, r )
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| 308 |
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#define HAL_SPARC_86940_CNT3_WRITE( v ) \
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| 309 |
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT3, v )
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| 310 |
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| 311 |
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/*---------------------------------------------------------------------------*/
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| 312 |
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/* end of hal_hwio.h */
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| 313 |
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#endif /* CYGONCE_HAL_HAL_HWIO_H */
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