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#ifndef CYGONCE_HAL_HALBOOT_SI /* -*-asm-*- */
2
#define CYGONCE_HAL_HALBOOT_SI
3
// ====================================================================
4
//
5
//      /halboot.si
6
//
7
//      HAL bootup platform-oriented code (assembler)
8
//
9
// ====================================================================
10
//####ECOSGPLCOPYRIGHTBEGIN####
11
// -------------------------------------------
12
// This file is part of eCos, the Embedded Configurable Operating System.
13
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14
//
15
// eCos is free software; you can redistribute it and/or modify it under
16
// the terms of the GNU General Public License as published by the Free
17
// Software Foundation; either version 2 or (at your option) any later version.
18
//
19
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
21
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
22
// for more details.
23
//
24
// You should have received a copy of the GNU General Public License along
25
// with eCos; if not, write to the Free Software Foundation, Inc.,
26
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27
//
28
// As a special exception, if other files instantiate templates or use macros
29
// or inline functions from this file, or you compile this file and link it
30
// with other works to produce a work based on this file, this file does not
31
// by itself cause the resulting work to be covered by the GNU General Public
32
// License. However the source code for this file must still be made available
33
// in accordance with section (3) of the GNU General Public License.
34
//
35
// This exception does not invalidate any other reasons why a work based on
36
// this file might be covered by the GNU General Public License.
37
//
38
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39
// at http://sources.redhat.com/ecos/ecos-license/
40
// -------------------------------------------
41
//####ECOSGPLCOPYRIGHTEND####
42
// ====================================================================
43
//#####DESCRIPTIONBEGIN####
44
//
45
// Author(s):           hmt
46
// Contributors:        hmt
47
// Date:                1999-02-01
48
// Purpose:             Bootup code, platform oriented.
49
// Description:
50
//
51
//####DESCRIPTIONEND####
52
//
53
// ====================================================================
54
 
55
// External Platform Initial Setup
56
//
57
// This should set up RAM and caches, and calm down any external
58
// interrupt sources.
59
//
60
// It is just plain included in vectors.S
61
//
62
// RAM has not yet been touched at all; in fact all you have is a
63
// register window selected.
64
 
65
 
66
#ifdef CYG_HAL_STARTUP_RAM
67
        ! Hit the entry point instructions in situ
68
#ifndef CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM
69
        ! *unless* we are going to copy into a different RAM area anyway:
70
        ! copy the real instructions into the vector:
71
        rd      %tbr, %g1
72
        andn    %g1, 0xfff, %g1         ! clear non-address bits
73
        set     real_vector_instructions, %l0
74
        ld      [ %l0 ], %l1
75
        st      %l1, [ %g1 ]            ! into the vector
76
        ld      [ %l0 + 4 ], %l1
77
        st      %l1, [ %g1 + 4 ]        ! into the vector
78
        ! then invalidate the instruction cache:
79
        set     3, %l0
80
        set     0x00001000, %l1
81
        set     0x80001000, %l2
82
        sta     %l0, [ %l1 ] 0x0c
83
        sta     %l0, [ %l2 ] 0x0c
84
        ! and the data cache
85
        sta     %l0, [ %l1 ] 0x0e
86
        sta     %l0, [ %l2 ] 0x0e
87
        nop
88
        nop
89
        nop
90
        nop                             ! should be enough
91
#endif // !CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM
92
#endif // CYG_HAL_STARTUP_RAM
93
 
94
 
95
#include                // a copy of CygMon~s cpu.h
96
 
97
 
98
/* Address of clock switch */
99
#define CLKSW_ADDR  0x01000003
100
 
101
/* Address of SW1 */
102
#define SW1_ADDR  0x02000003
103
 
104
/* Address of LED bank */
105
#define LED_ADDR  0x02000003
106
 
107
#define SRAM_BASE 0x30000000
108
#define SRAM_END  0x30080000
109
 
110
 
111
#define DRAM_BASE      0x04000000       /* base of system DRAM */
112
#define CS3_BASE       0x00000000       /* base of internal resource regs */
113
#define CS3_ASI        7                /* ASI of internal resource regs  */
114
 
115
// DRAM_BASE2 is defined so that we run the same RAM-sizing code in both
116
// RAM and ROM startup versions; but the RAM startup one starts RAM sizing
117
// at 0x043ff000 ie. 4k down from the top of the 4M available.
118
 
119
#ifdef CYG_HAL_STARTUP_RAM
120
#define DRAM_BASE2 DRAM_BASE + 0x00400000 - 0x1000
121
#else
122
#define DRAM_BASE2 DRAM_BASE
123
#endif
124
 
125
        .macro led val
126
        sethi   %hi(LED_ADDR),%l7
127
        set     \val,%l6
128
        not     %l6, %l6
129
        stb     %l6,[%l7 + %lo(LED_ADDR)]
130
        .endm
131
 
132
        /*
133
         * First, setup chip selects.
134
         *
135
         * NB: The AMR_VAL macro actually inverts the mask bits. For me, it is
136
         *     more natural to write a 1 bit where I want the address compared.
137
         *     The sparc registers use 0 bits, instead.
138
         */
139
 
140
        /* -CS0 ADDR_MASK:0xfc000000 ASI_MASK:0xfc */
141
        set     AMR_VAL(0xfc,0xfc000000),%l0
142
        mov     AMR0,%l1
143
        sta     %l0,[%l1] 1
144
 
145
        /* -CS1 BASE:0x10000000 ASI:4 */
146
        set     ARSR_VAL(4,0x10000000),%l0
147
        mov     ARSR1,%l1
148
        sta     %l0,[%l1] 1
149
        /* -CS1 ADDR MASK:0xf0000000 ASI MASK:0x7 */
150
        set     AMR_VAL(7,0xf0000000),%l0
151
        mov     AMR1,%l1
152
        sta     %l0,[%l1] 1
153
 
154
        /* -CS2 BASE:0x20000000 ASI:4 */
155
        set     ARSR_VAL(4,0x20000000), %l0
156
        mov     ARSR2,%l1
157
        sta     %l0,[%l1] 1
158
        /* -CS2 ADDR MASK:0xf0000000 ASI MASK:0x7 */
159
        set     AMR_VAL(7,0xf0000000),%l0
160
        mov     AMR2,%l1
161
        sta     %l0,[%l1] 1
162
 
163
        /* -CS3 BASE:CS3_BASE ASI:CS3_ASI */
164
        set     ARSR_VAL(CS3_ASI,CS3_BASE),%l0
165
        mov     ARSR3,%l1
166
        sta     %l0,[%l1] 1
167
        /* -CS3 ADDR MASK:0xffff0000 ASI MASK:0x7 */
168
        set     AMR_VAL(7,0xffff0000),%l0
169
        mov     AMR3,%l1
170
        sta     %l0,[%l1] 1
171
 
172
        /* -CS4 BASE: DRAM_BASE ASI:0xb */
173
        set     ARSR_VAL(0xb,DRAM_BASE),%l0
174
        mov     ARSR4,%l1
175
        sta     %l0,[%l1] 1
176
        /* -CS4 ADDR MASK:0xfc000000 ASI MASK:0xfc */
177
        set     AMR_VAL(0xfc,0xfc000000),%l0
178
        mov     AMR4,%l1
179
        sta     %l0,[%l1] 1
180
 
181
        /* -CS5 BASE:0x30000000 ASI:0xb */
182
        set     ARSR_VAL(0xb,0x30000000),%l0
183
        mov     ARSR5,%l1
184
        sta     %l0,[%l1] 1
185
        /* -CS5 ADDR MASK:0xfff80000 ASI MASK:0xfc */
186
        set     AMR_VAL(0xfc,0xfff80000),%l0
187
        mov     AMR5,%l1
188
        sta     %l0,[%l1] 1
189
 
190
 
191
        /*
192
         * Setup wait states. Each wait state register sets the wait states for
193
         * a pair of chip selects. The lower bits hold the wait state info for
194
         * the lower numbered chip select.
195
         */
196
 
197
        /* -CS0: 5 wait states,  -CS1: 7 wait states */
198
//      set     WSSR_VAL(7,7,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0
199
//      set     WSSR_VAL(4,4,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 // FOUR -> CS1
200
        set     WSSR_VAL(10,10,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 // TEN -> CS1
201
        mov     WSSR0,%l1
202
        sta     %l0,[%l1] 1
203
 
204
        /* -CS2: wait states disabled,  -CS3: wait states disabled */
205
        set     WSSR_VAL(0,0,0,0,0,0),%l0
206
        mov     WSSR1,%l1
207
        sta     %l0,[%l1] 1
208
 
209
        /* -CS4: wait states disabled,  -CS5: 0 wait states */
210
        set     WSSR_VAL(0,0,WSSR_WAITEN|WSSR_OVERRIDE,0,0,0),%l0
211
        mov     WSSR2,%l1
212
        sta     %l0,[%l1] 1
213
 
214
        led     0x10
215
 
216
        /* clear cache/BIU control register */
217
        mov     CBIR,%l1
218
        sta     %g0,[%l1] 1
219
 
220
        /* Read clock switch to determine the value of the refresh timer */
221
        sethi   %hi(CLKSW_ADDR),%l1
222
        ldub    [%l1 + %lo(CLKSW_ADDR)],%l0
223
        btst    0x80,%l0
224
        bne,a   1f
225
        mov     10,%l0          /* force to 10MHz if CLKSW-8 is ON */
226
    1:
227
        umul    %l0,15,%l0
228
        mov     DRLD,%l1
229
        sta     %l0,[%l1] 1
230
        mov     REFTMR,%l1
231
        sta     %l0,[%l1] 1
232
 
233
        /* read SW1 to get DRAM page size */
234
        sethi   %hi(SW1_ADDR),%l1
235
        ldub    [%l1 + %lo(SW1_ADDR)],%l0
236
        btst    0x10,%l0
237
        be,a    1f
238
         mov    0x0e,%l0        /* 1K page if branch taken (SW1-5 is OFF) */
239
        mov     0x06,%l0        /* 2K page (SW1-5 is OFF) */
240
    1:
241
        mov     SPGMR,%l1
242
        sta     %l0,[%l1] 1
243
 
244
        led     0x20
245
 
246
#ifdef CYG_HAL_STARTUP_ROM
247
        /* Turn on all system services */
248
        mov     SSCR_TIMER|SSCR_WAIT|SSCR_CS|SSCR_SAMEPG,%l0
249
        mov     SSCR,%l1
250
        sta     %l0,[%l1] 1
251
        nop
252
        nop
253
        nop
254
        nop
255
 
256
#endif
257
 
258
        led     0x30
259
 
260
        /*
261
         * Initialize caches.
262
         */
263
        sethi   %hi(0x1000),%l0         /* bank 1 invalidate */
264
        sethi   %hi(0x80000000),%l1     /* bank 2 invalidate */
265
        mov     3,%l2                   /* clear lock, lru, and valid bits */
266
        sta     %l2,[%l0] 0xc           /* do it - icache bank 1 */
267
        sta     %l2,[%l0] 0xe           /* do it - dcache bank 1 */
268
        sta     %l2,[%l0 + %l1] 0xc     /* do it - icache bank 2 */
269
        sta     %l2,[%l0 + %l1] 0xe     /* do it - dcache bank 2 */
270
 
271
        /* now, enable caches and buffers */
272
        mov     CBIR_ICEN|CBIR_DCEN|CBIR_PBEN|CBIR_WBEN,%l0
273
        mov     CBIR,%l1
274
        sta     %l0,[%l1] 1
275
        nop
276
        nop
277
        nop
278
        nop
279
 
280
        /* enable data and insn bursts */
281
        mov     BCR_IBE|BCR_DBE,%l0
282
        mov     BCR,%l1
283
        sta     %l0,[%l1] 1
284
        nop
285
        nop
286
        nop
287
        nop
288
 
289
        /*
290
         * DRAM setup/test.
291
         */
292
        led 0x40
293
 
294
        /*
295
         * Test SW1-7 to determine normal or EDO mode.
296
         *   SW1-7 ON  = EDO
297
         *   SW1-7 OFF = Normal.
298
         */
299
        sethi   %hi(SW1_ADDR),%l1
300
        ldub    [%l1 + %lo(SW1_ADDR)],%l7
301
        mov     DBANKR_SA04,%l0         /* DRAM starts at 0x04000000 */
302
        btst    0x40,%l7
303
        bne     1f                      /* branch if SW1-7 is OFF */
304
         mov    SSCR_DRAM,%l1
305
        /* EDO DRAM, enable burst in SSCR and EDO in DBANKR */
306
        or      %l1,SSCR_BURST,%l1
307
        or      %l0,DBANKR_EDO,%l0
308
    1:
309
        /*
310
         * Now, test SW1 to get DRAM page and bank size.
311
         *   SW1-5 ON  = 2k page, 16MB bank. (up to 64MB total)
312
         *   SW1-5 OFF = 1k page, 4MB bank.  (up to 16MB total)
313
         */
314
        btst    0x10,%l7
315
        bne,a   1f                              /* branch if OFF */
316
        or      %l0,DBANKR_4M|DBANKR_CA10,%l0  /* 1K page */
317
        or      %l0,DBANKR_16M|DBANKR_CA11,%l0 /* 2K page */
318
    1:
319
        mov     CS3_BASE+DBANKR,%l2
320
        sta     %l0,[%l2] CS3_ASI
321
 
322
        mov     DTIMR_RPS2|DTIMR_CBR3|DTIMR_CAS2|DTIMR_RP2,%l0
323
        mov     CS3_BASE+DTIMR,%l2
324
        sta     %l0,[%l2] CS3_ASI
325
 
326
        mov     SSCR,%l2
327
        lda     [%l2] 1, %l0
328
        or      %l0,%l1,%l0
329
        sta     %l0,[%l2] 1
330
 
331
        /*
332
         * Test SW1 to get potential DRAM limit.
333
         *   SW1-5 ON  = 2k page, up to 64MB total
334
         *   SW1-5 OFF = 1k page, up to 16MB total
335
         */
336
        btst    0x10,%l7
337
        bne,a   1f                              /* branch if OFF */
338
         sethi  %hi(DRAM_BASE + 16*1024*1024),%l0
339
        sethi   %hi(DRAM_BASE + 64*1024*1024),%l0
340
    1:
341
 
342
        /* subtract 4 to get last valid DRAM address */
343
        add     %l0,-4,%l0
344
 
345
        /* Assume maximim memory and fill with pattern */
346
        set     DRAM_BASE2,%l2
347
        set     0xaaaaaaaa,%l3
348
    1:
349
        st      %l3,[%l2]
350
        cmp     %l2,%l0
351
        blt     1b
352
         add    %l2,4,%l2
353
 
354
        /*
355
         * Go back, read data and compare with written data.
356
         * Fill in with zero as we go along.
357
         */
358
        set     DRAM_BASE2,%l2
359
    1:
360
        ld      [%l2],%l4
361
        cmp     %l4,%l3
362
        bne     2f
363
         st     %g0,[%l2]
364
        cmp     %l2,%l0
365
        blt,a   1b
366
         add    %l2,4,%l2
367
    2:
368
        led     0x50
369
 
370
        sub     %l2,64,%i6
371
        sethi   %hi(DRAM_BASE),%l1
372
        sub     %l2,%l1,%l0
373
        st      %l0,[%i6]
374
 
375
// NOTE that here, the frame pointer is set up to the top of RAM minus a
376
// little bit with the size of RAM at %fp (%i6)
377
#ifdef CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM
378
 
379
        led     0x58
380
 
381
        ! copy the trampoline code into the base of RAM (__ram_vectors_start)
382
        ! including the two ~rogue~ instructions...
383
 
384
        .extern __ram_vectors_start
385
        ! Using the true address here for the copy makes a badly-aligned
386
        ! __ram_vectors less likely to hide as an obscure failure:
387
        set     __ram_vectors_start, %l0 ! get the start of RAM
388
        set     rom_vectors, %l1        ! get the start of the trampoline
389
        set     rom_vectors_end, %l2    ! ...and its end.
390
33:
391
        ldd     [ %l1 ], %l4            ! also uses %l5
392
        std     %l4, [ %l0 ]
393
        inc     8, %l1
394
        inc     8, %l0
395
        cmp     %l1, %l2
396
        bl      33b
397
         nop
398
 
399
        led     0x59
400
 
401
        sethi   %hi(__ram_vectors_start), %g1   ! get the start of RAM
402
        andn    %g1, 0xfff, %g1
403
        set     real_vector_instructions, %l0
404
        ld      [ %l0 ], %l1
405
        st      %l1, [ %g1 ]            ! into the vector
406
        ld      [ %l0 + 4 ], %l1
407
        st      %l1, [ %g1 + 4 ]        ! into the vector
408
 
409
        led     0x5a
410
 
411
        ! then invalidate the instruction cache:
412
        set     3, %l0
413
        set     0x00001000, %l1
414
        set     0x80001000, %l2
415
        sta     %l0, [ %l1 ] 0x0c
416
        sta     %l0, [ %l2 ] 0x0c
417
 
418
        led     0x5b
419
 
420
        ! and the data cache
421
        sta     %l0, [ %l1 ] 0x0e
422
        sta     %l0, [ %l2 ] 0x0e
423
        nop
424
        nop
425
        nop
426
        nop                             ! should be enough
427
 
428
        led     0x5c
429
 
430
        ! and (re)set the tbr, finally.
431
        sethi   %hi(__ram_vectors_start), %g1
432
        andn    %g1, 0xfff, %g1
433
        wr      %g1, %tbr               ! Traps are at RAM start
434
        nop                             ! (__ram_vectors_start)
435
        nop
436
        nop
437
 
438
        led     0x5d
439
 
440
#else
441
 
442
        led     0x5f
443
 
444
#endif // CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM (was CYG_HAL_STARTUP_ROM)
445
 
446
        ! turn on caches - copied from the book
447
#define set_size        64
448
#define ini_tag         0
449
#define adr1            0x00000000
450
#define adr2            0x80000000
451
#define step            16
452
#define CTL_BITS        0x35
453
 
454
        set     set_size, %l7
455
        set     adr1, %o1
456
        set     adr2, %o2
457
        set     ini_tag, %l0
458
10:
459
        sta     %l0, [ %o1 ] 0x0c
460
        sta     %l0, [ %o1 ] 0x0e
461
        sta     %l0, [ %o2 ] 0x0c
462
        sta     %l0, [ %o2 ] 0x0e
463
        add     %o1, step, %o1
464
        subcc   %l7, 1, %l7
465
        bne     10b
466
        add     %o2, step, %o2
467
 
468
        set     0, %l1
469
        set     CTL_BITS, %l2
470
        sta     %l2, [ %l1 ] 0x01
471
        nop
472
        nop
473
        nop
474
        nop     ! delay to let caches stabilize
475
 
476
        led     0x60
477
 
478
        // Now set up the 86940
479
 
480
#define TRGM0   0
481
#define TRGM1   4
482
#define REQSNS  8
483
#define REQCLR 12
484
#define IMASK  16
485
#define IRLAT  20
486
#define IMODE  24
487
 
488
        sethi   %hi( 0x10000000 ), %l1  ! base address of the 86940 companion
489
 
490
        set     0xfffe0000, %l4         ! mask all intrs
491
        add     %l1, IMASK, %l3
492
        sta     %l4, [ %l3 ] 4
493
 
494
        set     0x11400000, %l6         ! Channels 14,12,11 into Active Low
495
        add     %l1, TRGM0, %l3
496
        sta     %l6, [ %l3 ] 4
497
 
498
        set     0x05100000, %l6         ! Channels 5,4,2 into Active Low
499
        add     %l1, TRGM1, %l3
500
        sta     %l6, [ %l3 ] 4
501
 
502
        add     %l1, REQCLR, %l3        ! clear all pending intrs
503
        sta     %l4, [ %l3 ] 4
504
 
505
        set     0x00100000, %l6         ! clear the latch
506
        add     %l1, IRLAT, %l3
507
        sta     %l6, [ %l3 ] 4
508
 
509
        nop
510
        nop
511
        nop
512
 
513
        led     0x70
514
 
515
#endif  /* CYGONCE_HAL_HALBOOT_SI */
516
/* EOF halboot.si */

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