OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sparclite/] [sleb/] [v2_0/] [include/] [pkgconf/] [mlt_sparclite_sleb_ram.mlt] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
version 0
2
region ram 4010000 3f0000 0 !
3
section ram_vectors 0 1 0 1 1 1 1 1 4010000 4010000 rom_vectors rom_vectors !The ram_vectors section is to allow some free space to copy vectors into from the ROM.  This is required to be variable size to accomodate SVT or MVT; 80 bytes vs 4kB.  Copying is not necessary with MVT, but it is optional because it may offer performance gains.  Copying is required for SVT because the (aligned) start of ROM contains initialization instructions.  RAM copy is used rather than leave a big gap in the ROM to get an aligned address for the trampoline code.  For RAM startup, ram_vectors will usually be of size zero, unless MVT and copying are enabled for memory estimation reasons.
4
section rom_vectors 0 8 0 1 0 1 0 1 text text !
5
section text 0 4 0 1 0 1 0 1 fini fini !
6
section fini 0 4 0 1 0 1 0 1 rodata rodata !
7
section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 !
8
section rodata1 0 8 0 1 0 1 0 1 fixup fixup !
9
section fixup 0 8 0 1 0 1 0 1 gcc_except_table gcc_except_table !
10
section gcc_except_table 0 8 0 1 0 1 0 1 data data !
11
section data 0 8 0 1 0 1 0 1 bss bss !
12
section bss 0 8 0 1 0 1 0 1 heap1 heap1 !
13
section heap1 0 8 0 0 0 0 0 0 !

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.