OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sparclite/] [sleb/] [v2_0/] [include/] [pkgconf/] [mlt_sparclite_sleb_rom.ldi] - Blame information for rev 390

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
// eCos memory layout - Fri Oct 20 09:30:14 2000
2
 
3
// This is a generated file - do not edit
4
 
5
#include 
6
 
7
MEMORY
8
{
9
    rom : ORIGIN = 0, LENGTH = 0x20000
10
    ram : ORIGIN = 0x4000000, LENGTH = 0x400000
11
}
12
 
13
SECTIONS
14
{
15
    SECTIONS_BEGIN
16
    SECTION_rom_vectors (rom, 0, LMA_EQ_VMA)
17
    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
18
    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
19
    SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
20
    SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
21
    SECTION_fixup (rom, ALIGN (0x8), LMA_EQ_VMA)
22
    SECTION_gcc_except_table (rom, ALIGN (0x8), LMA_EQ_VMA)
23
    SECTION_ram_vectors (ram, 0x4000000, LMA_EQ_VMA)
24
    SECTION_data (ram, ALIGN (0x8), FOLLOWING (.gcc_except_table))
25
    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
26
    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
27
    SECTIONS_END
28
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.