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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [v85x/] [ceb_v850/] [v2_0/] [include/] [hal_platform_setup.h] - Blame information for rev 174

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#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
#define CYGONCE_HAL_PLATFORM_SETUP_H
 
/*=============================================================================
//
//      hal_platform_setup.h
//
//      Platform specific support for HAL (assembly code)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    gthomas
// Contributors: gthomas, jlarmour
// Date:         2000-03-10
// Purpose:      NEC CEB/V850 platform specific support routines
// Description:
// Usage:       #include <cyg/hal/hal_platform_setup.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/system.h>           // System-wide configuration info
#include <pkgconf/hal.h>              // Architecture independent configuration
#include <cyg/hal/v850_common.h>        
#include CYGBLD_HAL_PLATFORM_H        // Platform specific configuration
 
        .macro  lea     addr,reg
        movhi   hi(\addr),r0,\reg
        movea   lo(\addr),\reg,\reg
        .endm
 
        .macro  PLATFORM_SETUP1
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
        movhi   hi(V850_REGS),r0,r6
 
        // set bus control signals
        mov     0x01,r1
        st.b    r1,lo(V850_REG_SYC)[r6]
 
        // Internal RAM, internal ROM and I/O - no wait states, regardless
        // of the setting of DWC
        // External RAM is 70ns, External ROM is 120ns. Therefore...
#if CYGHWR_HAL_V85X_CPU_FREQ < 14285714
        // External RAM      - 0 wait states
        movea   0x3F00,r0,r1
#elif CYGHWR_HAL_V85X_CPU_FREQ < 28571428
        // External RAM      - 1 wait state
        movea   0x7F00,r0,r1
#elif CYGHWR_HAL_V85X_CPU_FREQ < 42857142
        // External RAM      - 2 wait states
        movea   0xBF00,r0,r1
#else
        // External RAM      - 3 wait states
        movea   0xFF00,r0,r1
#endif
#if CYGHWR_HAL_V85X_CPU_FREQ < 8333333
        // External ROM      - 0 wait states
        ori     0x00FC,r1,r1
#elif CYGHWR_HAL_V85X_CPU_FREQ < 16666667
        // External ROM      - 1 wait states
        ori     0x00FD,r1,r1
#elif CYGHWR_HAL_V85X_CPU_FREQ < 25000000
        // External ROM      - 2 wait states
        ori     0x00FE,r1,r1
#else
        // External ROM      - 3 wait states
        ori     0x00FF,r1,r1
#endif
        st.h    r1,lo(V850_REG_DWC)[r6]
 
        // Internal RAM, ROM, I/O - always 0 idle regardless of the setting
        // of BCC
        // External RAM      - 0 idle
        // External ROM      - 0 idle
        movea   0x2AA8,r0,r1
        st.h    r1,lo(V850_REG_BCC)[r6]
 
        // No INTs on rising edge
        mov     0x00,r1
        st.b    r1,lo(V850_REG_EGP0)[r6]
 
        // enable INTP0 (serial) IRQ only, set for falling edge
        mov     0x01,r1
        st.b    r1,lo(V850_REG_EGN0)[r6]
 
        // Port 1 mode: set serial DSR, RXD and CTS as inputs, and others
        // as outputs
        movea   0x2C,r0,r1
        st.b    r1,lo(V850_REG_PM1)[r6]
 
        // Port 3 mode: SW2 read port: set to all input
        movea   0xFF,r0,r1
        st.b    r1,lo(V850_REG_PM3)[r6]
 
        // Set serial port control inputs (DSR, RXD, CTS) to 1
        // FIXME Why? Also I don't get why the top two bits are set.
        movea   0xEC,r0,r1
        st.b    r1,lo(V850_REG_P1)[r6]
 
        // Enable all outputs for 7-segment LED
        mov     0x00,r1
        st.b    r1,lo(V850_REG_PM10)[r6]
 
        // Set LED to 0
        mov     0x00,r1
        st.b    r1,lo(V850_REG_P10)[r6]
 
        // Init serial port 0 baud rate to divide clock down to 9600 baud
        // by setting baud count here
        // This may seem unnecessary, but setting up the serial allows
        // us to do diag output before HAL diag is initialized. The values
        // are clock dependent however, but this is only for debug so we
        // don't care.
        movea   0xDD,r0,r1
        st.b    r1,lo(V850_REG_BRGC0)[r6]
 
        // and divisor here
        mov     0x03,r1
        st.b    r1,lo(V850_REG_BRGMC00)[r6]
 
        // set serial 0 to enable tx/rx and 8-N-1
        movea   0xC8,r0,r1
        st.b    r1,lo(V850_REG_ASIM0)[r6]
 
        // disable reception of serial interrupts, and set serial interrupt
        // priority to level 7 (lowest)
        movea   0x47,r0,r1
        st.b    r1,lo(V850_REG_STIC0)[r6]
 
        // Memory expansion mode - set to 4MB
        // We could probably set this to 256K (MM==0x4), but there seems
        // no advantage
        mov     0x07,r1
        st.b    r1,lo(V850_REG_MM)[r6]
 
        // Setting the PCC register is tricky - it is a "specific register"
        // We set the CPU clock to full speed
        stsr    PSW,r7
        ori     CYGARC_PSW_NP,r7,r8
        ldsr    r8,PSW
        mov     0x00,r1
        st.b    r1,lo(V850_REG_PRCMD)[r6]
        st.b    r1,lo(V850_REG_PCC)[r6]
        ldsr    r7,PSW
        nop
        nop
        nop
        nop
        nop
#endif
        .endm
 
/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h                                               */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */

Line No.	Rev	Author	Line
1	27	unneback	`#ifndef CYGONCE_HAL_PLATFORM_SETUP_H`
2			`#define CYGONCE_HAL_PLATFORM_SETUP_H`
3
4			`/*=============================================================================`
5			`//`
6			`// hal_platform_setup.h`
7			`//`
8			`// Platform specific support for HAL (assembly code)`
9			`//`
10			`//=============================================================================`
11			`//####ECOSGPLCOPYRIGHTBEGIN####`
12			`// -------------------------------------------`
13			`// This file is part of eCos, the Embedded Configurable Operating System.`
14			`// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.`
15			`//`
16			`// eCos is free software; you can redistribute it and/or modify it under`
17			`// the terms of the GNU General Public License as published by the Free`
18			`// Software Foundation; either version 2 or (at your option) any later version.`
19			`//`
20			`// eCos is distributed in the hope that it will be useful, but WITHOUT ANY`
21			`// WARRANTY; without even the implied warranty of MERCHANTABILITY or`
22			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
23			`// for more details.`
24			`//`
25			`// You should have received a copy of the GNU General Public License along`
26			`// with eCos; if not, write to the Free Software Foundation, Inc.,`
27			`// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.`
28			`//`
29			`// As a special exception, if other files instantiate templates or use macros`
30			`// or inline functions from this file, or you compile this file and link it`
31			`// with other works to produce a work based on this file, this file does not`
32			`// by itself cause the resulting work to be covered by the GNU General Public`
33			`// License. However the source code for this file must still be made available`
34			`// in accordance with section (3) of the GNU General Public License.`
35			`//`
36			`// This exception does not invalidate any other reasons why a work based on`
37			`// this file might be covered by the GNU General Public License.`
38			`//`
39			`// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.`
40			`// at http://sources.redhat.com/ecos/ecos-license/`
41			`// -------------------------------------------`
42			`//####ECOSGPLCOPYRIGHTEND####`
43			`//=============================================================================`
44			`//#####DESCRIPTIONBEGIN####`
45			`//`
46			`// Author(s): gthomas`
47			`// Contributors: gthomas, jlarmour`
48			`// Date: 2000-03-10`
49			`// Purpose: NEC CEB/V850 platform specific support routines`
50			`// Description:`
51			`// Usage: #include <cyg/hal/hal_platform_setup.h>`
52			`//`
53			`//####DESCRIPTIONEND####`
54			`//`
55			`//===========================================================================*/`
56
57			`#include <pkgconf/system.h> // System-wide configuration info`
58			`#include <pkgconf/hal.h> // Architecture independent configuration`
59			`#include <cyg/hal/v850_common.h>`
60			`#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration`
61
62			`.macro lea addr,reg`
63			`movhi hi(\addr),r0,\reg`
64			`movea lo(\addr),\reg,\reg`
65			`.endm`
66
67			`.macro PLATFORM_SETUP1`
68			`#if defined(CYG_HAL_STARTUP_ROM) \|\| defined(CYG_HAL_STARTUP_ROMRAM)`
69			`movhi hi(V850_REGS),r0,r6`
70
71			`// set bus control signals`
72			`mov 0x01,r1`
73			`st.b r1,lo(V850_REG_SYC)[r6]`
74
75			`// Internal RAM, internal ROM and I/O - no wait states, regardless`
76			`// of the setting of DWC`
77			`// External RAM is 70ns, External ROM is 120ns. Therefore...`
78			`#if CYGHWR_HAL_V85X_CPU_FREQ < 14285714`
79			`// External RAM - 0 wait states`
80			`movea 0x3F00,r0,r1`
81			`#elif CYGHWR_HAL_V85X_CPU_FREQ < 28571428`
82			`// External RAM - 1 wait state`
83			`movea 0x7F00,r0,r1`
84			`#elif CYGHWR_HAL_V85X_CPU_FREQ < 42857142`
85			`// External RAM - 2 wait states`
86			`movea 0xBF00,r0,r1`
87			`#else`
88			`// External RAM - 3 wait states`
89			`movea 0xFF00,r0,r1`
90			`#endif`
91			`#if CYGHWR_HAL_V85X_CPU_FREQ < 8333333`
92			`// External ROM - 0 wait states`
93			`ori 0x00FC,r1,r1`
94			`#elif CYGHWR_HAL_V85X_CPU_FREQ < 16666667`
95			`// External ROM - 1 wait states`
96			`ori 0x00FD,r1,r1`
97			`#elif CYGHWR_HAL_V85X_CPU_FREQ < 25000000`
98			`// External ROM - 2 wait states`
99			`ori 0x00FE,r1,r1`
100			`#else`
101			`// External ROM - 3 wait states`
102			`ori 0x00FF,r1,r1`
103			`#endif`
104			`st.h r1,lo(V850_REG_DWC)[r6]`
105
106			`// Internal RAM, ROM, I/O - always 0 idle regardless of the setting`
107			`// of BCC`
108			`// External RAM - 0 idle`
109			`// External ROM - 0 idle`
110			`movea 0x2AA8,r0,r1`
111			`st.h r1,lo(V850_REG_BCC)[r6]`
112
113			`// No INTs on rising edge`
114			`mov 0x00,r1`
115			`st.b r1,lo(V850_REG_EGP0)[r6]`
116
117			`// enable INTP0 (serial) IRQ only, set for falling edge`
118			`mov 0x01,r1`
119			`st.b r1,lo(V850_REG_EGN0)[r6]`
120
121			`// Port 1 mode: set serial DSR, RXD and CTS as inputs, and others`
122			`// as outputs`
123			`movea 0x2C,r0,r1`
124			`st.b r1,lo(V850_REG_PM1)[r6]`
125
126			`// Port 3 mode: SW2 read port: set to all input`
127			`movea 0xFF,r0,r1`
128			`st.b r1,lo(V850_REG_PM3)[r6]`
129
130			`// Set serial port control inputs (DSR, RXD, CTS) to 1`
131			`// FIXME Why? Also I don't get why the top two bits are set.`
132			`movea 0xEC,r0,r1`
133			`st.b r1,lo(V850_REG_P1)[r6]`
134
135			`// Enable all outputs for 7-segment LED`
136			`mov 0x00,r1`
137			`st.b r1,lo(V850_REG_PM10)[r6]`
138
139			`// Set LED to 0`
140			`mov 0x00,r1`
141			`st.b r1,lo(V850_REG_P10)[r6]`
142
143			`// Init serial port 0 baud rate to divide clock down to 9600 baud`
144			`// by setting baud count here`
145			`// This may seem unnecessary, but setting up the serial allows`
146			`// us to do diag output before HAL diag is initialized. The values`
147			`// are clock dependent however, but this is only for debug so we`
148			`// don't care.`
149			`movea 0xDD,r0,r1`
150			`st.b r1,lo(V850_REG_BRGC0)[r6]`
151
152			`// and divisor here`
153			`mov 0x03,r1`
154			`st.b r1,lo(V850_REG_BRGMC00)[r6]`
155
156			`// set serial 0 to enable tx/rx and 8-N-1`
157			`movea 0xC8,r0,r1`
158			`st.b r1,lo(V850_REG_ASIM0)[r6]`
159
160			`// disable reception of serial interrupts, and set serial interrupt`
161			`// priority to level 7 (lowest)`
162			`movea 0x47,r0,r1`
163			`st.b r1,lo(V850_REG_STIC0)[r6]`
164
165			`// Memory expansion mode - set to 4MB`
166			`// We could probably set this to 256K (MM==0x4), but there seems`
167			`// no advantage`
168			`mov 0x07,r1`
169			`st.b r1,lo(V850_REG_MM)[r6]`
170
171			`// Setting the PCC register is tricky - it is a "specific register"`
172			`// We set the CPU clock to full speed`
173			`stsr PSW,r7`
174			`ori CYGARC_PSW_NP,r7,r8`
175			`ldsr r8,PSW`
176			`mov 0x00,r1`
177			`st.b r1,lo(V850_REG_PRCMD)[r6]`
178			`st.b r1,lo(V850_REG_PCC)[r6]`
179			`ldsr r7,PSW`
180			`nop`
181			`nop`
182			`nop`
183			`nop`
184			`nop`
185			`#endif`
186			`.endm`
187
188			`/---------------------------------------------------------------------------/`
189			`/* end of hal_platform_setup.h */`
190			`#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */`

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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [v85x/] [ceb_v850/] [v2_0/] [include/] [hal_platform_setup.h] - Blame information for rev 174