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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [v85x/] [v850/] [v2_0/] [include/] [var_intr.h] - Blame information for rev 174

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#ifndef CYGONCE_HAL_VAR_INTR_H
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#define CYGONCE_HAL_VAR_INTR_H
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//==========================================================================
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//
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//      var_intr.h
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//
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//      NEC V850 Interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    nickg
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// Contributors: nickg, jskov, gthomas, jlarmour
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// Date:         2001-03-21
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// Purpose:      NEC V850 Interrupt support
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// Description:  The macros defined here provide the HAL APIs for handling
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//               interrupts and the clock for variants of the NEC V85x
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//               architecture.
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//
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// Usage:
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//              #include <cyg/hal/var_intr.h>
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//              ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/plf_intr.h>
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//--------------------------------------------------------------------------
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// NEC V850/SA1 (70301x) and V850/SB1 (70303x) vectors.
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// These are the exception codes presented in the Cause register and
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// correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET
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#define CYGNUM_HAL_VECTOR_RESET                0x00
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#define CYGNUM_HAL_VECTOR_NMI                  0x01
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#define CYGNUM_HAL_VECTOR_INTWDT               0x02 // watchdog timer NMI
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#define CYGNUM_HAL_VECTOR_TRAP00               0x04
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#define CYGNUM_HAL_VECTOR_TRAP10               0x05
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#define CYGNUM_HAL_VECTOR_ILGOP                0x06 // illegal opcode
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#define CYGNUM_HAL_VECTOR_INTWDTM              0x08 // watchdog timer maskable
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#define CYGNUM_HAL_VECTOR_INTP0                0x09
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#define CYGNUM_HAL_VECTOR_INTP1                0x0A
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#define CYGNUM_HAL_VECTOR_INTP2                0x0B
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#define CYGNUM_HAL_VECTOR_INTP3                0x0C
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#define CYGNUM_HAL_VECTOR_INTP4                0x0D
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#define CYGNUM_HAL_VECTOR_INTP5                0x0E
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#define CYGNUM_HAL_VECTOR_INTP6                0x0F
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#if CYGINT_HAL_V850_VARIANT_SA1
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#define CYGNUM_HAL_VECTOR_INTWTNI              0x10
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#define CYGNUM_HAL_VECTOR_INTTM00              0x11
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#define CYGNUM_HAL_VECTOR_INTTM01              0x12
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#define CYGNUM_HAL_VECTOR_INTTM10              0x13
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#define CYGNUM_HAL_VECTOR_INTTM11              0x14
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#define CYGNUM_HAL_VECTOR_INTTM2               0x15
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#define CYGNUM_HAL_VECTOR_INTTM3               0x16
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#define CYGNUM_HAL_VECTOR_INTTM4               0x17
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#define CYGNUM_HAL_VECTOR_INTTM5               0x18
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#define CYGNUM_HAL_VECTOR_INTIIC0              0x19
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#define CYGNUM_HAL_VECTOR_INTCSI0              0x19
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#define CYGNUM_HAL_VECTOR_INTSER0              0x1A
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#define CYGNUM_HAL_VECTOR_INTSR0               0x1B
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#define CYGNUM_HAL_VECTOR_INTCSI1              0x1B
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#define CYGNUM_HAL_VECTOR_INTST0               0x1C
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#define CYGNUM_HAL_VECTOR_INTCSI2              0x1D
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#define CYGNUM_HAL_VECTOR_INTSER1              0x1E
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#define CYGNUM_HAL_VECTOR_INTSR1               0x1F
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#define CYGNUM_HAL_VECTOR_INTST1               0x20
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#define CYGNUM_HAL_VECTOR_INTAD                0x21
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#define CYGNUM_HAL_VECTOR_INTDMA0              0x22
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#define CYGNUM_HAL_VECTOR_INTDMA1              0x23
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#define CYGNUM_HAL_VECTOR_INTDMA2              0x24
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#define CYGNUM_HAL_VECTOR_INTWTN               0x25
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#define CYGNUM_HAL_VSR_MIN                     0
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#define CYGNUM_HAL_VSR_MAX                     0x25
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#define CYGNUM_HAL_VSR_COUNT                   0x26
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#elif CYGINT_HAL_V850_VARIANT_SB1
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#define CYGNUM_HAL_VECTOR_INTWTNI              0x14
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#define CYGNUM_HAL_VECTOR_INTTM00              0x15
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#define CYGNUM_HAL_VECTOR_INTTM01              0x16
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#define CYGNUM_HAL_VECTOR_INTTM10              0x17
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#define CYGNUM_HAL_VECTOR_INTTM11              0x18
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#define CYGNUM_HAL_VECTOR_INTTM2               0x19
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#define CYGNUM_HAL_VECTOR_INTTM3               0x1A
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#define CYGNUM_HAL_VECTOR_INTTM4               0x1B
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#define CYGNUM_HAL_VECTOR_INTTM5               0x1C
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#define CYGNUM_HAL_VECTOR_INTTM6               0x1D
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#define CYGNUM_HAL_VECTOR_INTTM7               0x1E
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#define CYGNUM_HAL_VECTOR_INTIIC0              0x1F
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#define CYGNUM_HAL_VECTOR_INTCSI0              0x1F
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#define CYGNUM_HAL_VECTOR_INTSER0              0x20
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#define CYGNUM_HAL_VECTOR_INTSR0               0x21
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#define CYGNUM_HAL_VECTOR_INTCSI1              0x21
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#define CYGNUM_HAL_VECTOR_INTST0               0x22
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#define CYGNUM_HAL_VECTOR_INTCSI2              0x23
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#define CYGNUM_HAL_VECTOR_INTIIC1              0x24
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#define CYGNUM_HAL_VECTOR_INTSER1              0x25
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#define CYGNUM_HAL_VECTOR_INTSR1               0x26
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#define CYGNUM_HAL_VECTOR_INTCSI3              0x26
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#define CYGNUM_HAL_VECTOR_INTST1               0x27
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#define CYGNUM_HAL_VECTOR_INTCSI4              0x28
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#ifdef __SB2
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#define CYGNUM_HAL_VECTOR_INTIE1               0x29
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#define CYGNUM_HAL_VECTOR_INTIE2               0x2A
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#endif
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#define CYGNUM_HAL_VECTOR_INTAD                0x2B
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#define CYGNUM_HAL_VECTOR_INTDMA0              0x2C
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#define CYGNUM_HAL_VECTOR_INTDMA1              0x2D
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#define CYGNUM_HAL_VECTOR_INTDMA2              0x2E
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#define CYGNUM_HAL_VECTOR_INTDMA3              0x2F
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#define CYGNUM_HAL_VECTOR_INTDMA4              0x30
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#define CYGNUM_HAL_VECTOR_INTDMA5              0x31
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#define CYGNUM_HAL_VECTOR_INTWTN               0x32
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#define CYGNUM_HAL_VECTOR_INTKR                0x33
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#define CYGNUM_HAL_VSR_MIN                     0
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#define CYGNUM_HAL_VSR_MAX                     0x33
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#define CYGNUM_HAL_VSR_COUNT                   ((CYGNUM_HAL_VSR_MAX-CYGNUM_HAL_VSR_MIN)+1)
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#else
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# error No v850 variant implemented!
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#endif
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// Min/Max exception numbers and how many there are
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#define CYGNUM_HAL_EXCEPTION_MIN                0
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#define CYGNUM_HAL_EXCEPTION_MAX                7
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#define CYGNUM_HAL_EXCEPTION_COUNT              ((CYGNUM_HAL_EXCEPTION_MAX-CYGNUM_HAL_EXCEPTION_MIN)+1)
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// Min/Max ISR numbers and how many there are
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#define CYGNUM_HAL_ISR_MIN                     0x08
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#define CYGNUM_HAL_ISR_MAX                     CYGNUM_HAL_VSR_MAX
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#define CYGNUM_HAL_ISR_COUNT                   ((CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN)+1)
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// The vector used by the Real time clock.
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#define CYGNUM_HAL_INTERRUPT_RTC               CYGNUM_HAL_VECTOR_INTTM10
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// Mapping from interrupt numbers to hardware registers
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#if CYGINT_HAL_V850_VARIANT_SA1
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#define CYG_HAL_V85X_INTERRUPT_CONTROL_REGISTERS        \
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    (volatile unsigned char *)V850_REG_WDTIC,           \
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    (volatile unsigned char *)V850_REG_PIC0,            \
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    (volatile unsigned char *)V850_REG_PIC1,            \
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    (volatile unsigned char *)V850_REG_PIC2,            \
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    (volatile unsigned char *)V850_REG_PIC3,            \
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    (volatile unsigned char *)V850_REG_PIC4,            \
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    (volatile unsigned char *)V850_REG_PIC5,            \
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    (volatile unsigned char *)V850_REG_PIC6,            \
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    (volatile unsigned char *)V850_REG_WTNIIC,          \
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    (volatile unsigned char *)V850_REG_TMIC00,          \
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    (volatile unsigned char *)V850_REG_TMIC01,          \
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    (volatile unsigned char *)V850_REG_TMIC10,          \
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    (volatile unsigned char *)V850_REG_TMIC11,          \
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    (volatile unsigned char *)V850_REG_TMIC2,           \
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    (volatile unsigned char *)V850_REG_TMIC3,           \
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    (volatile unsigned char *)V850_REG_TMIC4,           \
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    (volatile unsigned char *)V850_REG_TMIC5,           \
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    (volatile unsigned char *)V850_REG_CSIC0,           \
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    (volatile unsigned char *)V850_REG_SERIC0,          \
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    (volatile unsigned char *)V850_REG_CSIC1,           \
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    (volatile unsigned char *)V850_REG_STIC0,           \
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    (volatile unsigned char *)V850_REG_CSIC2,           \
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    (volatile unsigned char *)V850_REG_SERIC1,          \
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    (volatile unsigned char *)V850_REG_SRIC1,           \
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    (volatile unsigned char *)V850_REG_STIC1,           \
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    (volatile unsigned char *)V850_REG_ADIC,            \
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    (volatile unsigned char *)V850_REG_DMAIC0,          \
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    (volatile unsigned char *)V850_REG_DMAIC1,          \
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    (volatile unsigned char *)V850_REG_DMAIC2,          \
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    (volatile unsigned char *)V850_REG_WTNIC
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#elif CYGINT_HAL_V850_VARIANT_SB1
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#define CYG_HAL_V85X_INTERRUPT_CONTROL_REGISTERS        \
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    (volatile unsigned char *)V850_REG_WDTIC,           \
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    (volatile unsigned char *)V850_REG_PIC0,            \
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    (volatile unsigned char *)V850_REG_PIC1,            \
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    (volatile unsigned char *)V850_REG_PIC2,            \
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    (volatile unsigned char *)V850_REG_PIC3,            \
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    (volatile unsigned char *)V850_REG_PIC4,            \
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    (volatile unsigned char *)V850_REG_PIC5,            \
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    (volatile unsigned char *)V850_REG_PIC6,            \
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    NULL,                                               \
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    NULL,                                               \
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    NULL,                                               \
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    NULL,                                               \
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    (volatile unsigned char *)V850_REG_WTNIIC,          \
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    (volatile unsigned char *)V850_REG_TMIC00,          \
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    (volatile unsigned char *)V850_REG_TMIC01,          \
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    (volatile unsigned char *)V850_REG_TMIC10,          \
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    (volatile unsigned char *)V850_REG_TMIC11,          \
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    (volatile unsigned char *)V850_REG_TMIC2,           \
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    (volatile unsigned char *)V850_REG_TMIC3,           \
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    (volatile unsigned char *)V850_REG_TMIC4,           \
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    (volatile unsigned char *)V850_REG_TMIC5,           \
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    (volatile unsigned char *)V850_REG_TMIC6,           \
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    (volatile unsigned char *)V850_REG_TMIC7,           \
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    (volatile unsigned char *)V850_REG_CSIC0,           \
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    (volatile unsigned char *)V850_REG_SERIC0,          \
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    (volatile unsigned char *)V850_REG_CSIC1,           \
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    (volatile unsigned char *)V850_REG_STIC0,           \
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    (volatile unsigned char *)V850_REG_CSIC2,           \
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    (volatile unsigned char *)V850_REG_IICIC1,          \
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    (volatile unsigned char *)V850_REG_SERIC1,          \
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    (volatile unsigned char *)V850_REG_CSIC3,           \
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    (volatile unsigned char *)V850_REG_STIC1,           \
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    (volatile unsigned char *)V850_REG_CSIC4,           \
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    (volatile unsigned char *)V850_REG_IEBIC1,          \
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    (volatile unsigned char *)V850_REG_IEBIC2,          \
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    (volatile unsigned char *)V850_REG_ADIC,            \
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    (volatile unsigned char *)V850_REG_DMAIC0,          \
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    (volatile unsigned char *)V850_REG_DMAIC1,          \
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    (volatile unsigned char *)V850_REG_DMAIC2,          \
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    (volatile unsigned char *)V850_REG_DMAIC3,          \
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    (volatile unsigned char *)V850_REG_DMAIC4,          \
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    (volatile unsigned char *)V850_REG_DMAIC5,          \
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    (volatile unsigned char *)V850_REG_WTNIC,           \
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    (volatile unsigned char *)V850_REG_KRIC
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#endif // elif CYGINT_HAL_V850_VARIANT_SB1
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//--------------------------------------------------------------------------
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// Clock control
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// This is handled by the default code
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270 
//--------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_VAR_INTR_H
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// End of var_intr.h

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