OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [v85x/] [v850/] [v2_0/] [src/] [v850_misc.c] - Blame information for rev 587

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
//==========================================================================
2
//
3
//      v850_misc.c
4
//
5
//      HAL CPU variant miscellaneous functions
6
//
7
//==========================================================================
8
//####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under
14
// the terms of the GNU General Public License as published by the Free
15
// Software Foundation; either version 2 or (at your option) any later version.
16
//
17
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
// for more details.
21
//
22
// You should have received a copy of the GNU General Public License along
23
// with eCos; if not, write to the Free Software Foundation, Inc.,
24
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
//
26
// As a special exception, if other files instantiate templates or use macros
27
// or inline functions from this file, or you compile this file and link it
28
// with other works to produce a work based on this file, this file does not
29
// by itself cause the resulting work to be covered by the GNU General Public
30
// License. However the source code for this file must still be made available
31
// in accordance with section (3) of the GNU General Public License.
32
//
33
// This exception does not invalidate any other reasons why a work based on
34
// this file might be covered by the GNU General Public License.
35
//
36
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
// at http://sources.redhat.com/ecos/ecos-license/
38
// -------------------------------------------
39
//####ECOSGPLCOPYRIGHTEND####
40
//==========================================================================
41
//#####DESCRIPTIONBEGIN####
42
//
43
// Author(s):    gthomas
44
// Contributors: gthomas
45
// Date:         2000-03-15
46
// Purpose:      HAL miscellaneous functions
47
// Description:  This file contains miscellaneous functions provided by the
48
//               HAL.
49
//
50
//####DESCRIPTIONEND####
51
//
52
//========================================================================*/
53
 
54
#include <pkgconf/hal.h>
55
 
56
#include <cyg/infra/cyg_type.h>         // Base types
57
#include <cyg/infra/cyg_ass.h>          // assertion macros
58
 
59
#include <cyg/hal/hal_intr.h>
60
#include <cyg/hal/v850_common.h>
61
 
62
externC void cyg_hal_platform_hardware_init(void);
63
 
64
//
65
// Interrupt management functions
66
//
67
 
68
static volatile unsigned char *interrupt_control_registers[] = {
69
    CYG_HAL_V85X_INTERRUPT_CONTROL_REGISTERS   // Defined in <plf_intr.h>
70
};
71
 
72
#define INT_CONTROL_PENDING   0x80
73
#define INT_CONTROL_DISABLE   0x40
74
#define INT_CONTROL_LEVEL(n)  n
75
 
76
#define INT_CONTROL_DEFAULT INT_CONTROL_DISABLE|INT_CONTROL_LEVEL(7)
77
 
78
//
79
// Mask, i.e. disable, interrupt #vector from occurring
80
//
81
void
82
hal_interrupt_mask(int vector)
83
{
84
    volatile unsigned char *ctl;
85
    CYG_ASSERT(vector >= CYGNUM_HAL_ISR_MIN, "invalid interrupt vector [< MIN]");
86
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX, "invalid interrupt vector [> MAX]");
87
    ctl = interrupt_control_registers[vector-CYGNUM_HAL_ISR_MIN];
88
    CYG_ASSERT((void *)ctl != 0, "invalid interrupt vector [not defined]");
89
    if (ctl ) {
90
        *ctl |= INT_CONTROL_DISABLE;
91
    }
92
}
93
 
94
//
95
// Unmask, i.e. enable, interrupt #vector
96
//
97
void
98
hal_interrupt_unmask(int vector)
99
{
100
    volatile unsigned char *ctl;
101
    CYG_ASSERT(vector >= CYGNUM_HAL_ISR_MIN, "invalid interrupt vector [< MIN]");
102
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX, "invalid interrupt vector [> MAX]");
103
    ctl = interrupt_control_registers[vector-CYGNUM_HAL_ISR_MIN];
104
    CYG_ASSERT((void *)ctl != 0, "invalid interrupt vector [not defined]");
105
    if (ctl ) {
106
        *ctl &= ~INT_CONTROL_DISABLE;
107
    }
108
}
109
 
110
//
111
// Acknowledge, i.e. clear, interrupt #vector
112
//
113
void
114
hal_interrupt_acknowledge(int vector)
115
{
116
    volatile unsigned char *ctl;
117
    CYG_ASSERT(vector >= CYGNUM_HAL_ISR_MIN, "invalid interrupt vector [< MIN]");
118
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX, "invalid interrupt vector [> MAX]");
119
    ctl = interrupt_control_registers[vector-CYGNUM_HAL_ISR_MIN];
120
    CYG_ASSERT((void *)ctl != 0, "invalid interrupt vector [not defined]");
121
    if (ctl ) {
122
        *ctl &= ~INT_CONTROL_PENDING;
123
    }
124
}
125
 
126
static void
127
init_interrupts(void)
128
{
129
    int i;
130
    volatile unsigned char *ctl;
131
    for (i = CYGNUM_HAL_ISR_MIN;  i <= CYGNUM_HAL_ISR_MAX;  i++) {
132
        ctl = interrupt_control_registers[i-CYGNUM_HAL_ISR_MIN];
133
        if (ctl) {
134
            *ctl = INT_CONTROL_DEFAULT;
135
        }
136
    }
137
}
138
 
139
//
140
// Initialize the hardware.  This may involve platform specific code.
141
//
142
void
143
cyg_hal_hardware_init(void)
144
{
145
    init_interrupts();
146
    cyg_hal_platform_hardware_init();
147
}
148
 
149
/*------------------------------------------------------------------------*/
150
/* End of v850_misc.c                                                      */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.