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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [io/] [pci/] [v2_0/] [include/] [pci.h] - Blame information for rev 174

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#ifndef CYGONCE_PCI_H
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#define CYGONCE_PCI_H
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//=============================================================================
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//
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//      pci.h
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//
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//      PCI library
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    jskov, from design by nickg 
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// Contributors: jskov
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// Date:         1999-08-09
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// Purpose:      PCI configuration access
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// Usage:
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//              #include <cyg/io/pci.h>
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// Description: 
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//             This library provides a set of routines for accessing 
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//             the PCI bus configuration space in a portable manner. 
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//             This is provided by two APIs. The high level API (defined
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//             by this file) is used by device drivers, or other code, to
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//             access the PCI configuration space portably. The low level
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//             API (see pci_hw.h) is used  by the PCI library itself
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//             to access the hardware in a platform-specific manner and
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//             may also be used by device drivers to access the PCI
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//             configuration space directly.
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <cyg/infra/cyg_type.h>
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#include <cyg/io/pci_cfg.h>
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#include <cyg/io/pci_hw.h>
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//------------------------------------------------------------------
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// The PCI memory space can span 64 bits, IO space only 32 bits
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typedef CYG_WORD64 CYG_PCI_ADDRESS64;
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typedef CYG_WORD32 CYG_PCI_ADDRESS32;
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//------------------------------------------------------------------
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// Macros for manufacturing and decomposing device ids
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typedef CYG_WORD32 cyg_pci_device_id;           // PCI device ID
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#define CYG_PCI_DEV_MAKE_ID(__bus,__devfn) (((__bus)<<16)|((__devfn)<<8))
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#define CYG_PCI_DEV_GET_BUS(__devid) ((__devid>>16)&0xFF)
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#define CYG_PCI_DEV_GET_DEVFN(__devid) ((__devid>>8)&0xFF)
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#define CYG_PCI_NULL_DEVID 0xffffffff
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#define CYG_PCI_NULL_DEVFN 0xffff
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//------------------------------------------------------------------
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// PCI device data definitions and structures
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typedef enum {
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    CYG_PCI_HEADER_NORMAL = 0,
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    CYG_PCI_HEADER_BRIDGE = 1,
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    CYG_PCI_HEADER_CARDBUS_BRIDGE = 2
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} cyg_pci_header_type;
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typedef struct                          // PCI device data
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{
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    cyg_pci_device_id devid;            // ID of this device
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    // The following fields are read out of the
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    // config space for this device.
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    cyg_uint16  vendor;                 // vendor ID
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    cyg_uint16  device;                 // device ID
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    cyg_uint16  command;                // command register
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    cyg_uint16  status;                 // status register
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    cyg_uint32  class_rev;              // class+revision
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    cyg_uint8   cache_line_size;        // cache line size
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    cyg_uint8   latency_timer;          // latency timer
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    cyg_pci_header_type header_type;    // header type
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    cyg_uint8   bist;                   // Built-in Self-Test
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    cyg_uint32  base_address[6];        // Memory base address registers
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    // The following fields are used by the resource allocation
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    // routines to keep track of allocated resources.
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    cyg_uint32 num_bars;
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    cyg_uint32 base_size[6];            // Memory size for each base address
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    cyg_uint32 base_map[6];             // Physical address mapped
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    CYG_ADDRWORD hal_vector;            // HAL interrupt vector used by
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                                        // device if int_line!=0
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    // One of the following unions will be filled in according to
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    // the value of the header_type field.
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    union
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    {
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        struct
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        {
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            cyg_uint32  cardbus_cis;    // CardBus CIS Pointer
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            cyg_uint16  sub_vendor;     // subsystem vendor id
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            cyg_uint16  sub_id;         // subsystem id
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            cyg_uint32  rom_address;    // ROM address register
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            cyg_uint8   cap_list;       // capability list
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            cyg_uint8   reserved1[7];
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            cyg_uint8   int_line;       // interrupt line
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            cyg_uint8   int_pin;        // interrupt pin
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            cyg_uint8   min_gnt;        // timeslice request
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            cyg_uint8   max_lat;        // priority-level request
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        } normal;
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        struct
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        {
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            cyg_uint8   pri_bus;                // primary bus number
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            cyg_uint8   sec_bus;                // secondary bus number
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            cyg_uint8   sub_bus;                // subordinate bus number
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            cyg_uint8   sec_latency_timer;      // secondary bus latency
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            cyg_uint8   io_base;
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            cyg_uint8   io_limit;
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            cyg_uint16  sec_status;             // secondary bus status
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            cyg_uint16  mem_base;
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            cyg_uint16  mem_limit;
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            cyg_uint16  prefetch_base;
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            cyg_uint16  prefetch_limit;
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            cyg_uint32  prefetch_base_upper32;
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            cyg_uint32  prefetch_limit_upper32;
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            cyg_uint16  io_base_upper16;
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            cyg_uint16  io_limit_upper16;
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            cyg_uint8   reserved1[4];
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            cyg_uint32  rom_address;            // ROM address register
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            cyg_uint8   int_line;               // interrupt line
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            cyg_uint8   int_pin;                // interrupt pin
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            cyg_uint16  control;                // bridge control
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        } bridge;
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        struct
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        {
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            // Not yet supported
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        } cardbus_bridge;
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    } header;
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} cyg_pci_device;
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//------------------------------------------------------------------------
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// Init
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externC void cyg_pci_init( void );
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//------------------------------------------------------------------------
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// Common device configuration access functions
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// This function gets the PCI configuration information for the
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// device indicated in devid. The common fields of the cyg_pci_device
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// structure, and the appropriate fields of the relevant header union
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// member are filled in from the device's configuration space. If the
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// device has not been enabled, then this function will also fetch
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// the size and type information from the base address registers and
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// place it in the base_size[] array.
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externC void cyg_pci_get_device_info ( cyg_pci_device_id devid,
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                                        cyg_pci_device *dev_info );
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188
 
189
// This function sets the PCI configuration information for the
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// device indicated in devid. Only the configuration space registers
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// that are writable are actually written. Once all the fields have
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// been written, the device info will be read back into *dev_info, so
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// that it reflects the true state of the hardware.
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externC void cyg_pci_set_device_info ( cyg_pci_device_id devid,
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                                       cyg_pci_device *dev_info );
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//------------------------------------------------------------------------
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// Device find functions
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// Searches the PCI bus configuration space for a device with the
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// given vendor and device ids. The search starts at the device
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// pointed to by devid, or at the first slot if it contains
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// CYG_PCI_NULL_DEVID. *devid will be updated with the ID of the next
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// device found. Returns true if one is found and false if not.
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externC cyg_bool cyg_pci_find_device( cyg_uint16 vendor, cyg_uint16 device,
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                                      cyg_pci_device_id *devid );
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// Searches the PCI bus configuration space for a device with the
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// given class code.  The search starts at the device pointed to by
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// devid, or at the first slot if it contains CYG_PCI_NULL_DEVID.
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// *devid will be updated with the ID of the next device found.
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// Returns true if one is found and false if not.
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externC cyg_bool cyg_pci_find_class( cyg_uint32 dev_class,
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                                     cyg_pci_device_id *devid );
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// Searches the PCI bus configuration space for a device whose properties
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// match those required by the match_func, which the user supplies.  The
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// match_func's arguments are vendor, device, class exactly as they might
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// be in the two APIs above.  The additional parameter is for any state
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// which a caller might wish available to its callback routine.
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// The search starts at the device pointed to by
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// devid, or at the first slot if it contains CYG_PCI_NULL_DEVID.  *devid
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// will be updated with the ID of the next device found.  Returns true if
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// one is found and false if not.
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typedef cyg_bool (cyg_pci_match_func)( cyg_uint16,/* vendor */
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                                       cyg_uint16,/* device */
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                                       cyg_uint32,/* class  */
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                                       void * /* arbitrary user data */ );
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externC cyg_bool cyg_pci_find_matching( cyg_pci_match_func *matchp,
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                                        void * match_callback_data,
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                                        cyg_pci_device_id *devid );
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// Searches the PCI configuration space for the next valid device
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// after cur_devid. If cur_devid is given the value
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// CYG_PCI_NULL_DEVID, then the search starts at the first slot. It
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// is permitted for next_devid to point to the cur_devid.  Returns
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// true if another device is found and false if not.
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externC cyg_bool cyg_pci_find_next( cyg_pci_device_id cur_devid,
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                                    cyg_pci_device_id *next_devid );
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//------------------------------------------------------------------------
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// Resource Allocation
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// These routines allocate memory and IO space to PCI devices.
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// Allocate memory and IO space to all base address registers using
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// the current memory and IO base addresses in the library. If
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// dev_info does not contain valid base_size[] entries, then the
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// result is false.
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externC cyg_bool cyg_pci_configure_device( cyg_pci_device *dev_info );
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// Allocate memory and IO space for all devices found on the given
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// bus and its subordinate busses. This routine recurses when a
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// PCI-to-PCI bridge is encountered. The next_bus argument points
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// to a variable holding the bus number of the next PCI bus to
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// be allocated when a bridge is encountered. This routine returns
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// true if successful, false if unsuccessful.
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externC cyg_bool cyg_pci_configure_bus( cyg_uint8 bus,
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                                        cyg_uint8 *next_bus );
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// These routines set the base addresses for memory and IO mappings
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// to be used by the memory allocation routines. Normally these base
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// addresses will be set to default values based on the platform,
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// these routines allow those to be changed by application code if
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// necessary.
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externC void cyg_pci_set_memory_base( CYG_PCI_ADDRESS64 base );
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externC void cyg_pci_set_io_base( CYG_PCI_ADDRESS32 base );
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// These routines allocate memory or IO space to the base address
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// register indicated by bar. The base address in *base will be
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// correctly aligned and the address of the next free location will
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// be written back into it if the allocation succeeds. If the base
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// address register is of the wrong type for this allocation, or
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// dev_info does not contain valid base_size[] entries, the result is
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// false.
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externC cyg_bool cyg_pci_allocate_memory( cyg_pci_device *dev_info,
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                                          cyg_uint32 bar,
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                                          CYG_PCI_ADDRESS64 *base );
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externC cyg_bool cyg_pci_allocate_io( cyg_pci_device *dev_info,
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                                      cyg_uint32 bar,
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                                      CYG_PCI_ADDRESS32 *base );
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// Translate the device's PCI interrupt (INTA#-INTD#) to the
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// associated HAL vector. This may also depend on which slot the
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// device occupies. If the device may generate interrupts, the
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// translated vector number will be stored in vec and the result is
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// true. Otherwise the result is false.
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externC cyg_bool cyg_pci_translate_interrupt( cyg_pci_device *dev_info,
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                                              CYG_ADDRWORD *vec );
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//----------------------------------------------------------------------
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// Specific device configuration access functions
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// Read functions
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// These functions read registers of the appropriate size from the
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// configuration space of the given device. They should mainly be
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// used to access registers that are device specific. General PCI
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// registers are best accessed through cyg_pci_get_device_info().
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externC void cyg_pci_read_config_uint8( cyg_pci_device_id devid,
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                                        cyg_uint8 offset, cyg_uint8 *val);
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externC void cyg_pci_read_config_uint16( cyg_pci_device_id devid,
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                                         cyg_uint8 offset, cyg_uint16 *val);
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externC void cyg_pci_read_config_uint32( cyg_pci_device_id devid,
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                                         cyg_uint8 offset, cyg_uint32 *val);
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// Write functions
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// These functions write registers of the appropriate size to the
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// configuration space of the given device. They should mainly be
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// used to access registers that are device specific. General PCI
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// registers are best accessed through
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// cyg_pci_get_device_info(). Writing the general registers this way
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// may render the contents of a cyg_pci_device structure invalid.
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externC void cyg_pci_write_config_uint8( cyg_pci_device_id devid,
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                                         cyg_uint8 offset, cyg_uint8 val);
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externC void cyg_pci_write_config_uint16( cyg_pci_device_id devid,
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                                          cyg_uint8 offset, cyg_uint16 val);
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externC void cyg_pci_write_config_uint32( cyg_pci_device_id devid,
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                                          cyg_uint8 offset, cyg_uint32 val);
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324
 
325
//----------------------------------------------------------------------
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// Functions private to the PCI library. These should only be used by
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// tests.
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externC cyg_bool cyg_pci_allocate_memory_priv(cyg_pci_device *dev_info,
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                                              cyg_uint32 bar,
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                                              CYG_PCI_ADDRESS64 *base,
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                                             CYG_PCI_ADDRESS64 *assigned_addr);
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externC cyg_bool cyg_pci_allocate_io_priv( cyg_pci_device *dev_info,
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                                           cyg_uint32 bar,
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                                           CYG_PCI_ADDRESS32 *base,
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                                           CYG_PCI_ADDRESS32 *assigned_addr);
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337
 
338
//----------------------------------------------------------------------
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// Bus probing limits.
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// Note: these can be overridden by the platform
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#ifndef CYG_PCI_MAX_BUS
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#define CYG_PCI_MAX_BUS                      8  // Eight is enough?
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#endif
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#ifndef CYG_PCI_MAX_DEV
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#define CYG_PCI_MAX_DEV                      32
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#endif
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#ifndef CYG_PCI_MIN_DEV
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#define CYG_PCI_MIN_DEV                      0
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#endif
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#ifndef CYG_PCI_MAX_FN
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#define CYG_PCI_MAX_FN                       8
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#endif
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#ifndef CYG_PCI_MAX_BAR
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#define CYG_PCI_MAX_BAR                      6
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#endif
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357
//-----------------------------------------------------------------------------
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#endif // ifndef CYGONCE_PCI_H
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// End of pci.h

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