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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [kernel/] [v2_0/] [include/] [intr.hxx] - Blame information for rev 332

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#ifndef CYGONCE_KERNEL_INTR_HXX
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#define CYGONCE_KERNEL_INTR_HXX
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//==========================================================================
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//
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//      intr.hxx
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//
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//      Interrupt class declaration(s)
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):   nickg
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// Contributors:        nickg
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// Date:        1997-09-09
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// Purpose:     Define Interrupt class interfaces
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// Description: The classes defined here provide the APIs for handling
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//              interrupts.
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// Usage:       #include "intr.hxx"
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include 
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#include 
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// -------------------------------------------------------------------------
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// Default definitions
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// Some HALs define the ISR table to be a different size to the number
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// of ISR vectors. These HALs will define CYGNUM_HAL_ISR_TABLE_SIZE. All
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// other HALs will have the table size equal to the number of vectors.
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#ifndef CYGNUM_HAL_ISR_TABLE_SIZE
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# define CYGNUM_HAL_ISR_TABLE_SIZE      CYGNUM_HAL_ISR_COUNT
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#endif
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// -------------------------------------------------------------------------
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// Function prototype typedefs
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// VSR = Vector Service Routine. This is the code attached directly to an
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// interrupt vector. It is very architecture/platform specific and usually
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// must be written in assembler.
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typedef void  cyg_VSR();
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// ISR = Interrupt Service Routine. This is called from the default
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// VSR in response to an interrupt. It may access shared data but may
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// not call kernel routines. The return value may be
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// Cyg_Interrupt::HANDLED and/or Cyg_Interrupt::CALL_DSR.
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typedef cyg_uint32 cyg_ISR(cyg_vector vector, CYG_ADDRWORD data);
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// DSR = Deferred Service Routine. This is called if the ISR returns
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// the Cyg_Interrupt::CALL_DSR bit. It is called at a "safe" point in
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// the kernel where it may make calls on kernel routines. The count
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// argument indicates how many times the ISR has asked for the DSR to
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// be posted since the last time the DSR ran.
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typedef void cyg_DSR(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data);
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// -------------------------------------------------------------------------
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// Include HAL definitions
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class Cyg_Interrupt;
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#include 
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#include 
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#ifndef HAL_INTERRUPT_STACK_CALL_PENDING_DSRS
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#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS()    \
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      Cyg_Interrupt::call_pending_DSRs_inner()
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#endif
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externC void interrupt_end(
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    cyg_uint32          isr_ret,
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    Cyg_Interrupt       *intr,
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    HAL_SavedRegisters  *ctx
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    );
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externC void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
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externC void cyg_interrupt_call_pending_DSRs( void );
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// -------------------------------------------------------------------------
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// Interrupt class. This both represents each interrupt and provides a static
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// interface for controlling the interrupt hardware.
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class Cyg_Interrupt
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{
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    friend class Cyg_Scheduler;
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    friend void interrupt_end( cyg_uint32,
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                               Cyg_Interrupt *,
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                               HAL_SavedRegisters *);
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    friend void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
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    friend void cyg_interrupt_call_pending_DSRs( void );
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    cyg_vector          vector;         // Interrupt vector
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    cyg_priority        priority;       // Queuing priority
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    cyg_ISR             *isr;           // Pointer to ISR
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    cyg_DSR             *dsr;           // Pointer to DSR
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    CYG_ADDRWORD        data;           // Data pointer
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    // DSR handling interface called by the scheduler
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                                        // Check for pending DSRs
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    static cyg_bool     DSRs_pending();
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                                        // Call any pending DSRs
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    static void         call_pending_DSRs();
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    static void         call_pending_DSRs_inner();
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    // DSR handling interface called by the scheduler and HAL
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    // interrupt arbiters.
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    void                post_dsr();     // Post the DSR for this interrupt
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    // Data structures for handling DSR calls.  We implement two DSR
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    // handling mechanisms, a list based one and a table based
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    // one. The list based mechanism is safe with respect to temporary
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    // overloads and will not run out of resource. However it requires
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    // extra data per interrupt object, and interrupts must be turned
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    // off briefly when delivering the DSR. The table based mechanism
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    // does not need unnecessary interrupt switching, but may be prone
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    // to overflow on overload. However, since a correctly programmed
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    // real time application should not experience such a condition,
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    // the table based mechanism is more efficient for real use. The
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    // list based mechainsm is enabled by default since it is safer to
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    // use during development.
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#ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
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    static Cyg_Interrupt *dsr_table[CYGNUM_KERNEL_CPU_MAX]
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                                   [CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]
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                                   CYGBLD_ANNOTATE_VARIABLE_INTR;
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    static cyg_ucount32 dsr_table_head[CYGNUM_KERNEL_CPU_MAX]
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                                      CYGBLD_ANNOTATE_VARIABLE_INTR;
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    static volatile cyg_ucount32 dsr_table_tail[CYGNUM_KERNEL_CPU_MAX]
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                                               CYGBLD_ANNOTATE_VARIABLE_INTR;
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#endif
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#ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
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    // Number of DSR posts made
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    volatile cyg_ucount32 dsr_count CYGBLD_ANNOTATE_VARIABLE_INTR;
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    // next DSR in list
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    Cyg_Interrupt* volatile next_dsr CYGBLD_ANNOTATE_VARIABLE_INTR;
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    // static list of pending DSRs
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    static Cyg_Interrupt* volatile dsr_list[CYGNUM_KERNEL_CPU_MAX]
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                                           CYGBLD_ANNOTATE_VARIABLE_INTR;
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#endif
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#ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
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    // The default mechanism for handling interrupts is to attach just
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    // one Interrupt object to each vector. In some cases, and on some
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    // hardware, this is not possible, and each vector must carry a chain
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    // of interrupts.
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    Cyg_Interrupt       *next;          // Next Interrupt in list
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    // Chaining ISR inserted in HAL vector
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    static cyg_uint32 chain_isr(cyg_vector vector, CYG_ADDRWORD data);
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    // Table of interrupt chains
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    static Cyg_Interrupt *chain_list[CYGNUM_HAL_ISR_TABLE_SIZE];
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#endif
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    // Interrupt disable data. Interrupt disable can be nested. On
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    // each CPU this is controlled by disable_counter[cpu]. When the
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    // counter is first incremented from zero to one, the
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    // interrupt_disable_spinlock is claimed using spin_intsave(), the
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    // original interrupt enable state being saved in
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    // interrupt_disable_state[cpu].  When the counter is decremented
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    // back to zero the spinlock is cleared using clear_intsave().
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    // The spinlock is necessary in SMP systems since a thread
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    // accessing data shared with an ISR may be scheduled on a
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    // different CPU to the one that handles the interrupt. So, merely
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    // blocking local interrupts would be ineffective. SMP aware
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    // device drivers should either use their own spinlocks to protect
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    // data, or use the API supported by this class, via
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    // cyg_drv_isr_lock()/_unlock(). Note that it now becomes
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    // essential that ISRs do this if they are to be SMP-compatible.
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    // In a single CPU system, this mechanism reduces to just
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    // disabling/enabling interrupts.
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    // Disable level counter. This counts the number of times
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    // interrupts have been disabled.
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    static volatile cyg_int32 disable_counter[CYGNUM_KERNEL_CPU_MAX]
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                                              CYGBLD_ANNOTATE_VARIABLE_INTR;
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    // Interrupt disable spinlock. This is claimed by any CPU that has
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    // disabled interrupts via the Cyg_Interrupt API.
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    static Cyg_SpinLock interrupt_disable_spinlock CYGBLD_ANNOTATE_VARIABLE_INTR;
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    // Saved interrupt state. When each CPU first disables interrupts
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    // the original state of the interrupts are saved here to be
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    // restored later.
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    static CYG_INTERRUPT_STATE interrupt_disable_state[CYGNUM_KERNEL_CPU_MAX]
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                                                       CYGBLD_ANNOTATE_VARIABLE_INTR;
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public:
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    Cyg_Interrupt                       // Initialize interrupt
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    (
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        cyg_vector      vector,         // Vector to attach to
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        cyg_priority    priority,       // Queue priority
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        CYG_ADDRWORD    data,           // Data pointer
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        cyg_ISR         *isr,           // Interrupt Service Routine
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        cyg_DSR         *dsr            // Deferred Service Routine
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        );
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    ~Cyg_Interrupt();
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    // ISR return values
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    enum {
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        HANDLED  = 1,                   // Interrupt was handled
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        CALL_DSR = 2                    // Schedule DSR
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    };
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    // Interrupt management
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    void        attach();               // Attach to vector
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    void        detach();               // Detach from vector
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    // Static Interrupt management functions
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    // Get the current service routine
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    static void get_vsr(cyg_vector vector, cyg_VSR **vsr);
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    // Install a vector service routine
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    static void set_vsr(
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        cyg_vector vector,              // hardware vector to replace
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        cyg_VSR *vsr,                   // my new service routine
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        cyg_VSR **old = NULL            // pointer to old vsr, if required
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        );
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    // Static interrupt masking functions
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    // Disable interrupts at the CPU
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    static void disable_interrupts();
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302
    // Re-enable CPU interrupts
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    static void enable_interrupts();
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    // Are interrupts enabled at the CPU?
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    static inline cyg_bool interrupts_enabled()
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    {
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        return (0 == disable_counter[CYG_KERNEL_CPU_THIS()]);
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    }
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    // Get the vector for the following calls
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    inline cyg_vector get_vector()
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    {
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        return vector;
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    }
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    // Static PIC control functions
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    // Mask a specific interrupt in a PIC
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    static void mask_interrupt(cyg_vector vector);
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    // The same but not interrupt safe
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    static void mask_interrupt_intunsafe(cyg_vector vector);
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    // Clear PIC mask
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    static void unmask_interrupt(cyg_vector vector);
326
    // The same but not interrupt safe
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    static void unmask_interrupt_intunsafe(cyg_vector vector);
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    // Acknowledge interrupt at PIC
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    static void acknowledge_interrupt(cyg_vector vector);
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332
    // Change interrupt detection at PIC
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    static void configure_interrupt(
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        cyg_vector vector,              // vector to control
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        cyg_bool level,                 // level or edge triggered
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        cyg_bool up                     // hi/lo level, rising/falling edge
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        );
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#ifdef CYGPKG_KERNEL_SMP_SUPPORT
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341
    // SMP support for associating an interrupt with a specific CPU.
342
 
343
    static void set_cpu( cyg_vector, HAL_SMP_CPU_TYPE cpu );
344
    static HAL_SMP_CPU_TYPE get_cpu( cyg_vector );
345
 
346
#endif
347
};
348
 
349
#ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS
350
// -------------------------------------------------------------------------
351
// Check for pending DSRs
352
 
353
inline cyg_bool Cyg_Interrupt::DSRs_pending()
354
{
355
    HAL_SMP_CPU_TYPE cpu = CYG_KERNEL_CPU_THIS();
356
#ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
357
 
358
    return dsr_table_head[cpu] != dsr_table_tail[cpu];
359
 
360
#endif
361
#ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
362
 
363
    return dsr_list[cpu] != NULL;
364
 
365
#endif
366
};
367
#endif // CYGIMP_KERNEL_INTERRUPTS_DSRS
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// -------------------------------------------------------------------------
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#endif // ifndef CYGONCE_KERNEL_INTR_HXX
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// EOF intr.hxx

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