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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [kernel/] [v2_0/] [tests/] [intr0.cxx] - Blame information for rev 174

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//=================================================================
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//
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//        intr0.cxx
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//
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//        Interrupt test 0
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//
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//=================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):     dsm
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// Contributors:  dsm, jlarmour
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// Date:          1999-02-16
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// Description:   Very basic test of interrupt objects
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// Options:
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//     CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
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//     CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE
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//     CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
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//####DESCRIPTIONEND####
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#include <pkgconf/kernel.h>
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#include <cyg/kernel/intr.hxx>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/infra/testcase.h>
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#include "testaux.hxx"
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static cyg_ISR isr0, isr1;
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static cyg_DSR dsr0, dsr1;
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static char intr0_obj[sizeof(Cyg_Interrupt)];
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static char intr1_obj[sizeof(Cyg_Interrupt)];
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static cyg_uint32 isr0(cyg_vector vector, CYG_ADDRWORD data)
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{
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    CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
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    Cyg_Interrupt::acknowledge_interrupt(vector);
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    return 0;
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}
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static void dsr0(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data)
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{
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    CYG_UNUSED_PARAM(cyg_vector, vector);
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    CYG_UNUSED_PARAM(cyg_ucount32, count);
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    CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
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}
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static cyg_uint32 isr1(cyg_vector vector, CYG_ADDRWORD data)
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{
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    CYG_UNUSED_PARAM(cyg_vector, vector);
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    CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
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    return 0;
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}
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static void dsr1(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data)
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{
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    CYG_UNUSED_PARAM(cyg_vector, vector);
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    CYG_UNUSED_PARAM(cyg_ucount32, count);
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    CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
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}
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static bool flash( void )
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{
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    Cyg_Interrupt intr0 = Cyg_Interrupt(CYGNUM_HAL_ISR_MIN, 0, (CYG_ADDRWORD)333, isr0, dsr0 );
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    return true;
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}
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/* IMPORTANT: The calling convention for VSRs is target dependent.  It is
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 * unlikely that a plain C or C++ routine would function correctly on any
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 * particular platform, even if it could correctly access the system
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 * resources necessary to handle the event that caused it to be called.
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 * VSRs usually must be written in assembly language.
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 *
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 * This is just a test program.  The routine vsr0() below is defined simply
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 * to define an address that will be in executable memory.  If an event
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 * causes this VSR to be called, all bets are off.  If it is accidentally
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 * installed in the vector for the realtime clock, the system will likely
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 * freeze.
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 */
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static cyg_VSR vsr0;
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static void vsr0()
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{
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}
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void intr0_main( void )
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{
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    CYG_TEST_INIT();
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    CHECK(flash());
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    CHECK(flash());
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    // Make sure the chosen levels are not already in use.
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    int in_use;
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    cyg_vector lvl1 = CYGNUM_HAL_ISR_MIN + (1 % CYGNUM_HAL_ISR_COUNT);
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    HAL_INTERRUPT_IN_USE( lvl1, in_use );
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    Cyg_Interrupt* intr0 = NULL;
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    if (!in_use)
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        intr0 = new((void *)&intr0_obj[0]) Cyg_Interrupt( lvl1, 1, (CYG_ADDRWORD)777, isr0, dsr0 );
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    cyg_vector lvl2 = CYGNUM_HAL_ISR_MIN + ( 15 % CYGNUM_HAL_ISR_COUNT);
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    HAL_INTERRUPT_IN_USE( lvl2, in_use );
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    Cyg_Interrupt* intr1 = NULL;
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    if (!in_use && lvl1 != lvl2)
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        intr1 = new((void *)&intr1_obj[0]) Cyg_Interrupt( lvl2, 1, 888, isr1, dsr1 );
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    // Check these functions at least exist
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    Cyg_Interrupt::disable_interrupts();
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    Cyg_Interrupt::enable_interrupts();
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    if (intr0)
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        intr0->attach();
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    if (intr1)
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        intr1->attach();
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    if (intr0)
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        intr0->detach();
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    if (intr1)
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        intr1->detach();
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    // If this attaching interrupt replaces the previous interrupt
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    // instead of adding to it we could be in a big mess if the
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    // vector is being used by something important.
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    cyg_vector v = (CYGNUM_HAL_VSR_MIN + 11) % CYGNUM_HAL_VSR_COUNT;
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    cyg_VSR *old_vsr, *new_vsr;
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    Cyg_Interrupt::set_vsr( v, vsr0, &old_vsr );
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    Cyg_Interrupt::get_vsr( v, &new_vsr );
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    CHECK( vsr0 == new_vsr );
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    new_vsr = NULL;
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    Cyg_Interrupt::set_vsr( v, old_vsr, &new_vsr );
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    CHECK( new_vsr == vsr0 );
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    Cyg_Interrupt::set_vsr( v, new_vsr );
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    new_vsr = NULL;
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    Cyg_Interrupt::get_vsr( v, &new_vsr );
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    CHECK( vsr0 == new_vsr );
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    Cyg_Interrupt::set_vsr( v, old_vsr );
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    CHECK( vsr0 == new_vsr );
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    new_vsr = NULL;
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    Cyg_Interrupt::get_vsr( v, &new_vsr );
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    CHECK( old_vsr == new_vsr );
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    CHECK( NULL != vsr0 );
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    cyg_vector v1;
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#ifdef CYGPKG_HAL_MIPS_TX39    
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    // This can be removed when PR 17831 is fixed
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    if ( cyg_test_is_simulator )
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        v1 = 12 % CYGNUM_HAL_ISR_COUNT;
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    else /* NOTE TRAILING ELSE... */
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#endif
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    v1 = CYGNUM_HAL_ISR_MIN + (6 % CYGNUM_HAL_ISR_COUNT);
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    Cyg_Interrupt::mask_interrupt(v1);
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    Cyg_Interrupt::unmask_interrupt(v1);
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    Cyg_Interrupt::configure_interrupt(v1, true, true);
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    CYG_TEST_PASS_FINISH("Intr 0 OK");
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}
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externC void
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cyg_start( void )
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{
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#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
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    cyg_hal_invoke_constructors();
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#endif
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    intr0_main();
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}
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// EOF intr0.cxx

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