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//==========================================================================
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//
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// devs/eth/arm/ebsa285/..../include/devs_eth_ebsa285.inl
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//
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// EBSA-285 ethernet I/O definitions.
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov, hmt
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// Contributors: jskov, gthomas
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// Date: 2001-02-28
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// Purpose: EBSA285 ethernet defintions
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//####DESCRIPTIONEND####
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//==========================================================================
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#include // CYGNUM_HAL_INTERRUPT_...
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#include
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#include // hal_virt_to_phys_address()
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// --------------------------------------------------------------
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// Platform specifics:
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// support SDRAM with gaps in it.
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#define CYGHWR_DEVS_ETH_INTEL_I82559_PCIMEM_DISCONTIGUOUS
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// Interrupts are multiplex onto one interrupt pin.
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#define CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT \
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CYGNUM_HAL_INTERRUPT_PCI_IRQ
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// This brings on code to perform a selective reset on the device if the CU
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// wedges.
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#define CYGHWR_DEVS_ETH_INTEL_I82559_DEAD_TO (368640) // 0.1S of OS timer
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// The mask on an SA110 is really an enable: 1 => enabled, 0 => masked.
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// So to behave nestedly, we only need save the old value of the bits
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// of interest.
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#define CYGPRI_DEVS_ETH_INTEL_I82559_MASK_INTERRUPTS(p_i82559,old) \
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CYG_MACRO_START \
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int cpu_intr; \
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int mybits = \
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(1 << (p_i82559->vector)) | \
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(1 << CYGNUM_HAL_INTERRUPT_PCI_IRQ); \
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\
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HAL_DISABLE_INTERRUPTS( cpu_intr ); \
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old = *SA110_IRQCONT_IRQENABLE; \
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*SA110_IRQCONT_IRQENABLECLEAR = mybits; /* clear mybits */ \
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HAL_RESTORE_INTERRUPTS( cpu_intr ); \
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CYG_MACRO_END
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// We must only unmask (enable) those which were unmasked before,
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// according to the bits in old.
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#define CYGPRI_DEVS_ETH_INTEL_I82559_UNMASK_INTERRUPTS(p_i82559,old) \
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CYG_MACRO_START \
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*SA110_IRQCONT_IRQENABLESET = old & \
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((1 << (p_i82559->vector)) | \
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(1 << CYGNUM_HAL_INTERRUPT_PCI_IRQ)); \
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CYG_MACRO_END
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#define CYGPRI_DEVS_ETH_INTEL_I82559_ACK_INTERRUPTS(p_i82559) \
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CYG_MACRO_START \
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CYG_MACRO_END
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// --------------------------------------------------------------
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#define CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE
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#define CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE
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#define CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS( _x_ ) virt_to_bus((cyg_uint32)_x_)
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static inline cyg_uint32 virt_to_bus(cyg_uint32 p_memory)
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{ return (p_memory - CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE); }
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// --------------------------------------------------------------
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// Construct the two interfaces
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#ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH0
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static I82559 i82559_eth0_priv_data = {
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#ifdef CYGSEM_DEVS_ETH_ARM_EBSA285_ETH0_SET_ESA
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hardwired_esa: 1,
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mac_address: CYGDAT_DEVS_ETH_ARM_EBSA285_ETH0_ESA
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#else
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hardwired_esa: 0,
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#endif
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};
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ETH_DRV_SC(i82559_sc0,
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&i82559_eth0_priv_data, // Driver specific data
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CYGDAT_DEVS_ETH_ARM_EBSA285_ETH0_NAME, // Name for device
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i82559_start,
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i82559_stop,
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i82559_ioctl,
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i82559_can_send,
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i82559_send,
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i82559_recv,
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i82559_deliver,
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i82559_poll,
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i82559_int_vector
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);
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NETDEVTAB_ENTRY(i82559_netdev0,
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"i82559_" CYGDAT_DEVS_ETH_ARM_EBSA285_ETH0_NAME,
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i82559_init,
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&i82559_sc0);
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#endif // CYGPKG_DEVS_ETH_ARM_EBSA285_ETH0
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#ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH1
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static I82559 i82559_eth1_priv_data = {
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#ifdef CYGSEM_DEVS_ETH_ARM_EBSA285_ETH1_SET_ESA
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hardwired_esa: 1,
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mac_address: CYGDAT_DEVS_ETH_ARM_EBSA285_ETH1_ESA
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#else
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hardwired_esa: 0,
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#endif
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};
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ETH_DRV_SC(i82559_sc1,
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&i82559_eth1_priv_data, // Driver specific data
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CYGDAT_DEVS_ETH_ARM_EBSA285_ETH1_NAME, // Name for device
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i82559_start,
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i82559_stop,
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i82559_ioctl,
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i82559_can_send,
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i82559_send,
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i82559_recv,
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i82559_deliver,
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i82559_poll,
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i82559_int_vector
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);
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NETDEVTAB_ENTRY(i82559_netdev1,
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"i82559_" CYGDAT_DEVS_ETH_ARM_EBSA285_ETH1_NAME,
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i82559_init,
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&i82559_sc1);
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#endif // CYGPKG_DEVS_ETH_ARM_EBSA285_ETH1
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// --------------------------------------------------------------
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// These arrays are used for sanity checking of pointers
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I82559 *
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i82559_priv_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
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#ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH0
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&i82559_eth0_priv_data,
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#endif
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#ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH1
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&i82559_eth1_priv_data,
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#endif
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};
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#ifdef CYGDBG_USE_ASSERTS
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// These are only used when assertions are enabled
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cyg_netdevtab_entry_t *
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i82559_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
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#ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH0
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&i82559_netdev0,
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#endif
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#ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH1
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&i82559_netdev1,
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#endif
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};
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struct eth_drv_sc *
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i82559_sc_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
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#ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH0
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&i82559_sc0,
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#endif
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#ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH1
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&i82559_sc1,
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#endif
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};
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#endif // CYGDBG_USE_ASSERTS
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// --------------------------------------------------------------
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// Debugging
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//#define CYGDBG_DEVS_ETH_INTEL_I82559_CHATTER 1
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// --------------------------------------------------------------
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// RedBoot configuration options for managing ESAs for us
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#define CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM 0
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#define CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM_MAC_ADJUST (1)
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// --------------------------------------------------------------
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// EOF devs_eth_ebsa285.inl
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