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//==========================================================================

//

//      if_lpc2xxx.c

//

//==========================================================================

// ####ECOSGPLCOPYRIGHTBEGIN####                                            

// -------------------------------------------                              

// This file is part of eCos, the Embedded Configurable Operating System.   

// Copyright (C) 2008 Free Software Foundation, Inc.                        

//

// eCos is free software; you can redistribute it and/or modify it under    

// the terms of the GNU General Public License as published by the Free     

// Software Foundation; either version 2 or (at your option) any later      

// version.                                                                 

//

// eCos is distributed in the hope that it will be useful, but WITHOUT      

// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    

// for more details.                                                        

//

// You should have received a copy of the GNU General Public License        

// along with eCos; if not, write to the Free Software Foundation, Inc.,    

// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            

//

// As a special exception, if other files instantiate templates or use      

// macros or inline functions from this file, or you compile this file      

// and link it with other works to produce a work based on this file,       

// this file does not by itself cause the resulting work to be covered by   

// the GNU General Public License. However the source code for this file    

// must still be made available in accordance with section (3) of the GNU   

// General Public License v2.                                               

//

// This exception does not invalidate any other reasons why a work based    

// on this file might be covered by the GNU General Public License.         

// -------------------------------------------                              

// ####ECOSGPLCOPYRIGHTEND####                                              

//==========================================================================

//#####DESCRIPTIONBEGIN####

//

// Author(s):    Uwe Kindler

// Contributors: ilijak

// Date:         2008-08-10

// Description:  Hardware driver for LPC2xxx on-chip EMAC peripheral

//

//               This driver was originally written for LPC2468 and may

//               require some modifications to work on other LPC2xxx

//               variants as well.

//

//####DESCRIPTIONEND####

//

//========================================================================*/

#include <pkgconf/system.h>

#include <pkgconf/hal.h>

#include <pkgconf/devs_eth_arm_lpc2xxx.h>

#include <pkgconf/io_eth_drivers.h>

#if defined(CYGPKG_REDBOOT)

   #include <pkgconf/redboot.h>

#endif

#include <cyg/hal/hal_io.h>

#include <cyg/hal/hal_intr.h>

#include <cyg/hal/hal_arch.h>

#include <cyg/hal/drv_api.h>

#include <cyg/hal/hal_diag.h>

#include <cyg/infra/cyg_type.h>

#include <cyg/infra/cyg_ass.h>

#include <cyg/infra/diag.h>

#include <cyg/io/eth/netdev.h>

#include <cyg/io/eth/eth_drv.h>

#include <cyg/io/eth/eth_drv_stats.h>

#include <cyg/io/eth_phy.h>

#include <errno.h>

#include <string.h>

#ifdef CYGPKG_NET

#include <pkgconf/net.h>

#include <net/if.h>  /* Needed for struct ifnet */

#endif

#include <cyg/io/eth/eth_drv_stats.h>

//===========================================================================

//                                DEFINES

//===========================================================================

#ifndef CYGARC_HAL_LPC2XXX_REG_EMAC_BASE

#error "CYGARC_HAL_LPC2XXX_REG_EMAC_BASE not defined by varaint/platform."

#else

#define EMAC_BASE CYGARC_HAL_LPC2XXX_REG_EMAC_BASE

#endif

//

// MAC registers

//

#define EMAC_MAC1   (EMAC_BASE + 0x0000)

#define EMAC_MAC2   (EMAC_BASE + 0x0004)

#define EMAC_IPGT   (EMAC_BASE + 0x0008)

#define EMAC_IPGR   (EMAC_BASE + 0x000C)

#define EMAC_CLRT   (EMAC_BASE + 0x0010)

#define EMAC_MAXF   (EMAC_BASE + 0x0014)

#define EMAC_SUPP   (EMAC_BASE + 0x0018)

#define EMAC_TEST   (EMAC_BASE + 0x001C)

#define EMAC_MCFG   (EMAC_BASE + 0x0020)

#define EMAC_MCMD   (EMAC_BASE + 0x0024)

#define EMAC_MADR   (EMAC_BASE + 0x0028)

#define EMAC_MWTD   (EMAC_BASE + 0x002C)

#define EMAC_MRDD   (EMAC_BASE + 0x0030)

#define EMAC_MIND   (EMAC_BASE + 0x0034)

#define EMAC_SA0    (EMAC_BASE + 0x0040)

#define EMAC_SA1    (EMAC_BASE + 0x0044)

#define EMAC_SA2    (EMAC_BASE + 0x0048)

//

// Control registers

//

#define EMAC_CMD            (EMAC_BASE + 0x0100)

#define EMAC_STAT           (EMAC_BASE + 0x0104)

#define EMAC_RXDESC         (EMAC_BASE + 0x0108)

#define EMAC_RXSTAT         (EMAC_BASE + 0x010C)

#define EMAC_RXDESC_NUM     (EMAC_BASE + 0x0110)

#define EMAC_RX_PROD_IDX    (EMAC_BASE + 0x0114)

#define EMAC_RX_CONSUME_IDX (EMAC_BASE + 0x0118)

#define EMAC_TXDESC         (EMAC_BASE + 0x011C)

#define EMAC_TXSTAT         (EMAC_BASE + 0x0120)

#define EMAC_TXDESC_NUM     (EMAC_BASE + 0x0124)

#define EMAC_TX_PROD_IDX    (EMAC_BASE + 0x0128)

#define EMAC_TX_CONSUME_IDX (EMAC_BASE + 0x012C)

#define EMAC_TSV0           (EMAC_BASE + 0x0158)

#define EMAC_TSV1           (EMAC_BASE + 0x015C)

#define EMAC_RSV            (EMAC_BASE + 0x0160)

#define EMAC_FLOWCTRL_CNT   (EMAC_BASE + 0x0170)

#define EMAC_FLOWCTRL_STAT  (EMAC_BASE + 0x0174)

//

// Rx filter registers

//

#define EMAC_RXFILT_CTRL      (EMAC_BASE + 0x0200)

#define EMAC_RXFILT_WOL_STAT  (EMAC_BASE + 0x0204)

#define EMAC_RXFILT_WOL_CLR   (EMAC_BASE + 0x0204)

#define EMAC_HASH_FILT_L      (EMAC_BASE + 0x0210)

#define EMAC_HASH_FILT_H      (EMAC_BASE + 0x0214)

//

// Module control registers

//

#define EMAC_INT_STATUS       (EMAC_BASE + 0x0FE0)

#define EMAC_INT_EN           (EMAC_BASE + 0x0FE4)

#define EMAC_INT_CLR          (EMAC_BASE + 0x0FE8)

#define EMAC_INT_SET          (EMAC_BASE + 0x0FEC)

#define EMAC_POWER_DOWN       (EMAC_BASE + 0x0FF4)

#define EMAC_MODULE_ID        (EMAC_BASE + 0x0FFC)

//

// Register bits MCMD

//

#define  MCMD_WRITE           0x00

#define  MCMD_READ            0x01

//

// Register bits COMMAND register

//

#define CMD_RX_ENABLE        (1 << 0)

#define CMD_TX_ENABLE        (1 << 1)

#define CMD_REG_RESET        (1 << 3)

#define CMD_TX_RESET         (1 << 4)

#define CMD_RX_RESET         (1 << 5)

#define CMD_PASS_RUNT_FRAME  (1 << 6)

#define CMD_PASS_RX_FILTER   (1 << 7)

#define CMD_TX_FLOW_CONTROL  (1 << 8)

#define CMD_RMII             (1 << 9)

#define CMD_FULL_DUPLEX      (1 << 10)

//

// Register bits SUPP register

//

#define SUPP_SPEED_100MB     (1 << 8)

#define  EMAC_OLD_MODULE_ID  ((0x3902 << 16) | 0x2000)

//

// Register bits MAC1

//

#define MAC1_RX_EN                (1 << 0)

#define MAC1_PASS_ALL_RX_FRAMES   (1 << 1)

#define MAC1_RX_FLOW_CTRL         (1 << 2)

#define MAC1_TX_FLOW_CTRL         (1 << 3)

#define MAC1_LOOPBACK             (1 << 4)

#define MAC1_RESET_TX             (1 << 8)

#define MAC1_RESET_MCS_TX         (1 << 9)

#define MAC1_RESET_RX             (1 << 10)

#define MAC1_RESET_MCS_RX         (1 << 11)

#define MAC1_RESET_SIM            (1 << 14)

#define MAC1_SOFT_RESET           (1 << 15)

//

// Register bits MAC2

//

#define MAC2_FDX                  (1 << 0)

#define MAC2_FRAME_LEN_CHECK      (1 << 1)

#define MAC2_HUGE_FRAME_EN        (1 << 2)

#define MAC2_DELAYED_CRC          (1 << 3)

#define MAC2_CRC_EN               (1 << 4)

#define MAC2_PAD_CRC_EN           (1 << 5)

#define MAC2_VLAN_PAD_EN          (1 << 6)

#define MAC2_AUTO_DETECT_PAD_EN   (1 << 7)

#define MAC2_PURE_PREAMBLE        (1 << 8)

#define MAC2_LONG_PREAMBLE        (1 << 9)

#define MAC2_NO_BACKOFF           (1 << 12)

#define MAC2_BACK_PRESS           (1 << 13)

#define MAC2_EXCESS_DEFER         (1 << 14)

//

// Register bits RXFILT_CTRL

//

#define RXFILT_CTRL_ACC_UNICAST            (1 << 0)

#define RXFILT_CTRL_ACC_BROADCAST          (1 << 1)

#define RXFILT_CTRL_ACC_MULTICAST          (1 << 2)

#define RXFILT_CTRL_ACC_UNICAST_HASH       (1 << 3)

#define RXFILT_CTRL_ACC_MULTICAST_HASH     (1 << 4)

#define RXFILT_CTRL_ACC_PERFECT            (1 << 5)

#define RXFILT_CTRL_MAGIG_PKT_WOL          (1 << 12)

#define RXFILT_CTRL_RXFILT_WOL             (1 << 13)

//

// Register bits MCFG

//

#define MCFG_SCAN_INCR      (1 << 0)

#define MCFG_SUPP_PREAMBLE  (1 << 1)

#define MCFG_RESET_MII_MGMT (1 << 15)

//

// Register bits MIND

//

#define MIND_BUSY      (1 << 0)

#define MIND_SCANNING  (1 << 1)

#define MIND_NOT_VALID (1 << 2)

#define MIND_LINK_FAIL (1 << 3)

//

// EMAC interrupts

//

#define EMAC_INT_RXOVERRUN  (1 << 0)

#define EMAC_INT_RXERROR    (1 << 1)

#define EMAC_INT_RXFINISHED (1 << 2)

#define EMAC_INT_RXDONE     (1 << 3)

#define EMAC_INT_TXUNDERRUN (1 << 4)

#define EMAC_INT_TXERROR    (1 << 5)

#define EMAC_INT_TXFINISHED (1 << 6)

#define EMAC_INT_TXDONE     (1 << 7)

#define EMAC_INT_SOFTINT    (1 << 12)

#define EMAC_INT_WOL        (1 << 13)

//===========================================================================

//                ETHERNET RAM AND DMA CONFIGURATION

//===========================================================================

#ifdef CYGHWR_HAL_LPC_EMAC_RAM_AHB

# include <cyg/infra/cyg_type.h>

# define EMAC_RAM_MEM_SECTION   CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_LPC_EMAC_MEM_SECTION)

# define EMAC_RAM_BASE          (&emac_ahb_ram)

# define EMAC_RAM_SIZE          sizeof(emac_ahb_ram)

# define EMAC_BLOCK_SIZE        CYGHWR_HAL_LPC_EMAC_BLOCK_SIZE

#else // Backward compatibility

# define EMAC_RAM_BASE          0x7FE00000

# define EMAC_RAM_SIZE          0x00004000

# define EMAC_BLOCK_SIZE        0x600

#endif // CYGHWR_HAL_LPC_EMAC_RAM_AHB

//

// EMAC Descriptor TX and RX Control fields

//

#define EMAC_TX_DESC_INT        0x80000000

#define EMAC_TX_DESC_LAST       0x40000000

#define EMAC_TX_DESC_CRC        0x20000000

#define EMAC_TX_DESC_PAD        0x10000000

#define EMAC_TX_DESC_HUGE       0x08000000

#define EMAC_TX_DESC_OVERRIDE   0x04000000

#define EMAC_RX_DESC_INT        0x80000000

//

// EMAC Descriptor status related definition

//

#define TX_DESC_STATUS_ERR      0x80000000

#define TX_DESC_STATUS_NODESC   0x40000000

#define TX_DESC_STATUS_UNDERRUN 0x20000000

#define TX_DESC_STATUS_LCOL     0x10000000

#define TX_DESC_STATUS_ECOL     0x08000000

#define TX_DESC_STATUS_EDEFER   0x04000000

#define TX_DESC_STATUS_DEFER    0x02000000

#define TX_DESC_STATUS_COLCNT   0x01E00000

#define RX_DESC_STATUS_ERR      0x80000000

#define RX_DESC_STATUS_LAST     0x40000000

#define RX_DESC_STATUS_NODESC   0x20000000

#define RX_DESC_STATUS_OVERRUN  0x10000000

#define RX_DESC_STATUS_ALGNERR  0x08000000

#define RX_DESC_STATUS_RNGERR   0x04000000

#define RX_DESC_STATUS_LENERR   0x02000000

#define RX_DESC_STATUS_SYMERR   0x01000000

#define RX_DESC_STATUS_CRCERR   0x00800000

#define RX_DESC_STATUS_BCAST    0x00400000

#define RX_DESC_STATUS_MCAST    0x00200000

#define RX_DESC_STATUS_FAILFLT  0x00100000

#define RX_DESC_STATUS_VLAN     0x00080000

#define RX_DESC_STATUS_CTLFRAM  0x00040000

#define DESC_SIZE_MASK          0x000007FF

//

// This type defines a descriptor

//

typedef struct descriptor_st

{

    cyg_uint32 packet;

    cyg_uint32 control;

} descriptor_t;

//

// This type defines a rx status

// (double word aligned)

//

typedef struct rx_status_st

{

    cyg_uint32 info;

    cyg_uint32 hash_crc;

} rx_status_t;

//

// This type defines a tx status

//

typedef cyg_uint32 tx_status_t;

typedef union eth_buf_st

{

    cyg_uint32 dwords[EMAC_BLOCK_SIZE / sizeof(cyg_uint32)];

    cyg_uint8  bytes[EMAC_BLOCK_SIZE];

} eth_buf_t;

//

// Ethernet RAM and buffer configuration type

// The descriptors and statuses require a certain alignment. By defining each

// data type we assure this alignment.

// The TX descriptor array, the TX status array and the RX descriptor array

// need to be aligned on a 4 Byte (32 bit) address boundary. The RX status

// array need to be aligned on a 8 Byte (64 bit) address boundary.

//

typedef struct eth_ram_cfg_st

{

    volatile rx_status_t  rx_status[CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS];

    volatile descriptor_t rx_descr[CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS];

    volatile tx_status_t  tx_status[CYGNUM_DEVS_ETH_ARM_LPC2XXX_TX_BUFS];

    volatile descriptor_t tx_descr[CYGNUM_DEVS_ETH_ARM_LPC2XXX_TX_BUFS];

    volatile eth_buf_t    rx_buf[CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS];

} eth_ram_cfg_t;

#ifdef CYGHWR_HAL_LPC_EMAC_RAM_AHB

volatile static eth_ram_cfg_t emac_ahb_ram EMAC_RAM_MEM_SECTION;

#endif

#if CYGPKG_DEVS_ETH_ARM_LPC2XXX_DEBUG_LEVEL < 3

#if CYGPKG_DEVS_ETH_ARM_LPC2XXX_DEBUG_LEVEL > 0

   #define debug1_printf(args...) diag_printf(args)

#else

   #define debug1_printf(args...)

#endif

#if CYGPKG_DEVS_ETH_ARM_LPC2XXX_DEBUG_LEVEL > 1

   #define debug2_printf(args...) diag_printf(args)

#else

   #define debug2_printf(args...)

#endif

#else // CYGPKG_DEVS_ETH_ARM_LPC2XXX_DEBUG_LEVEL > 3

//

// Debug level 3 is a special kind of debug level. It prints the same debug

// messages like level 2 but it forces the debug output to the second serial

// port. This may be necessary for debugging the ethernet driver if the

// stand-alone network stack from redboot is used. It is possible to

// print debug messages while an application is loaded and run via GDB

// TCP/IP connection

//

static int cur;

#define debug1_printf(args...)                                               \

{                                                                            \

   cur =                                                                     \

   CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);\

   CYGACC_CALL_IF_SET_CONSOLE_COMM(1);                                       \

   diag_printf(args);                                                        \

   CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);                                     \

}

#define debug2_printf(args...)                                               \

{                                                                            \

   cur =                                                                     \

   CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);\

   CYGACC_CALL_IF_SET_CONSOLE_COMM(1);                                       \

   diag_printf(args);                                                        \

   CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);                                     \

}

#endif // CYGPKG_DEVS_ETH_ARM_LPC2XXX_DEBUG_LEVEL > 3

//Driver interface callbacks

#define _eth_drv_init(sc,mac)           \

  (sc->funs->eth_drv->init)(sc,(unsigned char *)mac)

#define _eth_drv_tx_done(sc,key,status)     \

  (sc->funs->eth_drv->tx_done)(sc,key,status)

#define _eth_drv_recv(sc,len)           \

  (sc->funs->eth_drv->recv)(sc,len)

#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED

static cyg_uint32

lpc2xxx_eth_isr (cyg_vector_t vector, cyg_addrword_t data);

#endif

// --------------------------------------------------------------

// RedBoot configuration options for managing ESAs for us

// Decide whether to have redboot config vars for it...

#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYGPKG_REDBOOT_NETWORKING)

#include <redboot.h>

#include <flash_config.h>

#ifdef CYGSEM_DEVS_ETH_ARM_LPC2XXX_REDBOOT_HOLDS_ESA_ETH0

RedBoot_config_option("Network hardware address [MAC] for eth0",

                      eth0_esa_data,

                      ALWAYS_ENABLED, true,

                      CONFIG_ESA, 0);

#endif // CYGSEM_DEVS_ETH_ARM_LPC2XXX_REDBOOT_HOLDS_ESA_ETH0

#endif  // CYGPKG_REDBOOT_NETWORKING && CYGSEM_REDBOOT_FLASH_CONFIG

// and initialization code to read them

// - independent of whether we are building RedBoot right now:

#ifdef CYGPKG_DEVS_ETH_ARM_LPC2XXX_REDBOOT_HOLDS_ESA

#include <cyg/hal/hal_if.h>

#ifndef CONFIG_ESA

    #define CONFIG_ESA (6)

#endif

#define CYGHWR_DEVS_ETH_ARM_LPC2XXX_GET_ESA( mac_address, ok )        \

  CYG_MACRO_START                                                     \

  ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,     \

                                    "eth0_esa_data",                  \

                                    mac_address,                      \

                                    CONFIG_ESA);                      \

  CYG_MACRO_END

#endif // CYGPKG_DEVS_ETH_ARM_LPC2XXX_REDBOOT_HOLDS_ESA

//

// LPC2xxx Ethernet private data

// The LPC2468 has a single on-chip ethernet device, so all device-specific

// data could be held in statics. However, in case this driver ever gets

// re-used for a chip with multiple ethernet devices that data is held

// in a driver-specific structure.

//

typedef struct lpc2xxx_eth_priv_s

{

   cyg_uint32              intr_vector;

   cyg_uint8              *enaddr;

   cyg_uint32              base;      // Base address of device

   eth_phy_access_t       *phy;

   cyg_uint32              cur_tx_key;

   cyg_uint32              total_len;

   cyg_uint8               iterator;

   cyg_bool                tx_busy;

   volatile eth_ram_cfg_t *ram;

#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED

   cyg_interrupt intr;

   cyg_handle_t  intr_handle;

#endif

} lpc2xxx_eth_priv_t;

//===========================================================================

//                           PHY SPECIFIC STUFF

//===========================================================================

//===========================================================================

// Write one of the PHY registers via the MII bus

//===========================================================================

static void

lpc2xxx_write_phy(int reg_addr, int phy_addr, unsigned short data)

{

    cyg_uint32 regval;

    HAL_WRITE_UINT32(EMAC_MCMD, MCMD_WRITE);

    regval = (phy_addr << 8) | reg_addr;

    HAL_WRITE_UINT32(EMAC_MADR, regval);

    HAL_WRITE_UINT32(EMAC_MWTD, data);

    do

    {

        HAL_READ_UINT32(EMAC_MIND, regval);

    }

    while (regval != 0);

}

//===========================================================================

// Read one of the PHY registers via the MII bus

//===========================================================================

static bool

lpc2xxx_read_phy(int reg_addr, int phy_addr, unsigned short *data)

{

    cyg_uint32 regval;

    HAL_WRITE_UINT32(EMAC_MCMD, 0);

    regval = (phy_addr << 8) | reg_addr;

    HAL_WRITE_UINT32(EMAC_MADR, regval);

    HAL_WRITE_UINT32(EMAC_MCMD, MCMD_READ);

    do

    {

        HAL_READ_UINT32(EMAC_MIND, regval);

    }

    while ((regval & ~MIND_LINK_FAIL) != 0);

    if (regval & MIND_LINK_FAIL)

    {

        debug1_printf("LPC2XXX_ETH: PHY link fail\n");

    }

    HAL_WRITE_UINT32(EMAC_MCMD, 0x0000);

    HAL_READ_UINT32(EMAC_MRDD, regval);

    debug2_printf("LPC2XXX_ETH: read result %08x\n", regval);

    *data = regval & 0xFFFF;

    return true;

}

//===========================================================================

// Init device for phy access

//===========================================================================

static void lpc2xxx_init_phy(void)

{

    int        i;

    cyg_uint32 regval;

    //

    // host clock divided by 20, no suppress preamble, no scan increment

    // Reset management hardware

    //

    HAL_WRITE_UINT32(EMAC_MCFG, 0x0018 | MCFG_RESET_MII_MGMT);

    for (i = 0; i < 0x40; ++i)

    {

        asm volatile ("  nop");

    }

    HAL_WRITE_UINT32(EMAC_MCFG, 0x0018);

    HAL_WRITE_UINT32(EMAC_MCMD, MCMD_WRITE);

    HAL_READ_UINT32(EMAC_CMD, regval);

    HAL_WRITE_UINT32(EMAC_CMD, regval | CMD_RMII); // RMII configuration

    HAL_WRITE_UINT32(EMAC_SUPP, 0x800 | SUPP_SPEED_100MB);

    HAL_DELAY_US(50);

    HAL_WRITE_UINT32(EMAC_SUPP, SUPP_SPEED_100MB);

    HAL_DELAY_US(1000);

}

//===========================================================================

// PHY specific data structures

//===========================================================================

ETH_PHY_REG_LEVEL_ACCESS_FUNS(lpc2xxx_phy,

                              lpc2xxx_init_phy,

                              NULL,

                              lpc2xxx_write_phy,

                              lpc2xxx_read_phy);

//===========================================================================

// Hardware driver specific data

//===========================================================================                              

lpc2xxx_eth_priv_t lpc2xxx_priv_data =

{

   .intr_vector = CYGNUM_HAL_INTERRUPT_ETH,

   .base        = EMAC_BASE,

   .phy         = &lpc2xxx_phy,

   .ram         =  (volatile eth_ram_cfg_t*)EMAC_RAM_BASE,

   .total_len   = 0,

   .iterator    = 0,

   .tx_busy     = false

};

//===========================================================================

// Initialize TX descriptors

// To avoid copy operations the higher-level sg_list entries will be 

// directly put into the device's TX descriptors (ring buffer).

//===========================================================================

static void lpc2xxx_eth_txdesc_init(lpc2xxx_eth_priv_t * priv)

{

    int i;

    debug1_printf("\nLPC2XXX_ETH: Initialising TX descriptors\n");

    debug2_printf("&priv->ram->tx_descr[0]:  0x%08X\n",

                  (cyg_uint32)priv->ram->tx_descr);

    debug2_printf("&priv->ram->tx_status[0]: 0x%08X\n",

                  (cyg_uint32)priv->ram->tx_descr);

    debug2_printf("No of TX descr: %d\n",

                  CYGNUM_DEVS_ETH_ARM_LPC2XXX_TX_BUFS);

    //

    // Init status for all TX descriptors

    //

    for (i = 0; i < CYGNUM_DEVS_ETH_ARM_LPC2XXX_TX_BUFS; i++)

    {

        priv->ram->tx_status[i] = 0;

    }

    //

    // Initialise TX pointers

    //

    HAL_WRITE_UINT32(EMAC_TXDESC, (cyg_uint32)priv->ram->tx_descr);

    HAL_WRITE_UINT32(EMAC_TXSTAT, (cyg_uint32)priv->ram->tx_status);

    HAL_WRITE_UINT32(EMAC_TXDESC_NUM, CYGNUM_DEVS_ETH_ARM_LPC2XXX_TX_BUFS - 1);

    HAL_WRITE_UINT32(EMAC_TX_PROD_IDX, 0);

}

//===========================================================================

// Initialize RX descriptors

// The driver currently supports up to 4 rx buffers. In the current 

// implementation the size of the RX buffers is fixed to 1536 (0x600) bytes.

// Incoming frames are then copied to higher-level's code sg lists.

//===========================================================================

static void lpc2xxx_eth_rxdesc_init(lpc2xxx_eth_priv_t * priv)

{

    int i;

    debug1_printf("\nLPC2XXX_ETH: Initialising RX descriptors\n");

    debug2_printf("&priv->ram->rx_descr[0]:  0x%08X\n",

                  (cyg_uint32)priv->ram->rx_descr);

    debug2_printf("&priv->ram->rx_status[0]: 0x%08X\n",

                  (cyg_uint32)priv->ram->rx_status);

    debug2_printf("No of TX descr: %d\n", CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS);

    //

    // Initialise RX descriptors - store pointers to receive buffers and

    // RX status, two words, status info. and status hash CRC.

    //

    for (i = 0; i < CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS; ++i)

    {

        priv->ram->rx_descr[i].packet  = (cyg_uint32)priv->ram->rx_buf[i].bytes;

        debug2_printf("priv->ram->rx_descr[%d].packet (0x%08X) "

                      "= &priv->ram->rx_buf[%d].bytes[0] (0x%08X)\n",

                      i, (cyg_uint32)&priv->ram->rx_descr[i].packet,

                      i, (cyg_uint32)priv->ram->rx_buf[i].bytes);

        priv->ram->rx_descr[i].control = (EMAC_RX_DESC_INT

                                       | ((EMAC_BLOCK_SIZE - 1)

                                          & DESC_SIZE_MASK));

        debug2_printf("priv->ram->rx_descr[%d].control (0x%08X) = 0x%08X\n",

                      i, (cyg_uint32)&priv->ram->rx_descr[i].control,

                      priv->ram->rx_descr[i].control);

        priv->ram->rx_status[i].info     = 0;

        priv->ram->rx_status[i].hash_crc = 0;

    }

    //

    // Initialise RX pointers

    //

    HAL_WRITE_UINT32(EMAC_RXDESC, (cyg_uint32)priv->ram->rx_descr);

    HAL_WRITE_UINT32(EMAC_RXSTAT, (cyg_uint32)priv->ram->rx_status);

    HAL_WRITE_UINT32(EMAC_RXDESC_NUM, CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS - 1);

    HAL_WRITE_UINT32(EMAC_RX_CONSUME_IDX, 0);

}

//===========================================================================

// Set a specific address match to a given address. Packets received which

// match this address will be passed on.

//===========================================================================

static void lpc2xxx_set_mac(lpc2xxx_eth_priv_t * priv, cyg_uint8 * enaddr)

{

    HAL_WRITE_UINT32(EMAC_SA0, (enaddr[5] << 8 | enaddr[4]));

    HAL_WRITE_UINT32(EMAC_SA1, (enaddr[3] << 8 | enaddr[2]));

    HAL_WRITE_UINT32(EMAC_SA2, (enaddr[1] << 8 | enaddr[0]));

}

//===========================================================================

// This function is called to stop the interface.

//===========================================================================

static void lpc2xxx_eth_stop(struct eth_drv_sc *sc)

{

    cyg_uint32          regval;

    // Disable the receiver and transmitter

    HAL_READ_UINT32(EMAC_MAC1, regval);

    HAL_WRITE_UINT32(EMAC_MAC1, regval & ~MAC1_RX_EN);

    HAL_READ_UINT32(EMAC_CMD, regval);

    HAL_WRITE_UINT32(EMAC_CMD, regval & ~(CMD_RX_ENABLE | CMD_TX_ENABLE));

}

//===========================================================================

// This function is called to "start up" the interface. It may be called

// multiple times, even when the hardware is already running.

//===========================================================================

static void

lpc2xxx_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)

{

    cyg_uint32  regval;

    //

    // To prevent overflow in the receive DMA engine the receive DMA engine 

    // should be enabled by setting the RxEnable bit in the Command register 

    // before enabling the receive datapath in the MAC by setting the 

    // RECEIVE ENABLE bit in the MAC1 register

    //

    HAL_READ_UINT32(EMAC_CMD, regval);

    HAL_WRITE_UINT32(EMAC_CMD, regval | CMD_RX_ENABLE | CMD_TX_ENABLE);

    HAL_READ_UINT32(EMAC_MAC1, regval);

    HAL_WRITE_UINT32(EMAC_MAC1, regval | MAC1_RX_EN);

}

//===========================================================================

// Enable and Disable of the receiver and transmitter.

// Initialize the interface. This configures the interface ready for use.

// Interrupts are grabbed etc. This means the start function has

// little to do except enable the receiver

//===========================================================================

static bool lpc2xxx_eth_init(struct cyg_netdevtab_entry *tab)

{

    struct eth_drv_sc *sc    = (struct eth_drv_sc *)tab->device_instance;

    lpc2xxx_eth_priv_t *priv = (lpc2xxx_eth_priv_t *)sc->driver_private;

    bool esa_ok = false;

    unsigned char enaddr[6] = { CYGPKG_DEVS_ETH_ARM_LPC2XXX_MACADDR};

    unsigned short phy_state = 0;

    cyg_uint32 regval;

    debug1_printf("\nLPC2XXX_ETH: Initialising 0x%08X\n",priv->base);

    //

    // turn on the ethernet MAC clock in PCONP, bit 30 and then do

    // a short delay

    //

    HAL_READ_UINT32(CYGARC_HAL_LPC24XX_REG_SCB_BASE +

                    CYGARC_HAL_LPC24XX_REG_PCONP, regval);

    HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_SCB_BASE +

                     CYGARC_HAL_LPC24XX_REG_PCONP,

                     regval | CYGARC_HAL_LPC24XX_REG_PCONP_ENET);

    HAL_DELAY_US(50);

    //

    // Because of a device errate in Rev '-' devices we need to check the

    // module ID to setup the RMII mode properly

    //

    HAL_READ_UINT32(EMAC_MODULE_ID, regval);

    if (EMAC_OLD_MODULE_ID == regval)

    {

        //

        // On Rev. '-', EMAC_MODULE_ID should be equal to

        // EMAC_OLD_MODULE_ID, P1.6 should be set -