| 1 |
786 |
skrzyp |
//==========================================================================
|
| 2 |
|
|
//
|
| 3 |
|
|
// devs/eth/arm/npwr/include/devs_eth_arm_npwr.inl
|
| 4 |
|
|
//
|
| 5 |
|
|
// NPWR ethernet I/O definitions.
|
| 6 |
|
|
//
|
| 7 |
|
|
//==========================================================================
|
| 8 |
|
|
// ####ECOSGPLCOPYRIGHTBEGIN####
|
| 9 |
|
|
// -------------------------------------------
|
| 10 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 11 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
| 12 |
|
|
//
|
| 13 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 14 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 15 |
|
|
// Software Foundation; either version 2 or (at your option) any later
|
| 16 |
|
|
// version.
|
| 17 |
|
|
//
|
| 18 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT
|
| 19 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 20 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 21 |
|
|
// for more details.
|
| 22 |
|
|
//
|
| 23 |
|
|
// You should have received a copy of the GNU General Public License
|
| 24 |
|
|
// along with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 25 |
|
|
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
| 26 |
|
|
//
|
| 27 |
|
|
// As a special exception, if other files instantiate templates or use
|
| 28 |
|
|
// macros or inline functions from this file, or you compile this file
|
| 29 |
|
|
// and link it with other works to produce a work based on this file,
|
| 30 |
|
|
// this file does not by itself cause the resulting work to be covered by
|
| 31 |
|
|
// the GNU General Public License. However the source code for this file
|
| 32 |
|
|
// must still be made available in accordance with section (3) of the GNU
|
| 33 |
|
|
// General Public License v2.
|
| 34 |
|
|
//
|
| 35 |
|
|
// This exception does not invalidate any other reasons why a work based
|
| 36 |
|
|
// on this file might be covered by the GNU General Public License.
|
| 37 |
|
|
// -------------------------------------------
|
| 38 |
|
|
// ####ECOSGPLCOPYRIGHTEND####
|
| 39 |
|
|
//==========================================================================
|
| 40 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 41 |
|
|
//
|
| 42 |
|
|
// Author(s): msalter
|
| 43 |
|
|
// Contributors:msalter, gthomas
|
| 44 |
|
|
// Date: 2002-01-10
|
| 45 |
|
|
// Purpose: NPWR ethernet defintions
|
| 46 |
|
|
//####DESCRIPTIONEND####
|
| 47 |
|
|
//==========================================================================
|
| 48 |
|
|
|
| 49 |
|
|
#include // CYGNUM_HAL_INTERRUPT_ETHERNET
|
| 50 |
|
|
#include // HAL_DCACHE_LINE_SIZE
|
| 51 |
|
|
#include // CYGARC_UNCACHED_ADDRESS
|
| 52 |
|
|
|
| 53 |
|
|
#ifdef CYGPKG_DEVS_ETH_ARM_NPWR_I82544_ETH0
|
| 54 |
|
|
|
| 55 |
|
|
// Use auto speed detection
|
| 56 |
|
|
#define CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
|
| 57 |
|
|
|
| 58 |
|
|
#define CYGHWR_INTEL_I82544_PCI_VIRT_TO_BUS( _x_ ) ((cyg_uint32)CYGARC_VIRT_TO_BUS(_x_))
|
| 59 |
|
|
#define CYGHWR_INTEL_I82544_PCI_BUS_TO_VIRT( _x_ ) ((cyg_uint32)CYGARC_BUS_TO_VIRT(_x_))
|
| 60 |
|
|
|
| 61 |
|
|
#define MAX_PACKET_SIZE 1536
|
| 62 |
|
|
#define SIZEOF_DESCRIPTOR 16
|
| 63 |
|
|
|
| 64 |
|
|
#define CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE \
|
| 65 |
|
|
(((MAX_PACKET_SIZE + SIZEOF_DESCRIPTOR) * \
|
| 66 |
|
|
(MAX_TX_DESCRIPTORS + MAX_RX_DESCRIPTORS)) + 64)
|
| 67 |
|
|
|
| 68 |
|
|
static char pci_mem_buffer[CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE + HAL_DCACHE_LINE_SIZE];
|
| 69 |
|
|
|
| 70 |
|
|
#define CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE \
|
| 71 |
|
|
(CYGARC_UNCACHED_ADDRESS(((unsigned)pci_mem_buffer + HAL_DCACHE_LINE_SIZE - 1) & ~(HAL_DCACHE_LINE_SIZE - 1)))
|
| 72 |
|
|
|
| 73 |
|
|
static I82544 i82544_eth0_priv_data = {
|
| 74 |
|
|
#ifdef CYGSEM_DEVS_ETH_ARM_NPWR_I82544_ETH0_SET_ESA
|
| 75 |
|
|
hardwired_esa: 1,
|
| 76 |
|
|
mac_address: CYGDAT_DEVS_ETH_ARM_NPWR_I82544_ETH0_ESA
|
| 77 |
|
|
#else
|
| 78 |
|
|
hardwired_esa: 0,
|
| 79 |
|
|
#endif
|
| 80 |
|
|
};
|
| 81 |
|
|
|
| 82 |
|
|
ETH_DRV_SC(i82544_sc0,
|
| 83 |
|
|
&i82544_eth0_priv_data, // Driver specific data
|
| 84 |
|
|
CYGDAT_DEVS_ETH_ARM_NPWR_I82544_ETH0_NAME, // Name for device
|
| 85 |
|
|
i82544_start,
|
| 86 |
|
|
i82544_stop,
|
| 87 |
|
|
i82544_ioctl,
|
| 88 |
|
|
i82544_can_send,
|
| 89 |
|
|
i82544_send,
|
| 90 |
|
|
i82544_recv,
|
| 91 |
|
|
i82544_deliver,
|
| 92 |
|
|
i82544_poll,
|
| 93 |
|
|
i82544_int_vector
|
| 94 |
|
|
);
|
| 95 |
|
|
|
| 96 |
|
|
NETDEVTAB_ENTRY(i82544_netdev0,
|
| 97 |
|
|
"i82544_" CYGDAT_DEVS_ETH_ARM_NPWR_I82544_ETH0_NAME,
|
| 98 |
|
|
i82544_init,
|
| 99 |
|
|
&i82544_sc0);
|
| 100 |
|
|
|
| 101 |
|
|
#endif // CYGPKG_DEVS_ETH_ARM_NPWR_I82544_ETH0
|
| 102 |
|
|
|
| 103 |
|
|
|
| 104 |
|
|
// These arrays are used for sanity checking of pointers
|
| 105 |
|
|
I82544 *
|
| 106 |
|
|
i82544_priv_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
|
| 107 |
|
|
#ifdef CYGPKG_DEVS_ETH_ARM_NPWR_I82544_ETH0
|
| 108 |
|
|
&i82544_eth0_priv_data,
|
| 109 |
|
|
#endif
|
| 110 |
|
|
};
|
| 111 |
|
|
|
| 112 |
|
|
#ifdef CYGDBG_USE_ASSERTS
|
| 113 |
|
|
// These are only used when assertions are enabled
|
| 114 |
|
|
cyg_netdevtab_entry_t *
|
| 115 |
|
|
i82544_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
|
| 116 |
|
|
#ifdef CYGPKG_DEVS_ETH_ARM_NPWR_I82544_ETH0
|
| 117 |
|
|
&i82544_netdev0,
|
| 118 |
|
|
#endif
|
| 119 |
|
|
};
|
| 120 |
|
|
|
| 121 |
|
|
struct eth_drv_sc *
|
| 122 |
|
|
i82544_sc_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
|
| 123 |
|
|
#ifdef CYGPKG_DEVS_ETH_ARM_NPWR_I82544_ETH0
|
| 124 |
|
|
&i82544_sc0,
|
| 125 |
|
|
#endif
|
| 126 |
|
|
};
|
| 127 |
|
|
#endif // CYGDBG_USE_ASSERTS
|
| 128 |
|
|
|
| 129 |
|
|
// EOF devs_eth_arm_npwr.inl
|
