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skrzyp |
//==========================================================================
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//
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// devs/eth/arm/uE250/..../include/devs_eth_uE250.inl
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//
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// NMI uE250 ethernet I/O definitions.
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov, hmt, gthomas
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// Contributors: jskov
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// Date: 2001-02-28
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// Purpose: FRV400 ethernet defintions
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//####DESCRIPTIONEND####
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//==========================================================================
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#include // CYGNUM_HAL_INTERRUPT_ETHR
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#include
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#include
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#ifdef __WANT_CONFIG
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#define CYGHWR_NS_DP83902A_PLF_RESET(_dp_) \
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CYG_MACRO_START \
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cyg_uint8 _t; \
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HAL_READ_UINT8(_dp_->reset, _t); \
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CYGACC_CALL_IF_DELAY_US(10); \
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HAL_WRITE_UINT8(_dp_->reset, _t); \
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CYGACC_CALL_IF_DELAY_US(10000); \
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CYG_MACRO_END
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#define DP_IN(_b_, _o_, _d_) \
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CYG_MACRO_START \
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_d_ = pci_io_read_8((cyg_addrword_t)(_b_)+(_o_)); \
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CYG_MACRO_END
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#define DP_OUT(_b_, _o_, _d_) \
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CYG_MACRO_START \
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pci_io_write_8((cyg_addrword_t)(_b_)+(_o_), _d_); \
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CYG_MACRO_END
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#define DP_IN_DATA(_b_, _d_) \
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CYG_MACRO_START \
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_d_ = pci_io_read_16((cyg_addrword_t)(_b_)); \
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CYG_MACRO_END
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#define DP_OUT_DATA(_b_, _d_) \
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CYG_MACRO_START \
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pci_io_write_16((cyg_addrword_t)(_b_), _d_); \
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CYG_MACRO_END
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//#define CYGHWR_NS_DP83902A_PLF_16BIT_DATA
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//#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
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#endif // __WANT_CONFIG
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#ifdef __WANT_DEVS
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#if defined(CYGSEM_DEVS_ETH_UE250_ETH0_SET_ESA)
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#if defined(CYGPKG_REDBOOT)
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#include
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#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
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#include
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#include
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RedBoot_config_option("Network hardware address [MAC]",
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lan_esa,
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ALWAYS_ENABLED, true,
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CONFIG_ESA, 0
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);
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#endif // CYGSEM_REDBOOT_FLASH_CONFIG
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#endif // CYGPKG_REDBOOT
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#include
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#ifndef CONFIG_ESA
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#define CONFIG_ESA 6
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#endif
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#endif
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static cyg_bool
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find_rtl8029_match_func( cyg_uint16 v, cyg_uint16 d, cyg_uint32 c, void *p )
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{
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return ((v == 0x10EC) && (d == 0x8029));
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}
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static void
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_ue250_eth_init(dp83902a_priv_data_t *dp)
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{
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cyg_pci_device_id devid;
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cyg_pci_device dev_info;
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#if defined(CYGSEM_DEVS_ETH_UE250_ETH0_SET_ESA)
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cyg_bool esa_ok;
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unsigned char _esa[6];
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#else
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unsigned char prom[32];
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int i;
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#endif
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devid = CYG_PCI_NULL_DEVID;
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if (cyg_pci_find_matching( &find_rtl8029_match_func, NULL, &devid )) {
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cyg_pci_get_device_info(devid, &dev_info);
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cyg_pci_translate_interrupt(&dev_info, &dp->interrupt);
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dp->base = (cyg_uint8 *)(dev_info.base_map[0] & ~1);
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dp->data = dp->base + 0x10;
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dp->reset = dp->base + 0x1F;
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#if 0
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diag_printf("RTL8029 at %p, interrupt: %x\n", dp->base, dp->interrupt);
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#endif
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#if defined(CYGSEM_DEVS_ETH_UE250_ETH0_SET_ESA)
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esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
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"lan_esa", _esa, CONFIG_ESA);
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if (esa_ok) {
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memcpy(dp->esa, _esa, sizeof(_esa));
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}
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#else
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// Read ESA from EEPROM
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DP_OUT(dp->base, DP_DCR, 0x49); // Wordwide access
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DP_OUT(dp->base, DP_RBCH, 0); // Remote byte count
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DP_OUT(dp->base, DP_RBCL, 0);
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DP_OUT(dp->base, DP_ISR, 0xFF); // Clear any pending interrupts
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DP_OUT(dp->base, DP_IMR, 0x00); // Mask all interrupts
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DP_OUT(dp->base, DP_RCR, 0x20); // Monitor
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DP_OUT(dp->base, DP_TCR, 0x02); // loopback
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DP_OUT(dp->base, DP_RBCH, 32); // Remote byte count
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DP_OUT(dp->base, DP_RBCL, 0);
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DP_OUT(dp->base, DP_RSAL, 0); // Remote address
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DP_OUT(dp->base, DP_RSAH, 0);
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DP_OUT(dp->base, DP_CR, DP_CR_START|DP_CR_RDMA); // Read data
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for (i = 0; i < 32; i++) {
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cyg_uint16 _val;
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HAL_READ_UINT16(dp->data, _val);
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prom[i] = _val;
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}
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// Set ESA into chip
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DP_OUT(dp->base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); // Select page 1
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for (i = 0; i < 6; i++) {
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DP_OUT(dp->base, DP_P1_PAR0+i, prom[i]);
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}
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DP_OUT(dp->base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); // Select page 0
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#endif
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}
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}
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#undef CYGHWR_NS_DP83902A_PLF_INIT
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#define CYGHWR_NS_DP83902A_PLF_INIT(dp) _ue250_eth_init(dp)
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#ifndef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
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static void
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_ue250_eth_int_clear(dp83902a_priv_data_t *dp)
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{
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cyg_drv_interrupt_acknowledge(dp->interrupt);
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}
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#undef CYGHWR_NS_DP83902A_PLF_INT_CLEAR
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#define CYGHWR_NS_DP83902A_PLF_INT_CLEAR(dp) _ue250_eth_int_clear(dp)
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#endif
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#ifdef CYGPKG_DEVS_ETH_UE250_ETH0
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static dp83902a_priv_data_t dp83902a_eth0_priv_data = {
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base : (cyg_uint8*) 0, //
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data : (cyg_uint8*) 0, // Filled in at runtime
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reset: (cyg_uint8*) 0, //
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interrupt: 0, //
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tx_buf1: 0x40, //
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tx_buf2: 0x48, // Buffer layout - change with care
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rx_buf_start: 0x50, //
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rx_buf_end: 0x80, //
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#ifdef CYGSEM_DEVS_ETH_UE250_ETH0_SET_ESA
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esa : CYGDAT_DEVS_ETH_UE250_ETH0_ESA,
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hardwired_esa : true,
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#else
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hardwired_esa : false,
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#endif
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};
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ETH_DRV_SC(dp83902a_sc,
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&dp83902a_eth0_priv_data, // Driver specific data
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CYGDAT_DEVS_ETH_UE250_ETH0_NAME,
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dp83902a_start,
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dp83902a_stop,
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dp83902a_control,
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dp83902a_can_send,
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dp83902a_send,
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dp83902a_recv,
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dp83902a_deliver, // "pseudoDSR" called from fast net thread
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dp83902a_poll, // poll function, encapsulates ISR and DSR
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dp83902a_int_vector);
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NETDEVTAB_ENTRY(dp83902a_netdev,
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"dp83902a_" CYGDAT_DEVS_ETH_UE250_ETH0_NAME,
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dp83902a_init,
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&dp83902a_sc);
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#endif // CYGPKG_DEVS_ETH_UE250_ETH0
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#endif // __WANT_DEVS
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// --------------------------------------------------------------
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// EOF devs_eth_ue250.inl
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