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//==========================================================================
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//
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// devs_eth_h8300_aki3068net.inl
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//
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// DP83902(RTL8019AS) ethernet I/O definitions.
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):
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// Contributors:
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// Date:
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// Purpose: aki3068net ethernet defintions
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//####DESCRIPTIONEND####
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//==========================================================================
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#include // CYGNUM_HAL_INTERRUPT_ETHR
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#include
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#define CYGHWR_NS_DP83902A_PLF_INIT ns_dp83902a_plf_init
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#ifdef __WANT_DEVS
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#ifdef CYGPKG_DEVS_ETH_H8300_AKI3068NET_ETH0
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static dp83902a_priv_data_t dp83902a_eth0_priv_data = {
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base: (cyg_uint8 *)0x200000,
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interrupt: 17,
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tx_buf1: 0x40,
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tx_buf2: 0x48,
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rx_buf_start: 0x50,
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rx_buf_end: 0x80,
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#ifdef CYGSEM_DEVS_ETH_H8300_AKI3068NET_ETH0_SET_ESA
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hardwired_esa: true,
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mac_address: CYGDAT_DEVS_ETH_H8300_AKI3068NET_ETH0_ESA
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#else
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hardwired_esa: false,
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#endif
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};
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ETH_DRV_SC(dp83902a_sc,
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&dp83902a_eth0_priv_data, // Driver specific data
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CYGDAT_DEVS_ETH_H8300_AKI3068NET_ETH0_NAME,
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dp83902a_start,
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dp83902a_stop,
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dp83902a_control,
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dp83902a_can_send,
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dp83902a_send,
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dp83902a_recv,
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dp83902a_deliver, // "pseudoDSR" called from fast net thread
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dp83902a_poll, // poll function, encapsulates ISR and DSR
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dp83902a_int_vector);
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NETDEVTAB_ENTRY(dp83902a_netdev,
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"dp83902a_" CYGDAT_DEVS_ETH_H8300_AKI3068NET_ETH0_NAME,
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dp83902a_init,
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&dp83902a_sc);
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void ns_dp83902a_plf_init(dp83902a_priv_data_t *dp);
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#endif // CYGPKG_DEVS_ETH_H8300_AKI3068NET_ETH0
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#endif
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// EOF devs_eth_h8300_aki3068net.inl
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