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skrzyp |
//==========================================================================
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//
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// devs/eth/mips/ocelot/include/devs_eth_mips_rm7000_ocelot.inl
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//
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// PC i82544 ethernet I/O definitions.
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov, nickg
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// Contributors:jskov
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// Date: 2001-11-25
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// Purpose: PC i82544 ethernet defintions
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//####DESCRIPTIONEND####
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//==========================================================================
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#include // CYGNUM_HAL_INTERRUPT_ETHR
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#ifdef CYGPKG_DEVS_ETH_I386_PC_I82544_ETH0
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#define CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE (CYGARC_UNCACHED_ADDRESS(CYGMEM_SECTION_pci_window))
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#define CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE CYGMEM_SECTION_pci_window_SIZE
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static I82544 i82544_eth0_priv_data = {
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#ifdef CYGSEM_DEVS_ETH_I386_PC_I82544_ETH0_SET_ESA
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hardwired_esa: 1,
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mac_address: CYGDAT_DEVS_ETH_I386_PC_I82544_ETH0_ESA
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#else
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hardwired_esa: 0,
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#endif
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};
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ETH_DRV_SC(i82544_sc0,
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&i82544_eth0_priv_data, // Driver specific data
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CYGDAT_DEVS_ETH_I386_PC_I82544_ETH0_NAME, // Name for device
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i82544_start,
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i82544_stop,
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i82544_ioctl,
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i82544_can_send,
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i82544_send,
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i82544_recv,
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i82544_deliver,
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i82544_poll,
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i82544_int_vector
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);
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NETDEVTAB_ENTRY(i82544_netdev0,
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"i82544_" CYGDAT_DEVS_ETH_I386_PC_I82544_ETH0_NAME,
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i82544_init,
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&i82544_sc0);
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#endif // CYGPKG_DEVS_ETH_I386_PC_I82544_ETH0
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// These arrays are used for sanity checking of pointers
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I82544 *
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i82544_priv_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
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#ifdef CYGPKG_DEVS_ETH_I386_PC_I82544_ETH0
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&i82544_eth0_priv_data,
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#endif
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};
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#ifdef CYGDBG_USE_ASSERTS
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// These are only used when assertions are enabled
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cyg_netdevtab_entry_t *
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i82544_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
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#ifdef CYGPKG_DEVS_ETH_I386_PC_I82544_ETH0
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&i82544_netdev0,
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#endif
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};
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struct eth_drv_sc *
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i82544_sc_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
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#ifdef CYGPKG_DEVS_ETH_I386_PC_I82544_ETH0
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&i82544_sc0,
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#endif
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};
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#endif // CYGDBG_USE_ASSERTS
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// EOF devs_eth_i386_pc_i82544.inl
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