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//==========================================================================
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//
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// if_i82544.c
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//
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// Intel 82544 ethernet driver
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt, gthomas
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// Contributors: Ron Spence, Pacific Softworks, jskov
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// Date: 2000-02-01
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// Purpose:
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// Description: hardware driver for 82544 Intel PRO/100+ ethernet
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// Notes: CU commands such as dump and config should, according
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// to the docs, set the CU active state while executing.
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// That does not seem to be the case though, and the
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// driver polls the completion bit in the packet status
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// word instead.
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//
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// Platform code may provide this vector:
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// CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT if it
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// requires the interrupts to be handled via demuxers
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// attached to a distinct interrupt.
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//
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// Platform code may alternatively define:
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// CYGHWR_DEVS_ETH_INTEL_I82544_DEMUX_ALL if it is necessary
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// to demux all interrupt sources - for example if they are
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// wire-or'd together on some hardware but distinct on
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// others. In this circumstance it is permitted for
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// cyg_pci_translate_interrupt [HAL_PCI_TRANSLATE_INTERRUPT]
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// to return invalid for 2nd and subsequent devices.
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//
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// Platform code can also define these three:
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// CYGPRI_DEVS_ETH_INTEL_I82544_MASK_INTERRUPTS(p_i82544,old)
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// CYGPRI_DEVS_ETH_INTEL_I82544_UNMASK_INTERRUPTS(p_i82544,old)
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// CYGPRI_DEVS_ETH_INTEL_I82544_ACK_INTERRUPTS(p_i82544)
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// which are particularly useful when nested interrupt
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// management is needed (which is always IMHO).
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//
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// Platform code can define this:
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// CYGHWR_DEVS_ETH_INTEL_I82544_MISSED_INTERRUPT(p_i82544)
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// to detect a dropped interrupt and loop again or
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// direct-call the DSR to reschedule the delivery routine.
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// Only a problem on edge-triggered interrupt systems.
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//
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// Platform code can also provide this macro:
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// CYGPRI_DEVS_ETH_INTEL_I82544_INTERRUPT_ACK_LOOP(p_i82544)
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// to handle delaying for acks to register on the interrupt
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// controller as necessary on the EBSA.
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//
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// Platform can define CYGHWR_DEVS_ETH_INTEL_I82544_GET_ESA()
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// as an external means to get ESAs, possibly from RedBoot
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// configuration info that's stored in flash memory.
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//
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// Platform def CYGHWR_DEVS_ETH_INTEL_I82544_HAS_NO_EEPROM
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// removes all code for dealing with the EEPROM for those
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// targets where there is none fitted. Either an external
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// means to get ESAs should be used, or we must rely on
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// hard-wiring the ESA's into each executable by means of the
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// usual CDL configuration.
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//
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// Platform def CYGHWR_DEVS_ETH_INTEL_I82544_HAS_ONE_EEPROM
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// is for hardware with multiple devices, but only one with a
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// serial EEPROM installed. The 2nd device would get either
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// the same ESA - because they are certain to be on different
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// segment and internets - or the same ESA incremented by
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// CYGHWR_DEVS_ETH_INTEL_I82544_HAS_ONE_EEPROM_MAC_ADJUST.
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// CYGHWR_DEVS_ETH_INTEL_I82544_HAS_ONE_EEPROM should be the
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// number (0 or 1) of the device that does have the EEPROM.
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//
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// CYGHWR_DEVS_ETH_INTEL_I82544_PCIMEM_DISCONTIGUOUS enables
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// checking code for breaks in the physical address of PCI
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// window memory. This can happen on some boards where a
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// smaller SDRAM is fitted than the hardware allows, so some
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// higher-order address bits are ignored. We make SDRAM
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// contiguous in mapped memory, but what the i82544 sees
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// might be discontiguous. The checking code skips any
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// allocated chunk who appears to contain such a break, and
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// tries again.
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//
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// CYGHWR_DEVS_ETH_INTEL_I82544_RESET_TIMEOUT( int32 )
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// CYGHWR_DEVS_ETH_INTEL_I82544_TIMEOUT_FIRED( int32 ) if
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// both defined give the driver a means to detect that we
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// have been fixated on the same transmit operation for too
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// long - we missed an interrupt or the device crashed. The
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// int32 argument is used to hold a eg. the value of a
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// fast-running hardware timer.
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//
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// Platform def CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD is
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// used to select Auto Speed Detection for setting up the
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// link parameters.
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//
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// FIXME: replace -1/-2 return values with proper E-defines
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// FIXME: For 82557/8 compatibility i82544_configure() function
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// probably needs some tweaking - config bits differ
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// slightly but crucially.
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// FIXME: EEPROM code not tested on a BE system.
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/system.h>
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#ifdef CYGPKG_IO_ETH_DRIVERS
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#include <pkgconf/io_eth_drivers.h>
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#endif
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#include <pkgconf/devs_eth_intel_i82544.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/cyg_ass.h>
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#include <cyg/hal/hal_arch.h>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/infra/diag.h>
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#include <cyg/hal/hal_if.h>
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#include <cyg/hal/drv_api.h>
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#include <cyg/io/eth/netdev.h>
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#include <cyg/io/eth/eth_drv.h>
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#ifdef CYGPKG_NET
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#include <pkgconf/net.h>
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#include <net/if.h> /* Needed for struct ifnet */
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#endif
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#ifdef CYGPKG_IO_PCI
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#include <cyg/io/pci.h>
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// So we can check the validity of the PCI window against the MLTs opinion,
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// and thereby what the malloc heap consumes willy-nilly:
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#include CYGHWR_MEMORY_LAYOUT_H
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#else
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#error "Need PCI package here"
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#endif
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#include <cyg/devs/eth/i82544_info.h>
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#include CYGDAT_DEVS_ETH_INTEL_I82544_INL
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// ------------------------------------------------------------------------
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#ifdef CYGDBG_DEVS_ETH_INTEL_I82544_CHATTER
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#define DEBUG_82544 // This one prints stuff as packets come and go
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#define DEBUG // Startup printing mainly
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#define noDEBUG_EE // Some EEPROM specific retries &c
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#endif
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#ifdef CYGDBG_USE_ASSERTS
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static struct {
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int can_send;
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int deliver;
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int stats;
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int waitcmd_timeouts;
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int waitcmd_timeouts_cu;
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int lockup_timeouts;
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int bad_cu_idles;
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} missed_interrupt = { 0,0,0, 0,0, 0, 0 };
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#endif
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#ifndef CYGPKG_REDBOOT
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#define os_printf diag_printf
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#define db_printf diag_printf
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#else
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static void os_printf( char *fmt, ... )
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{
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extern int start_console(void);
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extern void end_console(int);
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va_list a;
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int old_console;
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va_start( a, fmt );
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old_console = start_console();
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diag_vprintf( fmt, a );
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end_console(old_console);
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va_end( a );
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}
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#define db_printf os_printf
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#endif
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// ------------------------------------------------------------------------
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//
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// MEMORY ADDRESSING
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//
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// ------------------------------------------------------------------------
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// Macros for writing shared memory structures - no need for byte flipping
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#define READMEM8( _reg_, _val_ ) ((CYG_BYTE)(_val_) = *((volatile CYG_BYTE *)(_reg_)))
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#define WRITEMEM8( _reg_, _val_ ) (*((volatile CYG_BYTE *)(_reg_)) = (CYG_BYTE)(_val_))
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#define READMEM16( _reg_, _val_ ) ((CYG_WORD16)(_val_) = *((volatile CYG_WORD16 *)(_reg_)))
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#define WRITEMEM16( _reg_, _val_ ) (*((volatile CYG_WORD16 *)(_reg_)) = (CYG_WORD16)(_val_))
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#define READMEM32( _reg_, _val_ ) ((CYG_WORD32)(_val_) = *((volatile CYG_WORD32 *)(_reg_)))
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#define WRITEMEM32( _reg_, _val_ ) (*((volatile CYG_WORD32 *)(_reg_)) = (CYG_WORD32)(_val_))
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#define READMEM64( _reg_, _val_ ) ((CYG_WORD64)(_val_) = *((volatile CYG_WORD64 *)(_reg_)))
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#define WRITEMEM64( _reg_, _val_ ) (*((volatile CYG_WORD64 *)(_reg_)) = (CYG_WORD64)(_val_))
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#define OUTL( _v_, _a_ ) WRITEMEM32( _a_, _v_ )
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static inline cyg_uint32 INL(cyg_uint32 io_address)
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{ cyg_uint32 _t_; READMEM32( io_address, _t_ ); return _t_; }
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// ------------------------------------------------------------------------
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// Map from CPU-view addresses to PCI-bus master's view - however that is:
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#ifdef CYGHWR_INTEL_I82544_PCI_VIRT_TO_BUS
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#define VIRT_TO_BUS( _x_ ) CYGHWR_INTEL_I82544_PCI_VIRT_TO_BUS( _x_ )
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#define BUS_TO_VIRT( _x_ ) CYGHWR_INTEL_I82544_PCI_BUS_TO_VIRT( _x_ )
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#else // use default mappings: get a physical address to give to the device
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#define VIRT_TO_BUS( _x_ ) virt_to_bus((cyg_uint32)(_x_))
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static inline cyg_uint32 virt_to_bus(cyg_uint32 p_memory)
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{ return CYGARC_PHYSICAL_ADDRESS(p_memory); }
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#define BUS_TO_VIRT( _x_ ) bus_to_virt((cyg_uint32)(_x_))
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static inline cyg_uint32 bus_to_virt(cyg_uint32 p_bus)
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{ return CYGARC_UNCACHED_ADDRESS(p_bus); }
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#endif // not defined CYGHWR_INTEL_I82544_PCI_VIRT_TO_BUS
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// ------------------------------------------------------------------------
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//
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// 82544 REGISTER OFFSETS
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//
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// ------------------------------------------------------------------------
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// General registers
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#define I82544_CTRL 0x00000
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#define I82544_STATUS 0x00008
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#define I82544_EECD 0x00010
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#define I82544_CTRL_EXT 0x00018
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#define I82544_MDIC 0x00020
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#define I82544_FCAL 0x00028
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#define I82544_FCAH 0x0002c
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#define I82544_FCT 0x00030
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#define I82544_VET 0x00038
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#define I82544_FCTTV 0x00170
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#define I82544_TXCW 0x00178
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#define I82544_RXCW 0x00180
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#define I82544_PBA 0x01000
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// Interrupt control registers
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#define I82544_ICR 0x000c0
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#define I82544_ICS 0x000c8
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#define I82544_IMS 0x000d0
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#define I82544_IMC 0x000d8
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// Receive registers
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#define I82544_RCTL 0x00100
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#define I82544_FCRTL 0x02160
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#define I82544_FCRTH 0x02168
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#define I82544_RDBAL 0x02800
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#define I82544_RDBAH 0x02804
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#define I82544_RDLEN 0x02808
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#define I82544_RDH 0x02810
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#define I82544_RDT 0x02818
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#define I82544_RDTR 0x02820
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#define I82544_RXDCTL 0x02828
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#define I82544_RXCSUM 0x05000
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#define I82544_MTA 0x05200
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#define I82544_RAT 0x05400
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#define I82544_VFTA 0x05600
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#define I82544_RCTL_EN (1<<1)
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#define I82544_RCTL_BAM (1<<15)
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// Transmit registers
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#define I82544_TCTL 0x00400
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#define I82544_TIPG 0x00410
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#define I82544_TBT 0x00448
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#define I82544_AIT 0x00458
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#define I82544_TXDMAC 0x03000
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#define I82544_TDBAL 0x03800
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#define I82544_TDBAH 0x03804
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#define I82544_TDLEN 0x03808
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#define I82544_TDH 0x03810
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#define I82544_TDT 0x03818
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#define I82544_TIDV 0x03820
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#define I82544_TXDCTL 0x03828
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#define I82544_TSPMT 0x03830
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#define I82544_TCTL_EN (1<<1)
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|
|
#define I82544_TCTL_PSP (1<<3)
|
320 |
|
|
|
321 |
|
|
|
322 |
|
|
// ------------------------------------------------------------------------
|
323 |
|
|
//
|
324 |
|
|
// 82544 DEVICE CONTROL WORD DEFNITIONS
|
325 |
|
|
//
|
326 |
|
|
// ------------------------------------------------------------------------
|
327 |
|
|
|
328 |
|
|
#define I82544_CTRL_FD (1<<0)
|
329 |
|
|
#define I82544_CTRL_BEM (1<<1)
|
330 |
|
|
#define I82544_CTRL_LRST (1<<3)
|
331 |
|
|
#define I82544_CTRL_ASDE (1<<5)
|
332 |
|
|
#define I82544_CTRL_SLU (1<<6)
|
333 |
|
|
#define I82544_CTRL_ILOS (1<<7)
|
334 |
|
|
#define I82544_CTRL_SPEED (3<<8)
|
335 |
|
|
#define I82544_CTRL_FRCSPD (1<<11)
|
336 |
|
|
#define I82544_CTRL_FRCDPLX (1<<12)
|
337 |
|
|
#define I82544_CTRL_SWDPINSLO (15<<18)
|
338 |
|
|
#define I82544_CTRL_SWDPINSIO (15<<22)
|
339 |
|
|
#define I82544_CTRL_RST (1<<26)
|
340 |
|
|
#define I82544_CTRL_RFCE (1<<27)
|
341 |
|
|
#define I82544_CTRL_TFCE (1<<28)
|
342 |
|
|
#define I82544_CTRL_VME (1<<30)
|
343 |
|
|
#define I82544_CTRL_PHY_RST (1<<31)
|
344 |
|
|
|
345 |
|
|
#define I82544_CTRL_PHY_RESET (1<<18)
|
346 |
|
|
#define I82544_CTRL_PHY_RESET_DIR (1<<22)
|
347 |
|
|
#define I82544_CTRL_MDIO (1<<20)
|
348 |
|
|
#define I82544_CTRL_MDIO_DIR (1<<24)
|
349 |
|
|
#define I82544_CTRL_MDC (1<<21)
|
350 |
|
|
#define I82544_CTRL_MDC_DIR (1<<25)
|
351 |
|
|
|
352 |
|
|
#define I82544_CTRL_EXT_PHY_RESET4 (1<<4)
|
353 |
|
|
#define I82544_CTRL_EXT_PHY_RESET_DIR4 (1<<8)
|
354 |
|
|
|
355 |
|
|
#define PHY_ADDRESS 1
|
356 |
|
|
|
357 |
|
|
// ------------------------------------------------------------------------
|
358 |
|
|
//
|
359 |
|
|
// 82544 DEVICE STATUS WORD DEFNITIONS
|
360 |
|
|
//
|
361 |
|
|
// ------------------------------------------------------------------------
|
362 |
|
|
|
363 |
|
|
#define I82544_STATUS_FD 0x0001
|
364 |
|
|
#define I82544_STATUS_LU 0x0002
|
365 |
|
|
#define I82544_STATUS_TXOFF 0x0010
|
366 |
|
|
#define I82544_STATUS_TBIMODE 0x0020
|
367 |
|
|
#define I82544_STATUS_SPEED 0x00C0
|
368 |
|
|
#define I82544_STATUS_ASDV 0x0300
|
369 |
|
|
#define I82544_STATUS_PCI_SPD 0x0800
|
370 |
|
|
#define I82544_STATUS_BUS64 0x1000
|
371 |
|
|
#define I82544_STATUS_PCIX_MODE 0x2000
|
372 |
|
|
#define I82544_STATUS_PCIXSPD 0xC000
|
373 |
|
|
|
374 |
|
|
// ------------------------------------------------------------------------
|
375 |
|
|
//
|
376 |
|
|
// 82544 EEPROM INTERFACE
|
377 |
|
|
//
|
378 |
|
|
// ------------------------------------------------------------------------
|
379 |
|
|
|
380 |
|
|
// EEPROM_Ctrl bits.
|
381 |
|
|
#define EE_SHIFT_CLK 0x01 // EEPROM shift clock.
|
382 |
|
|
#define EE_CS 0x02 // EEPROM chip select.
|
383 |
|
|
#define EE_DATA_WRITE 0x04 // EEPROM chip data in.
|
384 |
|
|
#define EE_DATA_READ 0x08 // EEPROM chip data out.
|
385 |
|
|
#define EE_REQ 0x40 // EEPROM request (82546 only)
|
386 |
|
|
#define EE_GNT 0x80 // EEPROM grant (82546 only)
|
387 |
|
|
#define EE_PRES 0x100 // EEPROM present (82546 only)
|
388 |
|
|
#define EE_SIZE 0x200 // EEPROM size (82546 only)
|
389 |
|
|
#define EE_ENB (0x10|EE_CS)
|
390 |
|
|
|
391 |
|
|
|
392 |
|
|
// ------------------------------------------------------------------------
|
393 |
|
|
//
|
394 |
|
|
// RECEIVE DESCRIPTORS
|
395 |
|
|
//
|
396 |
|
|
// ------------------------------------------------------------------------
|
397 |
|
|
|
398 |
|
|
#define I82544_RD_BUFFER 0
|
399 |
|
|
#define I82544_RD_LENGTH 8
|
400 |
|
|
#define I82544_RD_CSUM 10
|
401 |
|
|
#define I82544_RD_STATUS 12
|
402 |
|
|
#define I82544_RD_ERRORS 13
|
403 |
|
|
#define I82544_RD_SPECIAL 14
|
404 |
|
|
#define I82544_RD_SIZE 16
|
405 |
|
|
|
406 |
|
|
#define I82544_RD_STATUS_DD (1<<0)
|
407 |
|
|
#define I82544_RD_STATUS_EOP (1<<1)
|
408 |
|
|
#define I82544_RD_STATUS_IXSM (1<<2)
|
409 |
|
|
#define I82544_RD_STATUS_VP (1<<3)
|
410 |
|
|
#define I82544_RD_STATUS_TCPCS (1<<5)
|
411 |
|
|
#define I82544_RD_STATUS_IPCS (1<<6)
|
412 |
|
|
#define I82544_RD_STATUS_PIF (1<<7)
|
413 |
|
|
|
414 |
|
|
// ------------------------------------------------------------------------
|
415 |
|
|
//
|
416 |
|
|
// TRANSMIT DESCRIPTORS
|
417 |
|
|
//
|
418 |
|
|
// ------------------------------------------------------------------------
|
419 |
|
|
|
420 |
|
|
// Currently we only use the legacy Tx descriptor
|
421 |
|
|
|
422 |
|
|
#define I82544_TD_BUFFER 0
|
423 |
|
|
#define I82544_TD_LENGTH 8
|
424 |
|
|
#define I82544_TD_CSO 10
|
425 |
|
|
#define I82544_TD_CMD 11
|
426 |
|
|
#define I82544_TD_STATUS 12
|
427 |
|
|
#define I82544_TD_CSS 13
|
428 |
|
|
#define I82544_TD_SPECIAL 14
|
429 |
|
|
#define I82544_TD_SIZE 16
|
430 |
|
|
|
431 |
|
|
#define I82544_TD_CMD_EOP (1<<0)
|
432 |
|
|
#define I82544_TD_CMD_IFCS (1<<1)
|
433 |
|
|
#define I82544_TD_CMD_IC (1<<2)
|
434 |
|
|
#define I82544_TD_CMD_RS (1<<3)
|
435 |
|
|
#define I82544_TD_CMD_RPS (1<<4)
|
436 |
|
|
#define I82544_TD_CMD_DEXT (1<<5)
|
437 |
|
|
#define I82544_TD_CMD_VLE (1<<6)
|
438 |
|
|
#define I82544_TD_CMD_IDE (1<<7)
|
439 |
|
|
|
440 |
|
|
#define I82544_TD_STATUS_DD (1<<0)
|
441 |
|
|
#define I82544_TD_STATUS_EC (1<<1)
|
442 |
|
|
#define I82544_TD_STATUS_LC (1<<2)
|
443 |
|
|
#define I82544_TD_STATUS_TU (1<<3)
|
444 |
|
|
|
445 |
|
|
// ------------------------------------------------------------------------
|
446 |
|
|
//
|
447 |
|
|
// DEVICES AND PACKET QUEUES
|
448 |
|
|
//
|
449 |
|
|
// ------------------------------------------------------------------------
|
450 |
|
|
|
451 |
|
|
#define MAX_RX_PACKET_SIZE 1536 // maximum Rx packet size
|
452 |
|
|
#define MAX_TX_PACKET_SIZE 1536 // maximum Tx packet size
|
453 |
|
|
|
454 |
|
|
|
455 |
|
|
// ------------------------------------------------------------------------
|
456 |
|
|
// Use arrays provided by platform header to verify pointers.
|
457 |
|
|
|
458 |
|
|
#ifdef CYGDBG_USE_ASSERTS
|
459 |
|
|
#define CHECK_NDP_SC_LINK() \
|
460 |
|
|
CYG_MACRO_START \
|
461 |
|
|
int i, valid_netdev = 0, valid_sc = 0; \
|
462 |
|
|
for(i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT; i++) { \
|
463 |
|
|
if (i82544_netdev_array[i] == ndp) valid_netdev = 1; \
|
464 |
|
|
if (i82544_sc_array[i] == sc) valid_sc = 1; \
|
465 |
|
|
if (valid_sc || valid_netdev) break; \
|
466 |
|
|
} \
|
467 |
|
|
CYG_ASSERT( valid_netdev, "Bad ndp" ); \
|
468 |
|
|
CYG_ASSERT( valid_sc, "Bad sc" ); \
|
469 |
|
|
CYG_ASSERT( (void *)p_i82544 == i82544_sc_array[i]->driver_private, \
|
470 |
|
|
"sc pointer bad" ); \
|
471 |
|
|
CYG_MACRO_END
|
472 |
|
|
#else
|
473 |
|
|
#define CHECK_NDP_SC_LINK()
|
474 |
|
|
#endif
|
475 |
|
|
|
476 |
|
|
#define IF_BAD_82544( _p_ ) \
|
477 |
|
|
if (({ \
|
478 |
|
|
int i, valid_p = 0; \
|
479 |
|
|
for(i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT; i++) { \
|
480 |
|
|
if (i82544_priv_array[i] == (_p_)) { \
|
481 |
|
|
valid_p = 1; \
|
482 |
|
|
break; \
|
483 |
|
|
} \
|
484 |
|
|
} \
|
485 |
|
|
CYG_ASSERT(valid_p, "Bad pointer-to-i82544"); \
|
486 |
|
|
(!valid_p); \
|
487 |
|
|
}))
|
488 |
|
|
|
489 |
|
|
// ------------------------------------------------------------------------
|
490 |
|
|
//
|
491 |
|
|
// Managing the memory that is windowed onto the PCI bus
|
492 |
|
|
//
|
493 |
|
|
// ------------------------------------------------------------------------
|
494 |
|
|
|
495 |
|
|
static cyg_uint32 i82544_heap_size;
|
496 |
|
|
static cyg_uint8 *i82544_heap_base;
|
497 |
|
|
static cyg_uint8 *i82544_heap_free;
|
498 |
|
|
|
499 |
|
|
static void *mem_reserved_ioctl = (void*)0;
|
500 |
|
|
// uncacheable memory reserved for ioctl calls
|
501 |
|
|
|
502 |
|
|
// ------------------------------------------------------------------------
|
503 |
|
|
//
|
504 |
|
|
// FUNCTION PROTOTYPES
|
505 |
|
|
//
|
506 |
|
|
// ------------------------------------------------------------------------
|
507 |
|
|
|
508 |
|
|
static int pci_init_find_82544s(void);
|
509 |
|
|
|
510 |
|
|
static void i82544_reset(struct i82544* p_i82544);
|
511 |
|
|
static void i82544_setup(struct i82544* p_i82544);
|
512 |
|
|
static int eth_set_mac_address(struct i82544* p_i82544, cyg_uint8 *addr, int eeprom );
|
513 |
|
|
|
514 |
|
|
static void InitRxRing(struct i82544* p_i82544);
|
515 |
|
|
static void InitTxRing(struct i82544* p_i82544);
|
516 |
|
|
|
517 |
|
|
static cyg_uint32
|
518 |
|
|
eth_isr(cyg_vector_t vector, cyg_addrword_t data);
|
519 |
|
|
|
520 |
|
|
static int i82544_configure(struct i82544* p_i82544, int promisc, int oversized);
|
521 |
|
|
|
522 |
|
|
// debugging/logging only:
|
523 |
|
|
//void dump_txcb(TxCB* p_txcb);
|
524 |
|
|
void DisplayStatistics(void);
|
525 |
|
|
void update_statistics(struct i82544* p_i82544);
|
526 |
|
|
//void dump_rfd(RFD* p_rfd, int anyway );
|
527 |
|
|
void dump_all_rfds( int intf );
|
528 |
|
|
void dump_packet(cyg_uint8 *p_buffer, int length);
|
529 |
|
|
|
530 |
|
|
static void i82544_stop( struct eth_drv_sc *sc );
|
531 |
|
|
|
532 |
|
|
// ------------------------------------------------------------------------
|
533 |
|
|
|
534 |
|
|
static void
|
535 |
|
|
udelay(int delay)
|
536 |
|
|
{
|
537 |
|
|
CYGACC_CALL_IF_DELAY_US(delay);
|
538 |
|
|
}
|
539 |
|
|
|
540 |
|
|
// ------------------------------------------------------------------------
|
541 |
|
|
// If we are demuxing for all interrupt sources, we must mask and unmask
|
542 |
|
|
// *all* interrupt sources together.
|
543 |
|
|
|
544 |
|
|
static inline int
|
545 |
|
|
Mask82544Interrupt(struct i82544* p_i82544)
|
546 |
|
|
{
|
547 |
|
|
cyg_drv_interrupt_mask(p_i82544->vector);
|
548 |
|
|
|
549 |
|
|
return 1;
|
550 |
|
|
}
|
551 |
|
|
|
552 |
|
|
static inline void
|
553 |
|
|
UnMask82544Interrupt(struct i82544* p_i82544, int old)
|
554 |
|
|
{
|
555 |
|
|
if (old & 1)
|
556 |
|
|
cyg_drv_interrupt_unmask(p_i82544->vector);
|
557 |
|
|
}
|
558 |
|
|
|
559 |
|
|
|
560 |
|
|
static inline void
|
561 |
|
|
Acknowledge82544Interrupt(struct i82544* p_i82544)
|
562 |
|
|
{
|
563 |
|
|
cyg_drv_interrupt_acknowledge(p_i82544->vector);
|
564 |
|
|
}
|
565 |
|
|
|
566 |
|
|
// ------------------------------------------------------------------------
|
567 |
|
|
// Memory management
|
568 |
|
|
//
|
569 |
|
|
// Simply carve off from the front of the PCI mapped window into real memory
|
570 |
|
|
|
571 |
|
|
static CYG_ADDRESS
|
572 |
|
|
pciwindow_mem_alloc(int size)
|
573 |
|
|
{
|
574 |
|
|
CYG_ADDRESS p_memory;
|
575 |
|
|
int _size = size;
|
576 |
|
|
|
577 |
|
|
#ifdef DEBUG
|
578 |
|
|
// db_printf("pciwindow_mem_alloc %d\n",size);
|
579 |
|
|
#endif
|
580 |
|
|
|
581 |
|
|
CYG_ASSERT(
|
582 |
|
|
(CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE <= (int)i82544_heap_free)
|
583 |
|
|
&&
|
584 |
|
|
((CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE +
|
585 |
|
|
CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE) > (int)i82544_heap_free)
|
586 |
|
|
&&
|
587 |
|
|
(0 < i82544_heap_size)
|
588 |
|
|
&&
|
589 |
|
|
(CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE >= i82544_heap_size)
|
590 |
|
|
&&
|
591 |
|
|
(CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE == (int)i82544_heap_base),
|
592 |
|
|
"Heap variables corrupted" );
|
593 |
|
|
|
594 |
|
|
p_memory = 0;
|
595 |
|
|
size = (size + 3) & ~3;
|
596 |
|
|
if ( (i82544_heap_free+size) < (i82544_heap_base+i82544_heap_size) ) {
|
597 |
|
|
cyg_uint32 *p;
|
598 |
|
|
p_memory = (CYG_ADDRESS)i82544_heap_free;
|
599 |
|
|
i82544_heap_free += size;
|
600 |
|
|
for ( p = (cyg_uint32 *)p_memory; _size > 0; _size -= 4 )
|
601 |
|
|
*p++ = 0;
|
602 |
|
|
}
|
603 |
|
|
|
604 |
|
|
CYG_ASSERT(
|
605 |
|
|
NULL == p_memory ||
|
606 |
|
|
VIRT_TO_BUS( p_memory ) + size == VIRT_TO_BUS( i82544_heap_free ),
|
607 |
|
|
"Discontiguous PCI memory in real addresses" );
|
608 |
|
|
|
609 |
|
|
return p_memory;
|
610 |
|
|
}
|
611 |
|
|
|
612 |
|
|
|
613 |
|
|
// ------------------------------------------------------------------------
|
614 |
|
|
//
|
615 |
|
|
// MDIO
|
616 |
|
|
//
|
617 |
|
|
// Device-specific bit-twiddling and line driving side-effects
|
618 |
|
|
|
619 |
|
|
// CYGACC_CALL_IF_DELAY_US() drags in huge amounts of scheduler locking and
|
620 |
|
|
// the like 'cos it's a VV call! We only want a delay of 1uS tops, so:
|
621 |
|
|
|
622 |
|
|
#define MII_DELAY() do { int z; for ( z = 0; z < 100; z++ ) ; } while (0)
|
623 |
|
|
|
624 |
|
|
#if 0
|
625 |
|
|
# define MII_PRINTF diag_printf
|
626 |
|
|
# define MII_STUFF "%4s | %4s | %4s | %4s [%08x]\n", \
|
627 |
|
|
(*_ctrl & (1<<20)) ? "MDIO" : "---", \
|
628 |
|
|
(*_ctrl & (1<<24)) ? "Wr" : "Rd", \
|
629 |
|
|
(*_ctrl & (1<<21)) ? "CLK" : "clk", \
|
630 |
|
|
*_ctrl
|
631 |
|
|
#else
|
632 |
|
|
# define MII_PRINTF( foo )
|
633 |
|
|
# define MII_STUFF
|
634 |
|
|
#endif
|
635 |
|
|
|
636 |
|
|
static inline cyg_uint32 mii_init( int ioaddr )
|
637 |
|
|
{
|
638 |
|
|
cyg_uint32 ctrl;
|
639 |
|
|
cyg_uint32 *_ctrl = &ctrl;
|
640 |
|
|
*_ctrl = INL( ioaddr + I82544_CTRL );
|
641 |
|
|
*_ctrl &=~ I82544_CTRL_MDC;
|
642 |
|
|
*_ctrl |= I82544_CTRL_MDC_DIR;
|
643 |
|
|
*_ctrl &= ~I82544_CTRL_MDIO_DIR;
|
644 |
|
|
*_ctrl &= ~I82544_CTRL_MDIO;
|
645 |
|
|
OUTL( *_ctrl, ioaddr + I82544_CTRL );
|
646 |
|
|
MII_PRINTF( "mii_init : " MII_STUFF );
|
647 |
|
|
MII_DELAY();
|
648 |
|
|
return *_ctrl;
|
649 |
|
|
}
|
650 |
|
|
|
651 |
|
|
static inline void mii_clock_up( int ioaddr, cyg_uint32 *_ctrl )
|
652 |
|
|
{
|
653 |
|
|
*_ctrl |= I82544_CTRL_MDC;
|
654 |
|
|
OUTL( *_ctrl, ioaddr + I82544_CTRL );
|
655 |
|
|
MII_PRINTF( "mii_clock_up : " MII_STUFF );
|
656 |
|
|
MII_DELAY();
|
657 |
|
|
}
|
658 |
|
|
|
659 |
|
|
static inline void mii_clock_down( int ioaddr, cyg_uint32 *_ctrl )
|
660 |
|
|
{
|
661 |
|
|
*_ctrl &=~ I82544_CTRL_MDC;
|
662 |
|
|
OUTL( *_ctrl, ioaddr + I82544_CTRL );
|
663 |
|
|
MII_PRINTF( "mii_clock_down: " MII_STUFF );
|
664 |
|
|
MII_DELAY();
|
665 |
|
|
}
|
666 |
|
|
|
667 |
|
|
static inline void mii_read_mode( int ioaddr, cyg_uint32 *_ctrl )
|
668 |
|
|
{
|
669 |
|
|
*_ctrl &= ~I82544_CTRL_MDIO_DIR;
|
670 |
|
|
*_ctrl &= ~I82544_CTRL_MDIO;
|
671 |
|
|
OUTL( *_ctrl, ioaddr + I82544_CTRL );
|
672 |
|
|
MII_PRINTF( "mii_read_mode : " MII_STUFF );
|
673 |
|
|
MII_DELAY();
|
674 |
|
|
}
|
675 |
|
|
|
676 |
|
|
static inline int mii_read_data_bit( int ioaddr, cyg_uint32 *_ctrl )
|
677 |
|
|
{
|
678 |
|
|
*_ctrl = INL( ioaddr + I82544_CTRL );
|
679 |
|
|
MII_PRINTF( "mii_read_data : " MII_STUFF );
|
680 |
|
|
return I82544_CTRL_MDIO == (I82544_CTRL_MDIO & *_ctrl);
|
681 |
|
|
}
|
682 |
|
|
|
683 |
|
|
static inline void mii_write_data_bit( int ioaddr, int databit, cyg_uint32 *_ctrl )
|
684 |
|
|
{
|
685 |
|
|
if ( databit )
|
686 |
|
|
*_ctrl |= I82544_CTRL_MDIO;
|
687 |
|
|
else
|
688 |
|
|
*_ctrl &= ~I82544_CTRL_MDIO;
|
689 |
|
|
*_ctrl |= I82544_CTRL_MDIO_DIR; // drive the mdio line
|
690 |
|
|
OUTL( *_ctrl, ioaddr + I82544_CTRL );
|
691 |
|
|
MII_PRINTF( "mii_write_data: " MII_STUFF );
|
692 |
|
|
MII_DELAY();
|
693 |
|
|
}
|
694 |
|
|
|
695 |
|
|
// Pass ioaddr around "invisibly"
|
696 |
|
|
#define MII_INIT() cyg_uint32 _ctrl_val = mii_init(ioaddr); \
|
697 |
|
|
cyg_uint32 *_ctrl = &_ctrl_val;
|
698 |
|
|
|
699 |
|
|
#define MII_CLOCK_UP() mii_clock_up(ioaddr, _ctrl)
|
700 |
|
|
#define MII_CLOCK_DOWN() mii_clock_down(ioaddr, _ctrl)
|
701 |
|
|
#define MII_READ_MODE() mii_read_mode(ioaddr, _ctrl)
|
702 |
|
|
#define MII_READ_DATA_BIT() mii_read_data_bit(ioaddr, _ctrl)
|
703 |
|
|
#define MII_WRITE_DATA_BIT( _d_ ) mii_write_data_bit(ioaddr,(_d_),_ctrl)
|
704 |
|
|
|
705 |
|
|
// ------------------------------------------------------------------------
|
706 |
|
|
//
|
707 |
|
|
// MDIO
|
708 |
|
|
//
|
709 |
|
|
// Management data over the MII interface - nasty hand driven serial stuff
|
710 |
|
|
//
|
711 |
|
|
|
712 |
|
|
static void mii_write_bits( int ioaddr, int val, int bitcount, cyg_uint32 *_ctrl )
|
713 |
|
|
{
|
714 |
|
|
int i;
|
715 |
|
|
// These are deliberately signed ints so that we can send an overlong
|
716 |
|
|
// preamble if we want by saying "send -1 of width 40 bits" and relying
|
717 |
|
|
// on sign extension.
|
718 |
|
|
for ( i = bitcount - 1; i >= 0; i-- ) {
|
719 |
|
|
MII_WRITE_DATA_BIT( (val >> i) & 1 );
|
720 |
|
|
MII_DELAY();
|
721 |
|
|
MII_CLOCK_UP();
|
722 |
|
|
MII_CLOCK_DOWN();
|
723 |
|
|
}
|
724 |
|
|
}
|
725 |
|
|
|
726 |
|
|
static int mii_read_bits( int ioaddr, int bitcount, cyg_uint32 *_ctrl )
|
727 |
|
|
{
|
728 |
|
|
int i;
|
729 |
|
|
int val = 0;
|
730 |
|
|
for ( i = bitcount - 1; i >= 0; i-- ) {
|
731 |
|
|
MII_CLOCK_DOWN();
|
732 |
|
|
val <<= 1;
|
733 |
|
|
val |= MII_READ_DATA_BIT();
|
734 |
|
|
MII_CLOCK_UP();
|
735 |
|
|
}
|
736 |
|
|
return val;
|
737 |
|
|
}
|
738 |
|
|
|
739 |
|
|
#define MII_WRITE_BITS( val, bitcount ) mii_write_bits( ioaddr, val, bitcount, _ctrl )
|
740 |
|
|
#define MII_READ_BITS( bitcount ) mii_read_bits( ioaddr, bitcount, _ctrl )
|
741 |
|
|
|
742 |
|
|
// Now define subsections of the protocol in terms of the above
|
743 |
|
|
|
744 |
|
|
#define MII_WRITE_PREAMBLE() MII_WRITE_BITS( -1, 32 ) // >32 x 1s
|
745 |
|
|
#define MII_WRITE_START() MII_WRITE_BITS( 1, 2 ) // 01
|
746 |
|
|
#define MII_WRITE_WRITE_CMD() MII_WRITE_BITS( 1, 2 ) // 01
|
747 |
|
|
#define MII_WRITE_READ_CMD() MII_WRITE_BITS( 2, 2 ) // 10
|
748 |
|
|
|
749 |
|
|
#define MII_WRITE_PHY_ADDR(_p_) MII_WRITE_BITS( _p_, 5 )
|
750 |
|
|
#define MII_WRITE_REGNUM( _r_ ) MII_WRITE_BITS( (_r_), 5 )
|
751 |
|
|
|
752 |
|
|
#define MII_WRITE_TURNAROUND() MII_WRITE_BITS( 2, 2 )
|
753 |
|
|
|
754 |
|
|
#define MII_READ_TURNAROUND() CYG_MACRO_START \
|
755 |
|
|
MII_READ_MODE(); /* to turn off driving the line */ \
|
756 |
|
|
(void)(MII_READ_BITS( 2 )); /* discard TA "bits" */ \
|
757 |
|
|
CYG_MACRO_END
|
758 |
|
|
|
759 |
|
|
#define MII_IDLE() CYG_MACRO_START \
|
760 |
|
|
MII_READ_MODE(); /* to turn off driving the line */ \
|
761 |
|
|
((void)MII_READ_BITS( 5 )); /* extra clocks in Hi-Z mode */ \
|
762 |
|
|
MII_CLOCK_DOWN(); \
|
763 |
|
|
CYG_MACRO_END
|
764 |
|
|
|
765 |
|
|
#define MII_READ_REGVAL() MII_READ_BITS( 16 )
|
766 |
|
|
#define MII_WRITE_REGVAL( _v_ ) MII_WRITE_BITS( (_v_), 16 )
|
767 |
|
|
|
768 |
|
|
static int mii_read_register( struct i82544 *p_i82544, int phy, int regnum )
|
769 |
|
|
{
|
770 |
|
|
int value = 0;
|
771 |
|
|
cyg_uint32 ioaddr = p_i82544->io_address;
|
772 |
|
|
|
773 |
|
|
if( p_i82544->device == 0x1004 )
|
774 |
|
|
{
|
775 |
|
|
// An 82543, read MII register via software defined pins in
|
776 |
|
|
// CTRL register.
|
777 |
|
|
|
778 |
|
|
MII_INIT();
|
779 |
|
|
MII_WRITE_PREAMBLE();
|
780 |
|
|
MII_WRITE_START();
|
781 |
|
|
MII_WRITE_READ_CMD();
|
782 |
|
|
MII_WRITE_PHY_ADDR(phy);
|
783 |
|
|
MII_WRITE_REGNUM( regnum );
|
784 |
|
|
MII_READ_TURNAROUND();
|
785 |
|
|
value = MII_READ_REGVAL();
|
786 |
|
|
MII_IDLE();
|
787 |
|
|
}
|
788 |
|
|
else
|
789 |
|
|
{
|
790 |
|
|
// Others, read MII register via MDIC register.
|
791 |
|
|
|
792 |
|
|
cyg_uint32 mdic = (2<<26) | (phy<<21) | (regnum<<16);
|
793 |
|
|
|
794 |
|
|
OUTL( mdic, ioaddr + I82544_MDIC );
|
795 |
|
|
|
796 |
|
|
// Wait for ready
|
797 |
|
|
do
|
798 |
|
|
{
|
799 |
|
|
mdic = INL( ioaddr + I82544_MDIC );
|
800 |
|
|
} while( (mdic & (1<<28)) == 0 );
|
801 |
|
|
|
802 |
|
|
value = mdic & 0xFFFF;
|
803 |
|
|
}
|
804 |
|
|
return value;
|
805 |
|
|
}
|
806 |
|
|
|
807 |
|
|
#ifndef CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
|
808 |
|
|
static void mii_write_register( struct i82544 *p_i82544, int phy, int regnum, int value )
|
809 |
|
|
{
|
810 |
|
|
cyg_uint32 ioaddr = p_i82544->io_address;
|
811 |
|
|
|
812 |
|
|
if( p_i82544->device == 0x1004 )
|
813 |
|
|
{
|
814 |
|
|
// An 82543, write MII register via software defined pins in
|
815 |
|
|
// CTRL register.
|
816 |
|
|
|
817 |
|
|
MII_INIT();
|
818 |
|
|
MII_WRITE_PREAMBLE();
|
819 |
|
|
MII_WRITE_START();
|
820 |
|
|
MII_WRITE_WRITE_CMD();
|
821 |
|
|
MII_WRITE_PHY_ADDR(phy);
|
822 |
|
|
MII_WRITE_REGNUM( regnum );
|
823 |
|
|
MII_WRITE_TURNAROUND();
|
824 |
|
|
MII_WRITE_REGVAL( value );
|
825 |
|
|
MII_IDLE();
|
826 |
|
|
}
|
827 |
|
|
else
|
828 |
|
|
{
|
829 |
|
|
// Others, write MII register via MDIC register.
|
830 |
|
|
|
831 |
|
|
cyg_uint32 mdic = (1<<26) | (phy<<21) | (regnum<<16) | (value&0xFFFF);
|
832 |
|
|
|
833 |
|
|
OUTL( mdic, ioaddr + I82544_MDIC );
|
834 |
|
|
|
835 |
|
|
// Wait for ready
|
836 |
|
|
do
|
837 |
|
|
{
|
838 |
|
|
mdic = INL( ioaddr + I82544_MDIC );
|
839 |
|
|
} while( (mdic & (1<<28)) == 0 );
|
840 |
|
|
}
|
841 |
|
|
}
|
842 |
|
|
#endif
|
843 |
|
|
|
844 |
|
|
#ifdef DEBUG
|
845 |
|
|
// dump out the PHY registers
|
846 |
|
|
static void show_phy( struct i82544 *p_i82544, int phy )
|
847 |
|
|
{
|
848 |
|
|
int i;
|
849 |
|
|
|
850 |
|
|
os_printf("PHY %d regs:",phy);
|
851 |
|
|
for( i = 0; i < 32; i++ )
|
852 |
|
|
{
|
853 |
|
|
cyg_uint32 mdic;
|
854 |
|
|
|
855 |
|
|
mdic = mii_read_register( p_i82544, phy, i );
|
856 |
|
|
|
857 |
|
|
if( (i%8)==0 ) os_printf("\n");
|
858 |
|
|
|
859 |
|
|
os_printf("%04x ",mdic);
|
860 |
|
|
}
|
861 |
|
|
os_printf("\n");
|
862 |
|
|
}
|
863 |
|
|
#endif
|
864 |
|
|
|
865 |
|
|
// ------------------------------------------------------------------------
|
866 |
|
|
//
|
867 |
|
|
// GET EEPROM SIZE
|
868 |
|
|
//
|
869 |
|
|
// ------------------------------------------------------------------------
|
870 |
|
|
|
871 |
|
|
// ------------------------------------------------------------------------
|
872 |
|
|
//
|
873 |
|
|
// Serial EEPROM access - much like the other Intel ethernet
|
874 |
|
|
//
|
875 |
|
|
|
876 |
|
|
// CYGACC_CALL_IF_DELAY_US() drags in huge amounts of scheduler locking and
|
877 |
|
|
// the like 'cos it's a VV call! Waste of time, mostly.
|
878 |
|
|
|
879 |
|
|
#define EE_DELAY() do { int z; for ( z = 0; z < 10000; z++ ) ; } while (0)
|
880 |
|
|
|
881 |
|
|
#if 0
|
882 |
|
|
# define EE_PRINTF diag_printf
|
883 |
|
|
# define EE_STUFF "%4s | %4s | %4s | %4s [%08x]\n", \
|
884 |
|
|
(l & EE_SHIFT_CLK) ? "CLK" : "clk", \
|
885 |
|
|
(l & EE_CS) ? "eeCS" : "--", \
|
886 |
|
|
(l & EE_DATA_WRITE) ? "eeDW" : "---", \
|
887 |
|
|
(l & EE_DATA_READ) ? "eeDR" : "---", \
|
888 |
|
|
l & 0xfffff
|
889 |
|
|
#else
|
890 |
|
|
# define EE_PRINTF( foo )
|
891 |
|
|
# define EE_STUFF
|
892 |
|
|
#endif
|
893 |
|
|
|
894 |
|
|
|
895 |
|
|
static inline void ee_select( int ioaddr, struct i82544 *p_i82544 )
|
896 |
|
|
{
|
897 |
|
|
cyg_uint32 l;
|
898 |
|
|
l = INL( ioaddr + I82544_EECD );
|
899 |
|
|
if (p_i82544->device == 0x1010 ||
|
900 |
|
|
p_i82544->device == 0x100e) {
|
901 |
|
|
// i82546 requires REQ/GNT before EEPROM access
|
902 |
|
|
l |= EE_REQ;
|
903 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
904 |
|
|
EE_DELAY();
|
905 |
|
|
while ((l & EE_GNT) == 0)
|
906 |
|
|
l = INL( ioaddr + I82544_EECD );
|
907 |
|
|
}
|
908 |
|
|
l &= ~0x3f;
|
909 |
|
|
l |= EE_ENB;
|
910 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
911 |
|
|
EE_DELAY();
|
912 |
|
|
l |= EE_CS;
|
913 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
914 |
|
|
l = INL( ioaddr + I82544_EECD );
|
915 |
|
|
EE_PRINTF( "ee_select : " EE_STUFF );
|
916 |
|
|
EE_DELAY();
|
917 |
|
|
}
|
918 |
|
|
|
919 |
|
|
static inline void ee_deselect( int ioaddr )
|
920 |
|
|
{
|
921 |
|
|
cyg_uint32 l;
|
922 |
|
|
l = INL( ioaddr + I82544_EECD ) & ~0x3f;
|
923 |
|
|
l |= EE_ENB;
|
924 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
925 |
|
|
EE_PRINTF( "ee_deselect 1 : " EE_STUFF );
|
926 |
|
|
EE_DELAY();
|
927 |
|
|
EE_DELAY();
|
928 |
|
|
EE_DELAY();
|
929 |
|
|
l &= ~EE_CS;
|
930 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
931 |
|
|
l = INL( ioaddr + I82544_EECD );
|
932 |
|
|
EE_PRINTF( "ee_deselect 2 : " EE_STUFF );
|
933 |
|
|
EE_DELAY();
|
934 |
|
|
EE_DELAY();
|
935 |
|
|
EE_DELAY();
|
936 |
|
|
if (l & EE_REQ) {
|
937 |
|
|
l &= ~EE_REQ;
|
938 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
939 |
|
|
EE_DELAY();
|
940 |
|
|
}
|
941 |
|
|
}
|
942 |
|
|
|
943 |
|
|
static inline void ee_clock_up( int ioaddr )
|
944 |
|
|
{
|
945 |
|
|
cyg_uint32 l;
|
946 |
|
|
l = INL( ioaddr + I82544_EECD );
|
947 |
|
|
l |= EE_SHIFT_CLK;
|
948 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
949 |
|
|
EE_DELAY();
|
950 |
|
|
l = INL( ioaddr + I82544_EECD );
|
951 |
|
|
EE_PRINTF( "ee_clock_up : " EE_STUFF );
|
952 |
|
|
EE_DELAY();
|
953 |
|
|
}
|
954 |
|
|
|
955 |
|
|
static inline void ee_clock_down( int ioaddr )
|
956 |
|
|
{
|
957 |
|
|
cyg_uint32 l;
|
958 |
|
|
l = INL( ioaddr + I82544_EECD );
|
959 |
|
|
l &=~ EE_SHIFT_CLK;
|
960 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
961 |
|
|
EE_DELAY();
|
962 |
|
|
l = INL( ioaddr + I82544_EECD );
|
963 |
|
|
EE_PRINTF( "ee_clock_down : " EE_STUFF );
|
964 |
|
|
EE_DELAY();
|
965 |
|
|
}
|
966 |
|
|
|
967 |
|
|
static inline int ee_read_data_bit( int ioaddr )
|
968 |
|
|
{
|
969 |
|
|
cyg_uint32 l;
|
970 |
|
|
l = INL( ioaddr + I82544_EECD );
|
971 |
|
|
EE_PRINTF( "ee_read_data : " EE_STUFF );
|
972 |
|
|
return EE_DATA_READ == (EE_DATA_READ & l);
|
973 |
|
|
}
|
974 |
|
|
|
975 |
|
|
static inline void ee_write_data_bit( int ioaddr, int databit )
|
976 |
|
|
{
|
977 |
|
|
cyg_uint32 l;
|
978 |
|
|
l = INL( ioaddr + I82544_EECD );
|
979 |
|
|
if ( databit )
|
980 |
|
|
l |= EE_DATA_WRITE;
|
981 |
|
|
else
|
982 |
|
|
l &= ~EE_DATA_WRITE;
|
983 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
984 |
|
|
l = INL( ioaddr + I82544_EECD );
|
985 |
|
|
EE_PRINTF( "ee_write_data : " EE_STUFF );
|
986 |
|
|
EE_DELAY();
|
987 |
|
|
}
|
988 |
|
|
|
989 |
|
|
// Pass ioaddr around "invisibly"
|
990 |
|
|
#define EE_SELECT() ee_select(ioaddr, p_i82544)
|
991 |
|
|
#define EE_DESELECT() ee_deselect(ioaddr)
|
992 |
|
|
#define EE_CLOCK_UP() ee_clock_up(ioaddr)
|
993 |
|
|
#define EE_CLOCK_DOWN() ee_clock_down(ioaddr)
|
994 |
|
|
#define EE_READ_DATA_BIT() ee_read_data_bit(ioaddr)
|
995 |
|
|
#define EE_WRITE_DATA_BIT( _d_ ) ee_write_data_bit(ioaddr,(_d_))
|
996 |
|
|
|
997 |
|
|
// ------------------------------------------------------------------------
|
998 |
|
|
|
999 |
|
|
static int
|
1000 |
|
|
get_eeprom_size( struct i82544 *p_i82544 )
|
1001 |
|
|
{
|
1002 |
|
|
cyg_uint32 l, ioaddr = p_i82544->io_address;
|
1003 |
|
|
int i, tmp, addrbits;
|
1004 |
|
|
|
1005 |
|
|
l = INL( ioaddr + I82544_EECD );
|
1006 |
|
|
|
1007 |
|
|
#ifdef DEBUG_EE
|
1008 |
|
|
diag_printf( "get_eeprom_size\n" );
|
1009 |
|
|
#endif
|
1010 |
|
|
|
1011 |
|
|
if (p_i82544->device == 0x1010 ||
|
1012 |
|
|
p_i82544->device == 0x100e) {
|
1013 |
|
|
|
1014 |
|
|
l |= EE_REQ;
|
1015 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
1016 |
|
|
EE_DELAY();
|
1017 |
|
|
while ((l & EE_GNT) == 0)
|
1018 |
|
|
l = INL( ioaddr + I82544_EECD );
|
1019 |
|
|
l &= ~0x3f;
|
1020 |
|
|
l |= EE_ENB;
|
1021 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
1022 |
|
|
EE_DELAY();
|
1023 |
|
|
l |= EE_CS;
|
1024 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
1025 |
|
|
l = INL( ioaddr + I82544_EECD );
|
1026 |
|
|
EE_DELAY();
|
1027 |
|
|
|
1028 |
|
|
for (i = 3; i >= 0; i--) { // Doc says to shift out a zero then:
|
1029 |
|
|
tmp = (6 & (1 << i)) ? 1 : 0; // "6" is the "read" command.
|
1030 |
|
|
EE_WRITE_DATA_BIT(tmp);
|
1031 |
|
|
EE_CLOCK_UP();
|
1032 |
|
|
EE_CLOCK_DOWN();
|
1033 |
|
|
}
|
1034 |
|
|
// Now clock out address zero, looking for the dummy 0 data bit
|
1035 |
|
|
for ( i = 1; i <= 10; i++ ) {
|
1036 |
|
|
EE_WRITE_DATA_BIT(0);
|
1037 |
|
|
EE_CLOCK_UP();
|
1038 |
|
|
EE_CLOCK_DOWN();
|
1039 |
|
|
if (EE_READ_DATA_BIT() == 0)
|
1040 |
|
|
break; // The dummy zero est arrive'
|
1041 |
|
|
}
|
1042 |
|
|
|
1043 |
|
|
if (6 != i && 8 != i)
|
1044 |
|
|
diag_printf("no EEPROM found\n");
|
1045 |
|
|
|
1046 |
|
|
addrbits = i;
|
1047 |
|
|
|
1048 |
|
|
tmp = 0;
|
1049 |
|
|
for (i = 15; i >= 0; i--) {
|
1050 |
|
|
EE_CLOCK_UP();
|
1051 |
|
|
if (EE_READ_DATA_BIT())
|
1052 |
|
|
tmp |= (1<<i);
|
1053 |
|
|
EE_CLOCK_DOWN();
|
1054 |
|
|
}
|
1055 |
|
|
|
1056 |
|
|
l = INL( ioaddr + I82544_EECD ) & ~0x3f;
|
1057 |
|
|
l |= EE_ENB;
|
1058 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
1059 |
|
|
EE_DELAY();
|
1060 |
|
|
EE_DELAY();
|
1061 |
|
|
EE_DELAY();
|
1062 |
|
|
l &= ~EE_CS;
|
1063 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
1064 |
|
|
l = INL( ioaddr + I82544_EECD );
|
1065 |
|
|
EE_DELAY();
|
1066 |
|
|
EE_DELAY();
|
1067 |
|
|
EE_DELAY();
|
1068 |
|
|
|
1069 |
|
|
l &= ~EE_REQ;
|
1070 |
|
|
OUTL( l, ioaddr + I82544_EECD );
|
1071 |
|
|
EE_DELAY();
|
1072 |
|
|
|
1073 |
|
|
return addrbits;
|
1074 |
|
|
}
|
1075 |
|
|
|
1076 |
|
|
return 6;
|
1077 |
|
|
}
|
1078 |
|
|
|
1079 |
|
|
static int
|
1080 |
|
|
read_eeprom_word( struct i82544 *p_i82544, int addrbits, int address )
|
1081 |
|
|
{
|
1082 |
|
|
int i, tmp;
|
1083 |
|
|
cyg_uint32 ioaddr = p_i82544->io_address;
|
1084 |
|
|
|
1085 |
|
|
// Should already be not-selected, but anyway:
|
1086 |
|
|
EE_SELECT();
|
1087 |
|
|
|
1088 |
|
|
// Shift the read command bits out.
|
1089 |
|
|
for (i = 3; i >= 0; i--) { // Doc says to shift out a zero then:
|
1090 |
|
|
tmp = (6 & (1 << i)) ? 1 : 0; // "6" is the "read" command.
|
1091 |
|
|
EE_WRITE_DATA_BIT(tmp);
|
1092 |
|
|
EE_CLOCK_UP();
|
1093 |
|
|
EE_CLOCK_DOWN();
|
1094 |
|
|
}
|
1095 |
|
|
|
1096 |
|
|
// Now clock out address
|
1097 |
|
|
for ( i = addrbits - 1; i >= 0 ; i-- ) {
|
1098 |
|
|
tmp = (address & (1<<i)) ? 1 : 0;
|
1099 |
|
|
EE_WRITE_DATA_BIT(tmp);
|
1100 |
|
|
EE_CLOCK_UP();
|
1101 |
|
|
tmp = EE_READ_DATA_BIT();
|
1102 |
|
|
EE_CLOCK_DOWN();
|
1103 |
|
|
|
1104 |
|
|
// CYG_ASSERT( (0 == tmp) == (0 == i), "Looking for zero handshake bit" );
|
1105 |
|
|
}
|
1106 |
|
|
|
1107 |
|
|
// read in the data
|
1108 |
|
|
tmp = 0;
|
1109 |
|
|
for (i = 15; i >= 0; i--) {
|
1110 |
|
|
EE_CLOCK_UP();
|
1111 |
|
|
if ( EE_READ_DATA_BIT() )
|
1112 |
|
|
tmp |= (1<<i);
|
1113 |
|
|
EE_CLOCK_DOWN();
|
1114 |
|
|
}
|
1115 |
|
|
|
1116 |
|
|
// Terminate the EEPROM access.
|
1117 |
|
|
EE_DESELECT();
|
1118 |
|
|
|
1119 |
|
|
#ifdef DEBUG_EE
|
1120 |
|
|
// diag_printf( "eeprom address %4x: data %4x\n", address, tmp );
|
1121 |
|
|
#endif
|
1122 |
|
|
|
1123 |
|
|
return tmp;
|
1124 |
|
|
}
|
1125 |
|
|
|
1126 |
|
|
// ------------------------------------------------------------------------
|
1127 |
|
|
|
1128 |
|
|
// ------------------------------------------------------------------------
|
1129 |
|
|
//
|
1130 |
|
|
// NETWORK INTERFACE INITIALIZATION
|
1131 |
|
|
//
|
1132 |
|
|
// Function : Init82544
|
1133 |
|
|
//
|
1134 |
|
|
// Description :
|
1135 |
|
|
// This routine resets, configures, and initializes the chip.
|
1136 |
|
|
// It also clears the ethernet statistics structure, and selects
|
1137 |
|
|
// which statistics are supported by this driver.
|
1138 |
|
|
//
|
1139 |
|
|
// ------------------------------------------------------------------------
|
1140 |
|
|
|
1141 |
|
|
static bool
|
1142 |
|
|
i82544_init(struct cyg_netdevtab_entry * ndp)
|
1143 |
|
|
{
|
1144 |
|
|
static int initialized = 0; // only probe PCI et al *once*
|
1145 |
|
|
|
1146 |
|
|
struct eth_drv_sc *sc;
|
1147 |
|
|
cyg_uint32 ioaddr;
|
1148 |
|
|
int count;
|
1149 |
|
|
struct i82544 *p_i82544;
|
1150 |
|
|
cyg_uint8 mac_address[ETHER_ADDR_LEN];
|
1151 |
|
|
|
1152 |
|
|
#ifdef DEBUG
|
1153 |
|
|
db_printf("i82544_init\n");
|
1154 |
|
|
#endif
|
1155 |
|
|
|
1156 |
|
|
sc = (struct eth_drv_sc *)(ndp->device_instance);
|
1157 |
|
|
p_i82544 = (struct i82544 *)(sc->driver_private);
|
1158 |
|
|
|
1159 |
|
|
IF_BAD_82544( p_i82544 ) {
|
1160 |
|
|
#ifdef DEBUG
|
1161 |
|
|
os_printf( "Bad device private pointer %x\n", sc->driver_private );
|
1162 |
|
|
#endif
|
1163 |
|
|
return 0;
|
1164 |
|
|
}
|
1165 |
|
|
|
1166 |
|
|
CHECK_NDP_SC_LINK();
|
1167 |
|
|
|
1168 |
|
|
if ( 0 == initialized++ ) {
|
1169 |
|
|
// then this is the first time ever:
|
1170 |
|
|
if ( ! pci_init_find_82544s() ) {
|
1171 |
|
|
#ifdef DEBUG
|
1172 |
|
|
os_printf( "pci_init_find_82544s failed\n" );
|
1173 |
|
|
#endif
|
1174 |
|
|
return 0;
|
1175 |
|
|
}
|
1176 |
|
|
}
|
1177 |
|
|
|
1178 |
|
|
// If this device is not present, exit
|
1179 |
|
|
if (0 == p_i82544->found)
|
1180 |
|
|
return 0;
|
1181 |
|
|
|
1182 |
|
|
p_i82544->mac_addr_ok = 0;
|
1183 |
|
|
|
1184 |
|
|
ioaddr = p_i82544->io_address; // get I/O address for 82544
|
1185 |
|
|
|
1186 |
|
|
#ifdef DEBUG
|
1187 |
|
|
os_printf("Init82544 %d @ %x\n", p_i82544->index, (int)ndp);
|
1188 |
|
|
#endif
|
1189 |
|
|
|
1190 |
|
|
// Reset device
|
1191 |
|
|
i82544_reset(p_i82544);
|
1192 |
|
|
|
1193 |
|
|
i82544_setup(p_i82544);
|
1194 |
|
|
|
1195 |
|
|
InitRxRing(p_i82544);
|
1196 |
|
|
InitTxRing(p_i82544);
|
1197 |
|
|
|
1198 |
|
|
|
1199 |
|
|
if (p_i82544->hardwired_esa) {
|
1200 |
|
|
// Hardwire the address without consulting the EEPROM.
|
1201 |
|
|
// When this flag is set, the p_i82544 will already contain
|
1202 |
|
|
// the ESA. Copy it to a mac_address for call to set_mac_addr
|
1203 |
|
|
mac_address[0] = p_i82544->mac_address[0];
|
1204 |
|
|
mac_address[1] = p_i82544->mac_address[1];
|
1205 |
|
|
mac_address[2] = p_i82544->mac_address[2];
|
1206 |
|
|
mac_address[3] = p_i82544->mac_address[3];
|
1207 |
|
|
mac_address[4] = p_i82544->mac_address[4];
|
1208 |
|
|
mac_address[5] = p_i82544->mac_address[5];
|
1209 |
|
|
|
1210 |
|
|
eth_set_mac_address(p_i82544, mac_address, 0);
|
1211 |
|
|
|
1212 |
|
|
} else {
|
1213 |
|
|
|
1214 |
|
|
// Acquire the ESA either from extenal means (probably RedBoot
|
1215 |
|
|
// variables) or from the attached EEPROM - if there is one.
|
1216 |
|
|
|
1217 |
|
|
#ifdef CYGHWR_DEVS_ETH_INTEL_I82544_GET_ESA
|
1218 |
|
|
int ok = false;
|
1219 |
|
|
CYGHWR_DEVS_ETH_INTEL_I82544_GET_ESA( p_i82544, mac_address, ok );
|
1220 |
|
|
if ( ok )
|
1221 |
|
|
eth_set_mac_address(p_i82544, mac_address, 0);
|
1222 |
|
|
|
1223 |
|
|
#else // ! CYGHWR_DEVS_ETH_INTEL_I82544_GET_ESA
|
1224 |
|
|
|
1225 |
|
|
#ifndef CYGHWR_DEVS_ETH_INTEL_I82544_HAS_NO_EEPROM
|
1226 |
|
|
int addr_length, i;
|
1227 |
|
|
cyg_uint16 checksum;
|
1228 |
|
|
|
1229 |
|
|
// read eeprom and get 82544's mac address
|
1230 |
|
|
addr_length = get_eeprom_size(p_i82544);
|
1231 |
|
|
// (this is the length of the *EEPROM*s address, not MAC address)
|
1232 |
|
|
|
1233 |
|
|
// If length is 1, it _probably_ means there's no EEPROM
|
1234 |
|
|
// present. Couldn't find an explicit mention of this in the
|
1235 |
|
|
// docs, but length=1 appears to be the behaviour in that case.
|
1236 |
|
|
if (1 == addr_length) {
|
1237 |
|
|
#ifdef DEBUG_EE
|
1238 |
|
|
os_printf("Error: No EEPROM present for device %d\n",
|
1239 |
|
|
p_i82544->index);
|
1240 |
|
|
#endif
|
1241 |
|
|
} else {
|
1242 |
|
|
for (checksum = 0, i = 0, count = 0; count < 64; count++) {
|
1243 |
|
|
cyg_uint16 value;
|
1244 |
|
|
// read word from eeprom
|
1245 |
|
|
value = read_eeprom_word(p_i82544, addr_length, count);
|
1246 |
|
|
#ifdef DEBUG_EE
|
1247 |
|
|
os_printf( "%02x: %04x\n", count, value );
|
1248 |
|
|
#endif
|
1249 |
|
|
checksum += value;
|
1250 |
|
|
if (count < 3) {
|
1251 |
|
|
mac_address[i++] = value & 0xFF;
|
1252 |
|
|
mac_address[i++] = (value >> 8) & 0xFF;
|
1253 |
|
|
}
|
1254 |
|
|
}
|
1255 |
|
|
|
1256 |
|
|
#ifndef CYGHWR_DEVS_ETH_INTEL_I82544_HAS_ONE_EEPROM_WITHOUT_CRC
|
1257 |
|
|
// If the EEPROM checksum is wrong, the MAC address read
|
1258 |
|
|
// from the EEPROM is probably wrong as well. In that
|
1259 |
|
|
// case, we don't set mac_addr_ok, but continue the
|
1260 |
|
|
// initialization. If then somebody calls i82544_start
|
1261 |
|
|
// without calling eth_set_mac_address() first, we refuse
|
1262 |
|
|
// to bring up the interface, because running with an
|
1263 |
|
|
// invalid MAC address is not a very brilliant idea.
|
1264 |
|
|
|
1265 |
|
|
if ((checksum & 0xFFFF) != 0xBABA) {
|
1266 |
|
|
// selftest verified checksum, verify again
|
1267 |
|
|
#ifdef DEBUG_EE
|
1268 |
|
|
os_printf("Warning: Invalid EEPROM checksum %04X for device %d\n",
|
1269 |
|
|
checksum, p_i82544->index);
|
1270 |
|
|
#endif
|
1271 |
|
|
} else // trailing block
|
1272 |
|
|
#endif
|
1273 |
|
|
{
|
1274 |
|
|
p_i82544->mac_addr_ok = 1;
|
1275 |
|
|
#ifdef DEBUG_EE
|
1276 |
|
|
os_printf("Valid EEPROM checksum\n");
|
1277 |
|
|
#endif
|
1278 |
|
|
// Second port of dual-port 82546 uses EEPROM ESA | 1
|
1279 |
|
|
if (p_i82544->device == 0x1010 ||
|
1280 |
|
|
p_i82544->device == 0x100e) {
|
1281 |
|
|
cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(p_i82544->devid);
|
1282 |
|
|
if (CYG_PCI_DEV_GET_FN(devfn) == 1)
|
1283 |
|
|
mac_address[5] |= 1;
|
1284 |
|
|
}
|
1285 |
|
|
eth_set_mac_address(p_i82544, mac_address, 0);
|
1286 |
|
|
}
|
1287 |
|
|
}
|
1288 |
|
|
|
1289 |
|
|
// record the MAC address in the device structure
|
1290 |
|
|
p_i82544->mac_address[0] = mac_address[0];
|
1291 |
|
|
p_i82544->mac_address[1] = mac_address[1];
|
1292 |
|
|
p_i82544->mac_address[2] = mac_address[2];
|
1293 |
|
|
p_i82544->mac_address[3] = mac_address[3];
|
1294 |
|
|
p_i82544->mac_address[4] = mac_address[4];
|
1295 |
|
|
p_i82544->mac_address[5] = mac_address[5];
|
1296 |
|
|
|
1297 |
|
|
#endif // ! CYGHWR_DEVS_ETH_INTEL_I82544_HAS_NO_EEPROM
|
1298 |
|
|
#endif // ! CYGHWR_DEVS_ETH_INTEL_I82544_GET_ESA
|
1299 |
|
|
}
|
1300 |
|
|
|
1301 |
|
|
#ifdef DEBUG
|
1302 |
|
|
os_printf("i82544_init: MAC Address = %02X %02X %02X %02X %02X %02X\n",
|
1303 |
|
|
p_i82544->mac_address[0], p_i82544->mac_address[1],
|
1304 |
|
|
p_i82544->mac_address[2], p_i82544->mac_address[3],
|
1305 |
|
|
p_i82544->mac_address[4], p_i82544->mac_address[5]);
|
1306 |
|
|
#endif
|
1307 |
|
|
|
1308 |
|
|
// and record the net dev pointer
|
1309 |
|
|
p_i82544->ndp = (void *)ndp;
|
1310 |
|
|
|
1311 |
|
|
p_i82544->within_send = 0; // init recursion level
|
1312 |
|
|
|
1313 |
|
|
// Initialize upper level driver
|
1314 |
|
|
if ( p_i82544->mac_addr_ok )
|
1315 |
|
|
(sc->funs->eth_drv->init)(sc, &(p_i82544->mac_address[0]) );
|
1316 |
|
|
else
|
1317 |
|
|
{
|
1318 |
|
|
(sc->funs->eth_drv->init)(sc, NULL );
|
1319 |
|
|
}
|
1320 |
|
|
|
1321 |
|
|
|
1322 |
|
|
#ifdef DEBUG
|
1323 |
|
|
|
1324 |
|
|
os_printf("CTRL %08x\n",INL( ioaddr + I82544_CTRL ));
|
1325 |
|
|
os_printf("STATUS %08x\n",INL( ioaddr + I82544_STATUS ));
|
1326 |
|
|
|
1327 |
|
|
#endif
|
1328 |
|
|
|
1329 |
|
|
return (1);
|
1330 |
|
|
}
|
1331 |
|
|
|
1332 |
|
|
// ------------------------------------------------------------------------
|
1333 |
|
|
//
|
1334 |
|
|
// Function : i82544_setup
|
1335 |
|
|
//
|
1336 |
|
|
// ------------------------------------------------------------------------
|
1337 |
|
|
|
1338 |
|
|
static void
|
1339 |
|
|
i82544_setup( struct i82544 *p_i82544 )
|
1340 |
|
|
{
|
1341 |
|
|
cyg_uint32 ioaddr;
|
1342 |
|
|
cyg_uint32 ctrl;
|
1343 |
|
|
#ifndef CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
|
1344 |
|
|
cyg_uint32 ctrl_ext;
|
1345 |
|
|
#endif
|
1346 |
|
|
|
1347 |
|
|
ioaddr = p_i82544->io_address; // get 82544's I/O address
|
1348 |
|
|
|
1349 |
|
|
#ifdef CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
|
1350 |
|
|
// Use Auto-negotiation
|
1351 |
|
|
|
1352 |
|
|
ctrl = INL( ioaddr + I82544_CTRL );
|
1353 |
|
|
|
1354 |
|
|
// Set link up bit
|
1355 |
|
|
ctrl |= I82544_CTRL_SLU | I82544_CTRL_ASDE;
|
1356 |
|
|
ctrl &= ~(I82544_CTRL_ILOS | I82544_CTRL_FRCSPD | I82544_CTRL_FRCDPLX);
|
1357 |
|
|
OUTL( ctrl, ioaddr + I82544_CTRL );
|
1358 |
|
|
udelay(20);
|
1359 |
|
|
|
1360 |
|
|
// we can assume link is up with autonegotiation
|
1361 |
|
|
p_i82544->link = 1;
|
1362 |
|
|
|
1363 |
|
|
// wait up to 5 seconds for link to come up
|
1364 |
|
|
{
|
1365 |
|
|
int delay_cnt = 500;
|
1366 |
|
|
while ((mii_read_register( p_i82544, PHY_ADDRESS, 1 ) & 0x4) == 0) {
|
1367 |
|
|
udelay(10000);
|
1368 |
|
|
if (--delay_cnt <= 0)
|
1369 |
|
|
break;
|
1370 |
|
|
}
|
1371 |
|
|
}
|
1372 |
|
|
|
1373 |
|
|
#else
|
1374 |
|
|
// The following sequence of resets and bit twiddling seem to be
|
1375 |
|
|
// necessary to get the 82543 working. Not sure what is necessary
|
1376 |
|
|
// for the 82544.
|
1377 |
|
|
|
1378 |
|
|
ctrl = INL( ioaddr + I82544_CTRL );
|
1379 |
|
|
|
1380 |
|
|
// Set link up bit
|
1381 |
|
|
ctrl |= I82544_CTRL_SLU;
|
1382 |
|
|
ctrl &= ~I82544_CTRL_ILOS;
|
1383 |
|
|
OUTL( ctrl, ioaddr + I82544_CTRL );
|
1384 |
|
|
udelay(20);
|
1385 |
|
|
|
1386 |
|
|
// Force PHY physical reset
|
1387 |
|
|
// We can only access the PHY after we have done this.
|
1388 |
|
|
|
1389 |
|
|
ctrl_ext = INL( ioaddr + I82544_CTRL_EXT );
|
1390 |
|
|
ctrl_ext |= I82544_CTRL_EXT_PHY_RESET_DIR4;
|
1391 |
|
|
OUTL( ctrl_ext, ioaddr + I82544_CTRL_EXT );
|
1392 |
|
|
udelay( 20000 );
|
1393 |
|
|
|
1394 |
|
|
ctrl_ext = INL( ioaddr + I82544_CTRL_EXT );
|
1395 |
|
|
ctrl_ext &= ~I82544_CTRL_EXT_PHY_RESET4;
|
1396 |
|
|
OUTL( ctrl_ext, ioaddr + I82544_CTRL_EXT );
|
1397 |
|
|
udelay( 20000 );
|
1398 |
|
|
|
1399 |
|
|
ctrl_ext = INL( ioaddr + I82544_CTRL_EXT );
|
1400 |
|
|
ctrl_ext |= I82544_CTRL_EXT_PHY_RESET4;
|
1401 |
|
|
OUTL( ctrl_ext, ioaddr + I82544_CTRL_EXT );
|
1402 |
|
|
udelay( 20000 );
|
1403 |
|
|
|
1404 |
|
|
#ifdef DEBUG
|
1405 |
|
|
show_phy( p_i82544, PHY_ADDRESS );
|
1406 |
|
|
#endif
|
1407 |
|
|
|
1408 |
|
|
#if 0
|
1409 |
|
|
// Reset PHY
|
1410 |
|
|
// Does not appear to be necessary.
|
1411 |
|
|
{
|
1412 |
|
|
cyg_uint16 phy_ctrl;
|
1413 |
|
|
phy_ctrl = mii_read_register( p_i82544, PHY_ADDRESS, 0 );
|
1414 |
|
|
phy_ctrl = 0x9000;
|
1415 |
|
|
// os_printf("PHY ctrl %04x\n",phy_ctrl);
|
1416 |
|
|
mii_write_register( p_i82544, PHY_ADDRESS, 0, phy_ctrl );
|
1417 |
|
|
do {
|
1418 |
|
|
phy_ctrl = mii_read_register( p_i82544, PHY_ADDRESS, 0 );
|
1419 |
|
|
// os_printf("PHY ctrl %04x\n",phy_ctrl);
|
1420 |
|
|
} while( phy_ctrl & 0x8000 );
|
1421 |
|
|
}
|
1422 |
|
|
show_phy( p_i82544, PHY_ADDRESS );
|
1423 |
|
|
#endif
|
1424 |
|
|
|
1425 |
|
|
#if 0
|
1426 |
|
|
// Tinker with PHY configuration.
|
1427 |
|
|
// Only on 82543? May not be necessary at all, since disabling
|
1428 |
|
|
// this does not see to make any difference.
|
1429 |
|
|
{
|
1430 |
|
|
cyg_uint16 data;
|
1431 |
|
|
|
1432 |
|
|
// Set CRS on Tx bit in PHY specific CR
|
1433 |
|
|
data = mii_read_register( p_i82544, PHY_ADDRESS, 16 );
|
1434 |
|
|
os_printf("PSCR %04x\n",data);
|
1435 |
|
|
data |= 0x0800;
|
1436 |
|
|
mii_write_register( p_i82544, PHY_ADDRESS, 16, data );
|
1437 |
|
|
|
1438 |
|
|
// Set TX clock to 25MHz in PHY extended CR
|
1439 |
|
|
data = mii_read_register( p_i82544, PHY_ADDRESS, 20 );
|
1440 |
|
|
os_printf("PSECR %04x\n",data);
|
1441 |
|
|
data |= 0x0070;
|
1442 |
|
|
mii_write_register( p_i82544, PHY_ADDRESS, 20, data );
|
1443 |
|
|
}
|
1444 |
|
|
show_phy( p_i82544, PHY_ADDRESS );
|
1445 |
|
|
#endif
|
1446 |
|
|
|
1447 |
|
|
#if 1
|
1448 |
|
|
// Force speed renegotiation.
|
1449 |
|
|
|
1450 |
|
|
{
|
1451 |
|
|
cyg_uint16 phy_ctrl;
|
1452 |
|
|
cyg_uint16 phy_stat;
|
1453 |
|
|
int delay_cnt = 100 * 5; // wait five seconds, then give up
|
1454 |
|
|
|
1455 |
|
|
p_i82544->link = 0;
|
1456 |
|
|
phy_ctrl = mii_read_register( p_i82544, PHY_ADDRESS, 0 );
|
1457 |
|
|
phy_ctrl |= 0x1200;
|
1458 |
|
|
// os_printf("PHY ctrl %04x\n",phy_ctrl);
|
1459 |
|
|
mii_write_register( p_i82544, PHY_ADDRESS, 0, phy_ctrl );
|
1460 |
|
|
// Wait for it to complete
|
1461 |
|
|
do {
|
1462 |
|
|
udelay(10000);
|
1463 |
|
|
phy_stat = mii_read_register( p_i82544, PHY_ADDRESS, 1 );
|
1464 |
|
|
phy_stat = mii_read_register( p_i82544, PHY_ADDRESS, 1 );
|
1465 |
|
|
} while( (phy_stat & 0x0020) == 0 && (delay_cnt-- > 0) );
|
1466 |
|
|
|
1467 |
|
|
if (phy_stat & 0x0020)
|
1468 |
|
|
p_i82544->link = 1;
|
1469 |
|
|
}
|
1470 |
|
|
|
1471 |
|
|
#ifdef DEBUG
|
1472 |
|
|
show_phy( p_i82544, PHY_ADDRESS );
|
1473 |
|
|
#endif
|
1474 |
|
|
#endif
|
1475 |
|
|
|
1476 |
|
|
#if 0
|
1477 |
|
|
// Reset link
|
1478 |
|
|
OUTL( ctrl | I82544_CTRL_LRST, ioaddr + I82544_CTRL );
|
1479 |
|
|
udelay(20);
|
1480 |
|
|
OUTL( ctrl, ioaddr + I82544_CTRL );
|
1481 |
|
|
udelay(20);
|
1482 |
|
|
show_phy( p_i82544, PHY_ADDRESS );
|
1483 |
|
|
#endif
|
1484 |
|
|
|
1485 |
|
|
|
1486 |
|
|
|
1487 |
|
|
// Transfer speed and duplicity settings from PHY to MAC
|
1488 |
|
|
|
1489 |
|
|
// In theory the MAC is supposed to auto-configure from what the
|
1490 |
|
|
// PHY has autonegotiated. In practice this does not seem to work
|
1491 |
|
|
// (on the 82543 at least, it always thinks it is 1000MHz full
|
1492 |
|
|
// duplex) and we have to transfer the settings from the PHY by
|
1493 |
|
|
// hand. Additionally, the settings in the PHY ctrl register seem
|
1494 |
|
|
// bogus, so we read the values out of the PHY specific status
|
1495 |
|
|
// register instead.
|
1496 |
|
|
|
1497 |
|
|
if (p_i82544->link) {
|
1498 |
|
|
cyg_uint16 phy_pssr;
|
1499 |
|
|
|
1500 |
|
|
phy_pssr = mii_read_register( p_i82544, PHY_ADDRESS, 17 );
|
1501 |
|
|
|
1502 |
|
|
ctrl = INL( ioaddr + I82544_CTRL );
|
1503 |
|
|
// os_printf("CTRL %08x\n",ctrl);
|
1504 |
|
|
ctrl &= ~(I82544_CTRL_SPEED | I82544_CTRL_FD);
|
1505 |
|
|
if( phy_pssr & (1<<13) )
|
1506 |
|
|
ctrl |= I82544_CTRL_FD;
|
1507 |
|
|
|
1508 |
|
|
// Transfer speed
|
1509 |
|
|
ctrl |= ((phy_pssr>>14)&3)<<8;
|
1510 |
|
|
|
1511 |
|
|
ctrl |= I82544_CTRL_FRCDPLX | I82544_CTRL_FRCSPD;
|
1512 |
|
|
|
1513 |
|
|
OUTL( ctrl, ioaddr + I82544_CTRL );
|
1514 |
|
|
// os_printf("CTRL %08x\n",ctrl);
|
1515 |
|
|
}
|
1516 |
|
|
|
1517 |
|
|
|
1518 |
|
|
#if 0
|
1519 |
|
|
#ifdef DEBUG
|
1520 |
|
|
{
|
1521 |
|
|
int status = i82544_status( sc );
|
1522 |
|
|
static int speed[4] = { 10, 100, 1000, 1000 };
|
1523 |
|
|
os_printf("i82544_start %d flg %x Link = %s, %d Mbps, %s Duplex\n",
|
1524 |
|
|
p_i82544->index,
|
1525 |
|
|
*(int *)p_i82544,
|
1526 |
|
|
status & GEN_STATUS_LINK ? "Up" : "Down",
|
1527 |
|
|
speed[(status & GEN_STATUS_BPS)>>GEN_STATUS_BPS_SHIFT],
|
1528 |
|
|
status & GEN_STATUS_FDX ? "Full" : "Half");
|
1529 |
|
|
}
|
1530 |
|
|
#endif
|
1531 |
|
|
#endif
|
1532 |
|
|
|
1533 |
|
|
// Hang around here for a bit to let the device settle down. We
|
1534 |
|
|
// don't seem to get away without this.
|
1535 |
|
|
|
1536 |
|
|
udelay( 1000000 );
|
1537 |
|
|
|
1538 |
|
|
#if 0
|
1539 |
|
|
|
1540 |
|
|
// Having done all that, the interface still does not work
|
1541 |
|
|
// properly, UNLESS I now wait >= 45 seconds here. After that it
|
1542 |
|
|
// seems happy. I cannot find any difference in the state of the
|
1543 |
|
|
// PHY or the 82543 to explain this.
|
1544 |
|
|
|
1545 |
|
|
show_phy( p_i82544, PHY_ADDRESS );
|
1546 |
|
|
os_printf("CTRL %08x\n",INL( ioaddr + I82544_CTRL ));
|
1547 |
|
|
os_printf("STATUS %08x\n",INL( ioaddr + I82544_STATUS ));
|
1548 |
|
|
os_printf("ICR %08x\n",INL( ioaddr + I82544_ICR ));
|
1549 |
|
|
os_printf("RCTL %08x\n",INL( ioaddr + I82544_RCTL ));
|
1550 |
|
|
os_printf("TCTL %08x\n",INL( ioaddr + I82544_TCTL ));
|
1551 |
|
|
|
1552 |
|
|
os_printf("Waiting 45 seconds\n");
|
1553 |
|
|
{
|
1554 |
|
|
int i;
|
1555 |
|
|
cyg_uint32 status = INL( ioaddr + I82544_STATUS );
|
1556 |
|
|
// for( i = 0; i < 60; i++ ) // works
|
1557 |
|
|
// for( i = 0; i < 45; i++ ) // works
|
1558 |
|
|
// for( i = 0; i < 40; i++ ) // fails
|
1559 |
|
|
// for( i = 0; i < 35; i++ ) // fails
|
1560 |
|
|
// for( i = 0; i < 30; i++ ) // fails
|
1561 |
|
|
{
|
1562 |
|
|
cyg_uint32 s;
|
1563 |
|
|
PC_WRITE_SCREEN_32( 60, i );
|
1564 |
|
|
udelay(1000000);
|
1565 |
|
|
s = INL( ioaddr + I82544_STATUS );
|
1566 |
|
|
if( s != status )
|
1567 |
|
|
{
|
1568 |
|
|
os_printf("%d STATUS change %08x\n",i,s);
|
1569 |
|
|
status = s;
|
1570 |
|
|
}
|
1571 |
|
|
}
|
1572 |
|
|
}
|
1573 |
|
|
|
1574 |
|
|
show_phy( p_i82544, PHY_ADDRESS );
|
1575 |
|
|
os_printf("CTRL %08x\n",INL( ioaddr + I82544_CTRL ));
|
1576 |
|
|
os_printf("STATUS %08x\n",INL( ioaddr + I82544_STATUS ));
|
1577 |
|
|
os_printf("ICR %08x\n",INL( ioaddr + I82544_ICR ));
|
1578 |
|
|
os_printf("RCTL %08x\n",INL( ioaddr + I82544_RCTL ));
|
1579 |
|
|
os_printf("TCTL %08x\n",INL( ioaddr + I82544_TCTL ));
|
1580 |
|
|
|
1581 |
|
|
#endif
|
1582 |
|
|
#endif // CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
|
1583 |
|
|
|
1584 |
|
|
// Set up interrupts
|
1585 |
|
|
|
1586 |
|
|
// Clear any pending interrupts
|
1587 |
|
|
ctrl = INL( ioaddr + I82544_ICR );
|
1588 |
|
|
|
1589 |
|
|
// clear all mask bits
|
1590 |
|
|
OUTL( 0xFFFFFFFF, ioaddr + I82544_IMC );
|
1591 |
|
|
|
1592 |
|
|
// Set interrupt bits for:
|
1593 |
|
|
// 1 = Transmit queue empty
|
1594 |
|
|
// 7 = Receiver timeout interrupt
|
1595 |
|
|
OUTL( (1<<1)|(1<<7), ioaddr + I82544_IMS );
|
1596 |
|
|
|
1597 |
|
|
}
|
1598 |
|
|
|
1599 |
|
|
// ------------------------------------------------------------------------
|
1600 |
|
|
//
|
1601 |
|
|
// Function : i82544_start
|
1602 |
|
|
//
|
1603 |
|
|
// ------------------------------------------------------------------------
|
1604 |
|
|
|
1605 |
|
|
static void
|
1606 |
|
|
i82544_start( struct eth_drv_sc *sc, unsigned char *enaddr, int flags )
|
1607 |
|
|
{
|
1608 |
|
|
struct i82544 *p_i82544;
|
1609 |
|
|
cyg_uint32 ioaddr;
|
1610 |
|
|
cyg_uint32 txctl, rxctl;
|
1611 |
|
|
|
1612 |
|
|
#ifdef CYGPKG_NET
|
1613 |
|
|
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
|
1614 |
|
|
#endif
|
1615 |
|
|
#ifdef DEBUG
|
1616 |
|
|
db_printf("i82544_start\n");
|
1617 |
|
|
#endif
|
1618 |
|
|
|
1619 |
|
|
p_i82544 = (struct i82544 *)sc->driver_private;
|
1620 |
|
|
ioaddr = p_i82544->io_address; // get 82544's I/O address
|
1621 |
|
|
|
1622 |
|
|
IF_BAD_82544( p_i82544 ) {
|
1623 |
|
|
#ifdef DEBUG
|
1624 |
|
|
os_printf( "i82544_start: Bad device pointer %x\n", p_i82544 );
|
1625 |
|
|
#endif
|
1626 |
|
|
return;
|
1627 |
|
|
}
|
1628 |
|
|
|
1629 |
|
|
if ( ! p_i82544->mac_addr_ok ) {
|
1630 |
|
|
#ifdef DEBUG
|
1631 |
|
|
os_printf("i82544_start %d: invalid MAC address, "
|
1632 |
|
|
"can't bring up interface\n",
|
1633 |
|
|
p_i82544->index );
|
1634 |
|
|
#endif
|
1635 |
|
|
return;
|
1636 |
|
|
}
|
1637 |
|
|
|
1638 |
|
|
if ( p_i82544->active )
|
1639 |
|
|
i82544_stop( sc );
|
1640 |
|
|
|
1641 |
|
|
// Enable device
|
1642 |
|
|
p_i82544->active = 1;
|
1643 |
|
|
|
1644 |
|
|
/* Enable promiscuous mode if requested, reception of oversized frames always.
|
1645 |
|
|
* The latter is needed for VLAN support and shouldn't hurt even if we're not
|
1646 |
|
|
* using VLANs.
|
1647 |
|
|
*/
|
1648 |
|
|
i82544_configure(p_i82544, 0
|
1649 |
|
|
#ifdef CYGPKG_NET
|
1650 |
|
|
|| !!(ifp->if_flags & IFF_PROMISC)
|
1651 |
|
|
#endif
|
1652 |
|
|
#ifdef ETH_DRV_FLAGS_PROMISC_MODE
|
1653 |
|
|
|| !!(flags & ETH_DRV_FLAGS_PROMISC_MODE)
|
1654 |
|
|
#endif
|
1655 |
|
|
, 1);
|
1656 |
|
|
|
1657 |
|
|
// enable receiver
|
1658 |
|
|
rxctl = INL( ioaddr + I82544_RCTL );
|
1659 |
|
|
rxctl |= I82544_RCTL_EN;
|
1660 |
|
|
OUTL( rxctl, ioaddr + I82544_RCTL );
|
1661 |
|
|
|
1662 |
|
|
// Enable transmitter
|
1663 |
|
|
txctl = INL( ioaddr + I82544_TCTL );
|
1664 |
|
|
txctl |= I82544_TCTL_EN;
|
1665 |
|
|
OUTL( txctl, ioaddr + I82544_TCTL );
|
1666 |
|
|
|
1667 |
|
|
}
|
1668 |
|
|
|
1669 |
|
|
// ------------------------------------------------------------------------
|
1670 |
|
|
//
|
1671 |
|
|
// Function : i82544_status
|
1672 |
|
|
//
|
1673 |
|
|
// ------------------------------------------------------------------------
|
1674 |
|
|
int
|
1675 |
|
|
i82544_status( struct eth_drv_sc *sc )
|
1676 |
|
|
{
|
1677 |
|
|
int status;
|
1678 |
|
|
struct i82544 *p_i82544;
|
1679 |
|
|
cyg_uint32 ioaddr;
|
1680 |
|
|
#ifdef DEBUG
|
1681 |
|
|
db_printf("i82544_status\n");
|
1682 |
|
|
#endif
|
1683 |
|
|
|
1684 |
|
|
p_i82544 = (struct i82544 *)sc->driver_private;
|
1685 |
|
|
|
1686 |
|
|
IF_BAD_82544( p_i82544 ) {
|
1687 |
|
|
#ifdef DEBUG
|
1688 |
|
|
os_printf( "i82544_status: Bad device pointer %x\n", p_i82544 );
|
1689 |
|
|
#endif
|
1690 |
|
|
return 0;
|
1691 |
|
|
}
|
1692 |
|
|
|
1693 |
|
|
ioaddr = p_i82544->io_address; // get 82544's I/O address
|
1694 |
|
|
|
1695 |
|
|
status = INL(ioaddr + I82544_STATUS);
|
1696 |
|
|
|
1697 |
|
|
return status;
|
1698 |
|
|
}
|
1699 |
|
|
|
1700 |
|
|
// ------------------------------------------------------------------------
|
1701 |
|
|
//
|
1702 |
|
|
// Function : BringDown82544
|
1703 |
|
|
//
|
1704 |
|
|
// ------------------------------------------------------------------------
|
1705 |
|
|
|
1706 |
|
|
static void
|
1707 |
|
|
i82544_stop( struct eth_drv_sc *sc )
|
1708 |
|
|
{
|
1709 |
|
|
struct i82544 *p_i82544;
|
1710 |
|
|
cyg_uint32 ioaddr;
|
1711 |
|
|
cyg_uint32 txctl, rxctl;
|
1712 |
|
|
|
1713 |
|
|
#ifdef DEBUG
|
1714 |
|
|
db_printf("i82544_stop\n");
|
1715 |
|
|
#endif
|
1716 |
|
|
|
1717 |
|
|
p_i82544 = (struct i82544 *)sc->driver_private;
|
1718 |
|
|
|
1719 |
|
|
IF_BAD_82544( p_i82544 ) {
|
1720 |
|
|
#ifdef DEBUG
|
1721 |
|
|
os_printf( "i82544_stop: Bad device pointer %x\n", p_i82544 );
|
1722 |
|
|
#endif
|
1723 |
|
|
return;
|
1724 |
|
|
}
|
1725 |
|
|
|
1726 |
|
|
#ifdef DEBUG
|
1727 |
|
|
os_printf("i82544_stop %d flg %x\n", p_i82544->index, *(int *)p_i82544 );
|
1728 |
|
|
#endif
|
1729 |
|
|
|
1730 |
|
|
p_i82544->active = 0; // stop people tormenting it
|
1731 |
|
|
|
1732 |
|
|
ioaddr = p_i82544->io_address;
|
1733 |
|
|
|
1734 |
|
|
// disable receiver
|
1735 |
|
|
rxctl = INL( ioaddr + I82544_RCTL );
|
1736 |
|
|
rxctl &= ~I82544_RCTL_EN;
|
1737 |
|
|
OUTL( rxctl, ioaddr + I82544_RCTL );
|
1738 |
|
|
|
1739 |
|
|
// Enable transmitter
|
1740 |
|
|
txctl = INL( ioaddr + I82544_TCTL );
|
1741 |
|
|
txctl &= ~I82544_TCTL_EN;
|
1742 |
|
|
OUTL( txctl, ioaddr + I82544_TCTL );
|
1743 |
|
|
|
1744 |
|
|
}
|
1745 |
|
|
|
1746 |
|
|
|
1747 |
|
|
// ------------------------------------------------------------------------
|
1748 |
|
|
//
|
1749 |
|
|
// Function : InitRxRing
|
1750 |
|
|
//
|
1751 |
|
|
// ------------------------------------------------------------------------
|
1752 |
|
|
|
1753 |
|
|
static void
|
1754 |
|
|
InitRxRing(struct i82544* p_i82544)
|
1755 |
|
|
{
|
1756 |
|
|
int i;
|
1757 |
|
|
CYG_ADDRESS rxring;
|
1758 |
|
|
cyg_uint32 ioaddr = p_i82544->io_address;
|
1759 |
|
|
cyg_uint32 rxctl;
|
1760 |
|
|
|
1761 |
|
|
#ifdef DEBUG_82544
|
1762 |
|
|
os_printf("InitRxRing %d\n", p_i82544->index);
|
1763 |
|
|
#endif
|
1764 |
|
|
|
1765 |
|
|
// Allocate array of Rx desriptors
|
1766 |
|
|
rxring = pciwindow_mem_alloc(
|
1767 |
|
|
MAX_RX_DESCRIPTORS * I82544_RD_SIZE + 32 );
|
1768 |
|
|
|
1769 |
|
|
// assign ring structure, aligning it on a 16 byte boudary.
|
1770 |
|
|
p_i82544->rx_ring = (rxring + 15) & ~15;
|
1771 |
|
|
|
1772 |
|
|
// Allocate and fill in buffer pointers
|
1773 |
|
|
for ( i = 0; i < MAX_RX_DESCRIPTORS; i++) {
|
1774 |
|
|
CYG_ADDRESS rd = p_i82544->rx_ring + (i*I82544_RD_SIZE);
|
1775 |
|
|
CYG_ADDRESS buf = pciwindow_mem_alloc(MAX_RX_PACKET_SIZE);
|
1776 |
|
|
WRITEMEM64( rd + I82544_RD_BUFFER, VIRT_TO_BUS(buf) );
|
1777 |
|
|
}
|
1778 |
|
|
|
1779 |
|
|
// Set the receiver queue registers
|
1780 |
|
|
|
1781 |
|
|
OUTL( VIRT_TO_BUS(p_i82544->rx_ring), ioaddr + I82544_RDBAL );
|
1782 |
|
|
OUTL( 0, ioaddr + I82544_RDBAH );
|
1783 |
|
|
OUTL( MAX_RX_DESCRIPTORS * I82544_RD_SIZE, ioaddr + I82544_RDLEN );
|
1784 |
|
|
OUTL( 0, ioaddr + I82544_RDH );
|
1785 |
|
|
OUTL( MAX_RX_DESCRIPTORS - 5, ioaddr + I82544_RDT );
|
1786 |
|
|
|
1787 |
|
|
// zero out RAT
|
1788 |
|
|
|
1789 |
|
|
for( i = 0; i < 32; i++ )
|
1790 |
|
|
OUTL( 0, ioaddr + I82544_RAT +(i*4) );
|
1791 |
|
|
|
1792 |
|
|
// Zero out MTA
|
1793 |
|
|
for( i = 0; i < 128; i++ )
|
1794 |
|
|
OUTL( 0, ioaddr + I82544_MTA +(i*4) );
|
1795 |
|
|
|
1796 |
|
|
// Set up receiver to accept broadcasts
|
1797 |
|
|
rxctl = INL( ioaddr + I82544_RCTL );
|
1798 |
|
|
rxctl |= I82544_RCTL_BAM;
|
1799 |
|
|
OUTL( rxctl, ioaddr + I82544_RCTL );
|
1800 |
|
|
|
1801 |
|
|
#ifdef DEBUG_82544
|
1802 |
|
|
os_printf("RCTL %08x\n",rxctl);
|
1803 |
|
|
#endif
|
1804 |
|
|
|
1805 |
|
|
p_i82544->next_rx_descriptor = 0;
|
1806 |
|
|
p_i82544->rx_pointer = 0;
|
1807 |
|
|
}
|
1808 |
|
|
|
1809 |
|
|
// ------------------------------------------------------------------------
|
1810 |
|
|
//
|
1811 |
|
|
// Function : PacketRxReady (Called from delivery thread & foreground)
|
1812 |
|
|
//
|
1813 |
|
|
// ------------------------------------------------------------------------
|
1814 |
|
|
|
1815 |
|
|
static void
|
1816 |
|
|
PacketRxReady(struct i82544* p_i82544)
|
1817 |
|
|
{
|
1818 |
|
|
struct cyg_netdevtab_entry *ndp;
|
1819 |
|
|
struct eth_drv_sc *sc;
|
1820 |
|
|
cyg_int32 rxp;
|
1821 |
|
|
cyg_uint32 ioaddr;
|
1822 |
|
|
|
1823 |
|
|
#ifdef DEBUG_82544
|
1824 |
|
|
// db_printf("PacketRxReady\n");
|
1825 |
|
|
#endif
|
1826 |
|
|
|
1827 |
|
|
ndp = (struct cyg_netdevtab_entry *)(p_i82544->ndp);
|
1828 |
|
|
sc = (struct eth_drv_sc *)(ndp->device_instance);
|
1829 |
|
|
|
1830 |
|
|
CHECK_NDP_SC_LINK();
|
1831 |
|
|
|
1832 |
|
|
ioaddr = p_i82544->io_address;
|
1833 |
|
|
|
1834 |
|
|
|
1835 |
|
|
rxp = p_i82544->rx_pointer;
|
1836 |
|
|
|
1837 |
|
|
for(;;)
|
1838 |
|
|
{
|
1839 |
|
|
cyg_int32 rxh, rxt;
|
1840 |
|
|
CYG_ADDRESS dp;
|
1841 |
|
|
cyg_uint8 status;
|
1842 |
|
|
|
1843 |
|
|
rxh = INL( ioaddr + I82544_RDH );
|
1844 |
|
|
|
1845 |
|
|
#if 0 //def DEBUG_82544
|
1846 |
|
|
os_printf("rxp %04d rxh %04x\n",rxp,rxh);
|
1847 |
|
|
#endif
|
1848 |
|
|
|
1849 |
|
|
// If the head pointer has not advanced, there have been no
|
1850 |
|
|
// packets received.
|
1851 |
|
|
if( rxh == rxp )
|
1852 |
|
|
break;
|
1853 |
|
|
|
1854 |
|
|
// Form packet address
|
1855 |
|
|
dp = p_i82544->rx_ring + (rxp * I82544_RD_SIZE);
|
1856 |
|
|
|
1857 |
|
|
// Get status
|
1858 |
|
|
READMEM8( dp + I82544_RD_STATUS, status );
|
1859 |
|
|
|
1860 |
|
|
#if 0 //def DEBUG_82544
|
1861 |
|
|
{
|
1862 |
|
|
cyg_uint16 length;
|
1863 |
|
|
READMEM16( dp + I82544_RD_LENGTH, length );
|
1864 |
|
|
os_printf("rxp %04d status %02x length %d\n",rxp,status,length);
|
1865 |
|
|
}
|
1866 |
|
|
#endif
|
1867 |
|
|
|
1868 |
|
|
if( status & I82544_RD_STATUS_EOP )
|
1869 |
|
|
{
|
1870 |
|
|
cyg_uint16 length;
|
1871 |
|
|
|
1872 |
|
|
READMEM16( dp + I82544_RD_LENGTH, length );
|
1873 |
|
|
|
1874 |
|
|
#ifdef DEBUG_82544
|
1875 |
|
|
os_printf("rxp %04d length %d\n",rxp,length);
|
1876 |
|
|
#endif
|
1877 |
|
|
CYG_ASSERT( MAX_RX_PACKET_SIZE >= length, "Oversize Rx" );
|
1878 |
|
|
|
1879 |
|
|
// tell the callback the right packet
|
1880 |
|
|
p_i82544->next_rx_descriptor = rxp;
|
1881 |
|
|
|
1882 |
|
|
#ifdef CYGPKG_NET
|
1883 |
|
|
if ( length > sizeof( struct ether_header ) )
|
1884 |
|
|
// then it is acceptable; offer the data to the network stack
|
1885 |
|
|
#endif
|
1886 |
|
|
(sc->funs->eth_drv->recv)( sc, length );
|
1887 |
|
|
|
1888 |
|
|
// All done!
|
1889 |
|
|
}
|
1890 |
|
|
|
1891 |
|
|
// Advance rxp pointer
|
1892 |
|
|
rxp = ( rxp + 1 ) % MAX_RX_DESCRIPTORS;
|
1893 |
|
|
|
1894 |
|
|
// We can now also advance the tail pointer by 1
|
1895 |
|
|
rxt = INL( ioaddr + I82544_RDT );
|
1896 |
|
|
dp = p_i82544->rx_ring + (rxt * I82544_RD_SIZE);
|
1897 |
|
|
WRITEMEM8( dp + I82544_RD_STATUS, status );
|
1898 |
|
|
rxt = ( rxt + 1 ) % MAX_RX_DESCRIPTORS;
|
1899 |
|
|
OUTL( rxt, ioaddr + I82544_RDT );
|
1900 |
|
|
|
1901 |
|
|
#ifdef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
|
1902 |
|
|
// Can't deliver more than one packet in polled standalone mode
|
1903 |
|
|
break;
|
1904 |
|
|
#endif
|
1905 |
|
|
}
|
1906 |
|
|
|
1907 |
|
|
// Save next rx pointer for next time.
|
1908 |
|
|
p_i82544->rx_pointer = rxp;
|
1909 |
|
|
|
1910 |
|
|
}
|
1911 |
|
|
|
1912 |
|
|
// and the callback function
|
1913 |
|
|
|
1914 |
|
|
static void
|
1915 |
|
|
i82544_recv( struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len )
|
1916 |
|
|
{
|
1917 |
|
|
struct i82544 *p_i82544;
|
1918 |
|
|
cyg_int32 rxp;
|
1919 |
|
|
CYG_ADDRESS dp;
|
1920 |
|
|
CYG_ADDRESS from_p;
|
1921 |
|
|
cyg_uint16 total_len;
|
1922 |
|
|
struct eth_drv_sg *last_sg;
|
1923 |
|
|
|
1924 |
|
|
#ifdef DEBUG_82544
|
1925 |
|
|
db_printf("i82544_recv\n");
|
1926 |
|
|
#endif
|
1927 |
|
|
|
1928 |
|
|
p_i82544 = (struct i82544 *)sc->driver_private;
|
1929 |
|
|
|
1930 |
|
|
IF_BAD_82544( p_i82544 ) {
|
1931 |
|
|
#ifdef DEBUG_82544
|
1932 |
|
|
os_printf( "i82544_recv: Bad device pointer %x\n", p_i82544 );
|
1933 |
|
|
#endif
|
1934 |
|
|
return;
|
1935 |
|
|
}
|
1936 |
|
|
|
1937 |
|
|
rxp = p_i82544->next_rx_descriptor;
|
1938 |
|
|
// Form packet address
|
1939 |
|
|
dp = p_i82544->rx_ring + (rxp * I82544_RD_SIZE);
|
1940 |
|
|
|
1941 |
|
|
#if 0 //def DEBUG_82544
|
1942 |
|
|
{
|
1943 |
|
|
int i;
|
1944 |
|
|
os_printf("RxD %08x",dp);
|
1945 |
|
|
for( i = 0; i < 16; i++ )
|
1946 |
|
|
{
|
1947 |
|
|
cyg_uint8 b;
|
1948 |
|
|
if( (i%8) == 0 ) os_printf("\n");
|
1949 |
|
|
READMEM8( dp + i, b );
|
1950 |
|
|
os_printf("%02x ",b);
|
1951 |
|
|
}
|
1952 |
|
|
os_printf("\n");
|
1953 |
|
|
}
|
1954 |
|
|
#endif
|
1955 |
|
|
// Copy the data to the network stack
|
1956 |
|
|
READMEM64( dp + I82544_RD_BUFFER, from_p );
|
1957 |
|
|
from_p = BUS_TO_VIRT(from_p);
|
1958 |
|
|
READMEM16( dp + I82544_RD_LENGTH, total_len );
|
1959 |
|
|
|
1960 |
|
|
#ifdef DEBUG_82544
|
1961 |
|
|
db_printf("RXP: %04x len %d\n",rxp,total_len);
|
1962 |
|
|
#endif
|
1963 |
|
|
|
1964 |
|
|
// check we have memory to copy into; we would be called even if
|
1965 |
|
|
// caller was out of memory in order to maintain our state.
|
1966 |
|
|
if ( 0 == sg_len || 0 == sg_list )
|
1967 |
|
|
return; // caller was out of mbufs
|
1968 |
|
|
|
1969 |
|
|
CYG_ASSERT( 0 < sg_len, "sg_len underflow" );
|
1970 |
|
|
CYG_ASSERT( MAX_ETH_DRV_SG >= sg_len, "sg_len overflow" );
|
1971 |
|
|
|
1972 |
|
|
for ( last_sg = &sg_list[sg_len]; sg_list < last_sg; sg_list++ ) {
|
1973 |
|
|
cyg_uint8 *to_p;
|
1974 |
|
|
int l;
|
1975 |
|
|
|
1976 |
|
|
to_p = (cyg_uint8 *)(sg_list->buf);
|
1977 |
|
|
l = sg_list->len;
|
1978 |
|
|
|
1979 |
|
|
CYG_ASSERT( 0 <= l, "sg length -ve" );
|
1980 |
|
|
|
1981 |
|
|
if ( 0 >= l || 0 == to_p )
|
1982 |
|
|
return; // caller was out of mbufs
|
1983 |
|
|
|
1984 |
|
|
if ( l > total_len )
|
1985 |
|
|
l = total_len;
|
1986 |
|
|
|
1987 |
|
|
#if 0 //def DEBUG_82544
|
1988 |
|
|
{
|
1989 |
|
|
int i,ll = l;
|
1990 |
|
|
os_printf("Pkt len %d",l);
|
1991 |
|
|
if( ll > 32 ) ll = 32;
|
1992 |
|
|
for( i = 0; i < ll; i++ )
|
1993 |
|
|
{
|
1994 |
|
|
cyg_uint8 b;
|
1995 |
|
|
if( (i%8) == 0 ) os_printf("\n %04x: ",i);
|
1996 |
|
|
b = ((cyg_uint8 *)from_p)[i];
|
1997 |
|
|
os_printf("%02x ",b);
|
1998 |
|
|
}
|
1999 |
|
|
os_printf("\n");
|
2000 |
|
|
|
2001 |
|
|
}
|
2002 |
|
|
#endif
|
2003 |
|
|
memcpy( to_p, (unsigned char *)from_p, l );
|
2004 |
|
|
from_p += l;
|
2005 |
|
|
total_len -= l;
|
2006 |
|
|
}
|
2007 |
|
|
|
2008 |
|
|
CYG_ASSERT( 0 == total_len, "total_len mismatch in rx" );
|
2009 |
|
|
CYG_ASSERT( last_sg == sg_list, "sg count mismatch in rx" );
|
2010 |
|
|
|
2011 |
|
|
}
|
2012 |
|
|
|
2013 |
|
|
|
2014 |
|
|
// ------------------------------------------------------------------------
|
2015 |
|
|
//
|
2016 |
|
|
// Function : InitTxRing
|
2017 |
|
|
//
|
2018 |
|
|
// ------------------------------------------------------------------------
|
2019 |
|
|
|
2020 |
|
|
static void
|
2021 |
|
|
InitTxRing(struct i82544* p_i82544)
|
2022 |
|
|
{
|
2023 |
|
|
int i;
|
2024 |
|
|
cyg_uint32 ioaddr = p_i82544->io_address;
|
2025 |
|
|
CYG_ADDRESS txring;
|
2026 |
|
|
cyg_uint32 txctl;
|
2027 |
|
|
|
2028 |
|
|
#ifdef DEBUG_82544
|
2029 |
|
|
os_printf("InitTxRing %d\n", p_i82544->index);
|
2030 |
|
|
#endif
|
2031 |
|
|
|
2032 |
|
|
// Allocate array of Tx desriptors
|
2033 |
|
|
txring = pciwindow_mem_alloc(
|
2034 |
|
|
MAX_TX_DESCRIPTORS * I82544_TD_SIZE + 32 );
|
2035 |
|
|
|
2036 |
|
|
// assign ring structure, aligning it on a 16 byte boudary.
|
2037 |
|
|
p_i82544->tx_ring = (txring + 15) & ~15;
|
2038 |
|
|
|
2039 |
|
|
// Allocate and fill in buffer pointers
|
2040 |
|
|
for ( i = 0; i < MAX_TX_DESCRIPTORS; i++) {
|
2041 |
|
|
CYG_ADDRESS td = p_i82544->tx_ring + (i*I82544_TD_SIZE);
|
2042 |
|
|
WRITEMEM64( td + I82544_TD_BUFFER, 0 );
|
2043 |
|
|
}
|
2044 |
|
|
|
2045 |
|
|
// Set the transmitter queue registers
|
2046 |
|
|
|
2047 |
|
|
OUTL( VIRT_TO_BUS(p_i82544->tx_ring), ioaddr + I82544_TDBAL );
|
2048 |
|
|
OUTL( 0, ioaddr + I82544_TDBAH );
|
2049 |
|
|
OUTL( MAX_TX_DESCRIPTORS * I82544_TD_SIZE, ioaddr + I82544_TDLEN );
|
2050 |
|
|
OUTL( 0, ioaddr + I82544_TDH );
|
2051 |
|
|
OUTL( 0, ioaddr + I82544_TDT );
|
2052 |
|
|
|
2053 |
|
|
// Set IPG values
|
2054 |
|
|
OUTL( 8 | (8<<10) | (6<<20), ioaddr + I82544_TIPG );
|
2055 |
|
|
|
2056 |
|
|
// Program tx ctrl register
|
2057 |
|
|
txctl = INL( ioaddr + I82544_TCTL );
|
2058 |
|
|
txctl |= (15<<4); // collision threshold
|
2059 |
|
|
txctl |= (64<<12); // collision distance
|
2060 |
|
|
txctl |= I82544_TCTL_PSP;
|
2061 |
|
|
OUTL( txctl, ioaddr + I82544_TCTL );
|
2062 |
|
|
|
2063 |
|
|
p_i82544->tx_in_progress = 0;
|
2064 |
|
|
p_i82544->tx_pointer = 0;
|
2065 |
|
|
|
2066 |
|
|
}
|
2067 |
|
|
|
2068 |
|
|
// ------------------------------------------------------------------------
|
2069 |
|
|
//
|
2070 |
|
|
// Function : TxDone (Called from delivery thread)
|
2071 |
|
|
//
|
2072 |
|
|
// This returns Tx's from the Tx Machine to the stack (ie. reports
|
2073 |
|
|
// completion) - allowing for missed interrupts, and so on.
|
2074 |
|
|
// ------------------------------------------------------------------------
|
2075 |
|
|
|
2076 |
|
|
static void
|
2077 |
|
|
TxDone(struct i82544* p_i82544)
|
2078 |
|
|
{
|
2079 |
|
|
struct cyg_netdevtab_entry *ndp;
|
2080 |
|
|
struct eth_drv_sc *sc;
|
2081 |
|
|
cyg_uint32 ioaddr;
|
2082 |
|
|
cyg_int32 txp = p_i82544->tx_pointer;
|
2083 |
|
|
|
2084 |
|
|
#ifdef DEBUG_82544
|
2085 |
|
|
// db_printf("TxDone\n");
|
2086 |
|
|
#endif
|
2087 |
|
|
|
2088 |
|
|
ndp = (struct cyg_netdevtab_entry *)(p_i82544->ndp);
|
2089 |
|
|
sc = (struct eth_drv_sc *)(ndp->device_instance);
|
2090 |
|
|
|
2091 |
|
|
CHECK_NDP_SC_LINK();
|
2092 |
|
|
|
2093 |
|
|
ioaddr = p_i82544->io_address; // get device I/O address
|
2094 |
|
|
|
2095 |
|
|
if( !p_i82544->active )
|
2096 |
|
|
return;
|
2097 |
|
|
|
2098 |
|
|
for(;;)
|
2099 |
|
|
{
|
2100 |
|
|
cyg_uint8 status;
|
2101 |
|
|
cyg_uint8 cmd;
|
2102 |
|
|
CYG_ADDRESS dp;
|
2103 |
|
|
cyg_int32 txh;
|
2104 |
|
|
|
2105 |
|
|
txh = INL( ioaddr + I82544_TDH );
|
2106 |
|
|
|
2107 |
|
|
// If there has been no advance on the transmit header,
|
2108 |
|
|
// nothing to do.
|
2109 |
|
|
if( txh == txp )
|
2110 |
|
|
break;
|
2111 |
|
|
|
2112 |
|
|
#ifdef DEBUG_82544
|
2113 |
|
|
os_printf("TxDone: TxH %04d TxP %04d\n",txh,txp);
|
2114 |
|
|
#endif
|
2115 |
|
|
|
2116 |
|
|
// Get descriptor address
|
2117 |
|
|
dp = p_i82544->tx_ring + (txp * I82544_TD_SIZE);
|
2118 |
|
|
|
2119 |
|
|
READMEM8( dp + I82544_TD_CMD, cmd );
|
2120 |
|
|
READMEM8( dp + I82544_TD_STATUS, status );
|
2121 |
|
|
#ifdef DEBUG_82544
|
2122 |
|
|
os_printf("cmd %02x status %02x\n",cmd,status);
|
2123 |
|
|
#endif
|
2124 |
|
|
|
2125 |
|
|
// Zero out buffer and command
|
2126 |
|
|
WRITEMEM64( dp + I82544_TD_BUFFER, 0 );
|
2127 |
|
|
WRITEMEM8( dp + I82544_TD_CMD, 0 );
|
2128 |
|
|
|
2129 |
|
|
if( cmd & I82544_TD_CMD_EOP )
|
2130 |
|
|
{
|
2131 |
|
|
// A done end of packet descrptor
|
2132 |
|
|
|
2133 |
|
|
if( p_i82544->tx_keys[txp] != 0 )
|
2134 |
|
|
{
|
2135 |
|
|
// Call network stack with correct value of txp in structure.
|
2136 |
|
|
// There may be recursive calls in here, so we need to make sure
|
2137 |
|
|
// that txp is updated correctly.
|
2138 |
|
|
p_i82544->tx_pointer = ( txp + 1 ) % MAX_TX_DESCRIPTORS;
|
2139 |
|
|
(sc->funs->eth_drv->tx_done)( sc, p_i82544->tx_keys[txp], 0 );
|
2140 |
|
|
txp = p_i82544->tx_pointer;
|
2141 |
|
|
continue;
|
2142 |
|
|
}
|
2143 |
|
|
}
|
2144 |
|
|
|
2145 |
|
|
// Advance tx pointer
|
2146 |
|
|
txp = ( txp + 1 ) % MAX_TX_DESCRIPTORS;
|
2147 |
|
|
|
2148 |
|
|
}
|
2149 |
|
|
|
2150 |
|
|
// restore txp to data structure.
|
2151 |
|
|
p_i82544->tx_pointer = txp;
|
2152 |
|
|
|
2153 |
|
|
}
|
2154 |
|
|
|
2155 |
|
|
|
2156 |
|
|
static cyg_bool
|
2157 |
|
|
check_link(struct i82544 *p_i82544)
|
2158 |
|
|
{
|
2159 |
|
|
if ( p_i82544->link == 0 )
|
2160 |
|
|
{
|
2161 |
|
|
cyg_uint16 phy_pssr;
|
2162 |
|
|
cyg_uint16 phy_stat;
|
2163 |
|
|
|
2164 |
|
|
phy_stat = mii_read_register( p_i82544, PHY_ADDRESS, 1 );
|
2165 |
|
|
if (phy_stat & 0x20)
|
2166 |
|
|
{
|
2167 |
|
|
cyg_uint32 ioaddr;
|
2168 |
|
|
cyg_uint32 ctrl;
|
2169 |
|
|
|
2170 |
|
|
p_i82544->link = 1;
|
2171 |
|
|
|
2172 |
|
|
ioaddr = p_i82544->io_address; // get device I/O address
|
2173 |
|
|
|
2174 |
|
|
phy_pssr = mii_read_register( p_i82544, PHY_ADDRESS, 17 );
|
2175 |
|
|
|
2176 |
|
|
ctrl = INL( ioaddr + I82544_CTRL );
|
2177 |
|
|
ctrl &= ~(I82544_CTRL_SPEED | I82544_CTRL_FD);
|
2178 |
|
|
if( phy_pssr & (1<<13) )
|
2179 |
|
|
ctrl |= I82544_CTRL_FD;
|
2180 |
|
|
|
2181 |
|
|
// Transfer speed
|
2182 |
|
|
ctrl |= ((phy_pssr>>14)&3)<<8;
|
2183 |
|
|
ctrl |= I82544_CTRL_FRCDPLX | I82544_CTRL_FRCSPD;
|
2184 |
|
|
|
2185 |
|
|
OUTL( ctrl, ioaddr + I82544_CTRL );
|
2186 |
|
|
}
|
2187 |
|
|
}
|
2188 |
|
|
|
2189 |
|
|
return p_i82544->link == 1;
|
2190 |
|
|
}
|
2191 |
|
|
|
2192 |
|
|
|
2193 |
|
|
// ------------------------------------------------------------------------
|
2194 |
|
|
//
|
2195 |
|
|
// Function : i82544_can_send
|
2196 |
|
|
//
|
2197 |
|
|
// ------------------------------------------------------------------------
|
2198 |
|
|
|
2199 |
|
|
static int
|
2200 |
|
|
i82544_can_send(struct eth_drv_sc *sc)
|
2201 |
|
|
{
|
2202 |
|
|
struct i82544 *p_i82544;
|
2203 |
|
|
cyg_uint32 ioaddr;
|
2204 |
|
|
|
2205 |
|
|
#ifdef DEBUG_82544
|
2206 |
|
|
// db_printf("i82544_can_send\n");
|
2207 |
|
|
#endif
|
2208 |
|
|
|
2209 |
|
|
p_i82544 = (struct i82544 *)sc->driver_private;
|
2210 |
|
|
|
2211 |
|
|
IF_BAD_82544( p_i82544 ) {
|
2212 |
|
|
#ifdef DEBUG_82544
|
2213 |
|
|
os_printf( "i82544_send: Bad device pointer %x\n", p_i82544 );
|
2214 |
|
|
#endif
|
2215 |
|
|
return 0;
|
2216 |
|
|
}
|
2217 |
|
|
|
2218 |
|
|
ioaddr = p_i82544->io_address; // get device I/O address
|
2219 |
|
|
|
2220 |
|
|
if ( p_i82544->active )
|
2221 |
|
|
{
|
2222 |
|
|
cyg_int32 txh, txt, diff;
|
2223 |
|
|
|
2224 |
|
|
|
2225 |
|
|
if (!check_link(p_i82544))
|
2226 |
|
|
return 0;
|
2227 |
|
|
|
2228 |
|
|
// Poll for Tx completion
|
2229 |
|
|
TxDone( p_i82544 );
|
2230 |
|
|
|
2231 |
|
|
#ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
|
2232 |
|
|
// We are not prepared to receive a packet now if we are in a polled
|
2233 |
|
|
// standalone configuration.
|
2234 |
|
|
|
2235 |
|
|
// Poll for receptions
|
2236 |
|
|
PacketRxReady( p_i82544 );
|
2237 |
|
|
#endif
|
2238 |
|
|
|
2239 |
|
|
// Now see whether the Tx queue has space for another
|
2240 |
|
|
// transmit. We look at the difference between the head and
|
2241 |
|
|
// tail pointer, and if there is space for at least 5 more
|
2242 |
|
|
// descriptors, we allow a new transmission to go ahead.
|
2243 |
|
|
txh = INL( ioaddr + I82544_TDH );
|
2244 |
|
|
txt = INL( ioaddr + I82544_TDT );
|
2245 |
|
|
|
2246 |
|
|
diff = (txh-1) - txt;
|
2247 |
|
|
if( diff < 0 ) diff += MAX_TX_DESCRIPTORS;
|
2248 |
|
|
#ifdef DEBUG_82544
|
2249 |
|
|
// os_printf("TxH %04d TxT %04d diff %04d\n",txh,txt,diff);
|
2250 |
|
|
#endif
|
2251 |
|
|
return diff > 5;
|
2252 |
|
|
}
|
2253 |
|
|
|
2254 |
|
|
return false;
|
2255 |
|
|
|
2256 |
|
|
}
|
2257 |
|
|
|
2258 |
|
|
// ------------------------------------------------------------------------
|
2259 |
|
|
//
|
2260 |
|
|
// Function : i82544_send
|
2261 |
|
|
//
|
2262 |
|
|
// ------------------------------------------------------------------------
|
2263 |
|
|
|
2264 |
|
|
static void
|
2265 |
|
|
i82544_send(struct eth_drv_sc *sc,
|
2266 |
|
|
struct eth_drv_sg *sg_list, int sg_len, int total_len,
|
2267 |
|
|
unsigned long key)
|
2268 |
|
|
{
|
2269 |
|
|
struct i82544 *p_i82544;
|
2270 |
|
|
cyg_uint32 ioaddr;
|
2271 |
|
|
struct eth_drv_sg *last_sg;
|
2272 |
|
|
cyg_int32 txt;
|
2273 |
|
|
|
2274 |
|
|
|
2275 |
|
|
#ifdef DEBUG_82544
|
2276 |
|
|
db_printf("i82544_send\n");
|
2277 |
|
|
#endif
|
2278 |
|
|
|
2279 |
|
|
p_i82544 = (struct i82544 *)sc->driver_private;
|
2280 |
|
|
|
2281 |
|
|
IF_BAD_82544( p_i82544 ) {
|
2282 |
|
|
#ifdef DEBUG_82544
|
2283 |
|
|
os_printf( "i82544_send: Bad device pointer %x\n", p_i82544 );
|
2284 |
|
|
#endif
|
2285 |
|
|
return;
|
2286 |
|
|
}
|
2287 |
|
|
|
2288 |
|
|
#ifdef DEBUG_82544
|
2289 |
|
|
os_printf("Tx %d %x: %d sg's, %d bytes, KEY %x\n",
|
2290 |
|
|
p_i82544->index, (int)p_i82544, sg_len, total_len, key );
|
2291 |
|
|
#endif
|
2292 |
|
|
|
2293 |
|
|
if ( ! p_i82544->active )
|
2294 |
|
|
return; // device inactive, no return
|
2295 |
|
|
ioaddr = p_i82544->io_address; // get device I/O address
|
2296 |
|
|
|
2297 |
|
|
// Get the tx tail pointer
|
2298 |
|
|
txt = INL( ioaddr + I82544_TDT );
|
2299 |
|
|
|
2300 |
|
|
for ( last_sg = &sg_list[sg_len]; sg_list < last_sg; sg_list++ )
|
2301 |
|
|
{
|
2302 |
|
|
cyg_uint8 *from_p;
|
2303 |
|
|
cyg_uint8 cmd = 0;
|
2304 |
|
|
CYG_ADDRESS dp;
|
2305 |
|
|
int l;
|
2306 |
|
|
|
2307 |
|
|
from_p = (cyg_uint8 *)(sg_list->buf); // normal cached address
|
2308 |
|
|
l = sg_list->len;
|
2309 |
|
|
|
2310 |
|
|
if ( l > total_len )
|
2311 |
|
|
l = total_len;
|
2312 |
|
|
|
2313 |
|
|
// Get the descriptor address from the tail pointer.
|
2314 |
|
|
dp = p_i82544->tx_ring + (txt * I82544_TD_SIZE);
|
2315 |
|
|
|
2316 |
|
|
total_len -= l;
|
2317 |
|
|
|
2318 |
|
|
#ifdef HAL_DCACHE_STORE
|
2319 |
|
|
HAL_DCACHE_STORE( ((CYG_ADDRESS)from_p) &~(HAL_DCACHE_LINE_SIZE-1),
|
2320 |
|
|
l + (HAL_DCACHE_LINE_SIZE-1) );
|
2321 |
|
|
#endif
|
2322 |
|
|
|
2323 |
|
|
WRITEMEM64( dp + I82544_TD_BUFFER, VIRT_TO_BUS(from_p) );
|
2324 |
|
|
WRITEMEM16( dp + I82544_TD_LENGTH, l );
|
2325 |
|
|
|
2326 |
|
|
// Set EOP bit on last packet
|
2327 |
|
|
if( total_len <= 0 )
|
2328 |
|
|
cmd |= I82544_TD_CMD_EOP;
|
2329 |
|
|
|
2330 |
|
|
// Get status back
|
2331 |
|
|
// cmd |= I82544_TD_CMD_RPS | I82544_TD_CMD_RS;
|
2332 |
|
|
|
2333 |
|
|
cmd |= I82544_TD_CMD_IFCS;
|
2334 |
|
|
|
2335 |
|
|
// Write command byte
|
2336 |
|
|
WRITEMEM8( dp + I82544_TD_CMD, cmd );
|
2337 |
|
|
|
2338 |
|
|
// Zero out rest of fields
|
2339 |
|
|
WRITEMEM8( dp + I82544_TD_STATUS, 0 );
|
2340 |
|
|
WRITEMEM8( dp + I82544_TD_CSO, 0 );
|
2341 |
|
|
WRITEMEM8( dp + I82544_TD_CSS, 0 );
|
2342 |
|
|
WRITEMEM16( dp + I82544_TD_SPECIAL, 0 );
|
2343 |
|
|
|
2344 |
|
|
// Store the key for this transmission in the matching slot
|
2345 |
|
|
// for the descriptor.
|
2346 |
|
|
p_i82544->tx_keys[txt] = key;
|
2347 |
|
|
|
2348 |
|
|
// Increment tx tail pointer
|
2349 |
|
|
txt = (txt + 1) % MAX_TX_DESCRIPTORS;
|
2350 |
|
|
|
2351 |
|
|
}
|
2352 |
|
|
|
2353 |
|
|
// And finally, cause the transmission to happen by setting the
|
2354 |
|
|
// tail pointer in the hardware.
|
2355 |
|
|
OUTL( txt, ioaddr + I82544_TDT );
|
2356 |
|
|
|
2357 |
|
|
}
|
2358 |
|
|
|
2359 |
|
|
// ------------------------------------------------------------------------
|
2360 |
|
|
//
|
2361 |
|
|
// Function : i82544_reset
|
2362 |
|
|
//
|
2363 |
|
|
// ------------------------------------------------------------------------
|
2364 |
|
|
static void
|
2365 |
|
|
i82544_reset(struct i82544* p_i82544)
|
2366 |
|
|
{
|
2367 |
|
|
cyg_uint32 ioaddr = p_i82544->io_address;
|
2368 |
|
|
cyg_uint32 ctrl;
|
2369 |
|
|
|
2370 |
|
|
#ifdef DEBUG
|
2371 |
|
|
db_printf("i82544_reset\n");
|
2372 |
|
|
#endif
|
2373 |
|
|
|
2374 |
|
|
ctrl = INL( ioaddr + I82544_CTRL );
|
2375 |
|
|
|
2376 |
|
|
// reset controller
|
2377 |
|
|
OUTL( ctrl | I82544_CTRL_RST, ioaddr + I82544_CTRL );
|
2378 |
|
|
udelay(20);
|
2379 |
|
|
ctrl = INL( ioaddr + I82544_CTRL );
|
2380 |
|
|
|
2381 |
|
|
}
|
2382 |
|
|
|
2383 |
|
|
// ------------------------------------------------------------------------
|
2384 |
|
|
//
|
2385 |
|
|
// INTERRUPT HANDLERS
|
2386 |
|
|
//
|
2387 |
|
|
// ------------------------------------------------------------------------
|
2388 |
|
|
|
2389 |
|
|
static cyg_uint32
|
2390 |
|
|
eth_isr(cyg_vector_t vector, cyg_addrword_t data)
|
2391 |
|
|
{
|
2392 |
|
|
struct i82544* p_i82544 = (struct i82544 *)data;
|
2393 |
|
|
cyg_uint16 status;
|
2394 |
|
|
cyg_uint32 ioaddr;
|
2395 |
|
|
|
2396 |
|
|
#ifdef DEBUG_82544
|
2397 |
|
|
// db_printf("eth_isr\n");
|
2398 |
|
|
#endif
|
2399 |
|
|
|
2400 |
|
|
IF_BAD_82544( p_i82544 ) {
|
2401 |
|
|
#ifdef DEBUG_82544
|
2402 |
|
|
os_printf( "i82544_isr: Bad device pointer %x\n", p_i82544 );
|
2403 |
|
|
#endif
|
2404 |
|
|
return 0;
|
2405 |
|
|
}
|
2406 |
|
|
|
2407 |
|
|
ioaddr = p_i82544->io_address;
|
2408 |
|
|
|
2409 |
|
|
status = INL( ioaddr + I82544_ICR );
|
2410 |
|
|
|
2411 |
|
|
#ifdef DEBUG_82544
|
2412 |
|
|
db_printf("eth_isr %04x\n",status);
|
2413 |
|
|
#endif
|
2414 |
|
|
|
2415 |
|
|
return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // schedule DSR
|
2416 |
|
|
}
|
2417 |
|
|
|
2418 |
|
|
|
2419 |
|
|
// ------------------------------------------------------------------------
|
2420 |
|
|
|
2421 |
|
|
#ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
|
2422 |
|
|
static void
|
2423 |
|
|
eth_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
|
2424 |
|
|
{
|
2425 |
|
|
struct i82544* p_i82544 = (struct i82544 *)data;
|
2426 |
|
|
struct cyg_netdevtab_entry *ndp =
|
2427 |
|
|
(struct cyg_netdevtab_entry *)(p_i82544->ndp);
|
2428 |
|
|
struct eth_drv_sc *sc = (struct eth_drv_sc *)(ndp->device_instance);
|
2429 |
|
|
|
2430 |
|
|
#ifdef DEBUG_82544
|
2431 |
|
|
db_printf("eth_dsr\n");
|
2432 |
|
|
#endif
|
2433 |
|
|
|
2434 |
|
|
eth_drv_dsr( vector, count, (cyg_addrword_t)sc );
|
2435 |
|
|
|
2436 |
|
|
cyg_drv_interrupt_acknowledge(p_i82544->vector);
|
2437 |
|
|
}
|
2438 |
|
|
#endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
|
2439 |
|
|
|
2440 |
|
|
// ------------------------------------------------------------------------
|
2441 |
|
|
// Deliver routine:
|
2442 |
|
|
|
2443 |
|
|
void
|
2444 |
|
|
i82544_deliver(struct eth_drv_sc *sc)
|
2445 |
|
|
{
|
2446 |
|
|
struct i82544* p_i82544 = (struct i82544 *)(sc->driver_private);
|
2447 |
|
|
|
2448 |
|
|
#ifdef DEBUG
|
2449 |
|
|
db_printf("i82544_deliver\n");
|
2450 |
|
|
#endif
|
2451 |
|
|
|
2452 |
|
|
// First pass any rx data up the stack
|
2453 |
|
|
PacketRxReady(p_i82544);
|
2454 |
|
|
|
2455 |
|
|
// Then scan for completed Tx and inform the stack
|
2456 |
|
|
TxDone(p_i82544);
|
2457 |
|
|
}
|
2458 |
|
|
|
2459 |
|
|
// ------------------------------------------------------------------------
|
2460 |
|
|
// Device table entry to operate the chip in a polled mode.
|
2461 |
|
|
// Only diddle the interface we were asked to!
|
2462 |
|
|
|
2463 |
|
|
void
|
2464 |
|
|
i82544_poll(struct eth_drv_sc *sc)
|
2465 |
|
|
{
|
2466 |
|
|
struct i82544 *p_i82544;
|
2467 |
|
|
p_i82544 = (struct i82544 *)sc->driver_private;
|
2468 |
|
|
|
2469 |
|
|
#ifdef DEBUG
|
2470 |
|
|
db_printf("i82544_poll\n");
|
2471 |
|
|
#endif
|
2472 |
|
|
|
2473 |
|
|
IF_BAD_82544( p_i82544 ) {
|
2474 |
|
|
#ifdef DEBUG
|
2475 |
|
|
os_printf( "i82544_poll: Bad device pointer %x\n", p_i82544 );
|
2476 |
|
|
#endif
|
2477 |
|
|
return;
|
2478 |
|
|
}
|
2479 |
|
|
|
2480 |
|
|
if (!check_link(p_i82544))
|
2481 |
|
|
return;
|
2482 |
|
|
|
2483 |
|
|
// As it happens, this driver always requests the DSR to be called:
|
2484 |
|
|
(void)eth_isr( p_i82544->vector, (cyg_addrword_t)p_i82544 );
|
2485 |
|
|
|
2486 |
|
|
// (no harm in calling this ints-off also, when polled)
|
2487 |
|
|
i82544_deliver( sc );
|
2488 |
|
|
}
|
2489 |
|
|
|
2490 |
|
|
// ------------------------------------------------------------------------
|
2491 |
|
|
// Determine interrupt vector used by a device - for attaching GDB stubs
|
2492 |
|
|
// packet handler.
|
2493 |
|
|
|
2494 |
|
|
int
|
2495 |
|
|
i82544_int_vector(struct eth_drv_sc *sc)
|
2496 |
|
|
{
|
2497 |
|
|
struct i82544 *p_i82544;
|
2498 |
|
|
p_i82544 = (struct i82544 *)sc->driver_private;
|
2499 |
|
|
return (p_i82544->vector);
|
2500 |
|
|
}
|
2501 |
|
|
|
2502 |
|
|
|
2503 |
|
|
// ------------------------------------------------------------------------
|
2504 |
|
|
//
|
2505 |
|
|
// Function : pci_init_find_82544s
|
2506 |
|
|
//
|
2507 |
|
|
// This is called exactly once at the start of time to:
|
2508 |
|
|
// o scan the PCI bus for objects
|
2509 |
|
|
// o record them in the device table
|
2510 |
|
|
// o acquire all the info needed for the driver to access them
|
2511 |
|
|
// o instantiate interrupts for them
|
2512 |
|
|
// o attach those interrupts appropriately
|
2513 |
|
|
// ------------------------------------------------------------------------
|
2514 |
|
|
|
2515 |
|
|
static cyg_pci_match_func find_82544s_match_func;
|
2516 |
|
|
|
2517 |
|
|
// Intel 82543 and 82544 are virtually identical, with different
|
2518 |
|
|
// dev codes
|
2519 |
|
|
static cyg_bool
|
2520 |
|
|
find_82544s_match_func( cyg_uint16 v, cyg_uint16 d, cyg_uint32 c, void *p )
|
2521 |
|
|
{
|
2522 |
|
|
return ((0x8086 == v) &&
|
2523 |
|
|
((0x1004 == d) || // 82543
|
2524 |
|
|
(0x100d == d) || // 82543
|
2525 |
|
|
(0x1008 == d) || // 82544
|
2526 |
|
|
(0x1010 == d) || // 82546
|
2527 |
|
|
(0x100e == d) // 82540EM
|
2528 |
|
|
)
|
2529 |
|
|
);
|
2530 |
|
|
}
|
2531 |
|
|
|
2532 |
|
|
static int
|
2533 |
|
|
pci_init_find_82544s( void )
|
2534 |
|
|
{
|
2535 |
|
|
cyg_pci_device_id devid;
|
2536 |
|
|
cyg_pci_device dev_info;
|
2537 |
|
|
cyg_uint16 cmd;
|
2538 |
|
|
int device_index;
|
2539 |
|
|
int found_devices = 0;
|
2540 |
|
|
|
2541 |
|
|
#ifdef DEBUG
|
2542 |
|
|
db_printf("pci_init_find_82544s()\n");
|
2543 |
|
|
#endif
|
2544 |
|
|
|
2545 |
|
|
// allocate memory to be used in ioctls later
|
2546 |
|
|
if (mem_reserved_ioctl != (void*)0) {
|
2547 |
|
|
#ifdef DEBUG
|
2548 |
|
|
db_printf("pci_init_find_82544s() called > once\n");
|
2549 |
|
|
#endif
|
2550 |
|
|
return 0;
|
2551 |
|
|
}
|
2552 |
|
|
|
2553 |
|
|
// First initialize the heap in PCI window'd memory
|
2554 |
|
|
i82544_heap_size = CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE;
|
2555 |
|
|
i82544_heap_base = (cyg_uint8 *)CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE;
|
2556 |
|
|
i82544_heap_free = i82544_heap_base;
|
2557 |
|
|
|
2558 |
|
|
// mem_reserved_ioctl = pciwindow_mem_alloc(MAX_MEM_RESERVED_IOCTL);
|
2559 |
|
|
|
2560 |
|
|
cyg_pci_init();
|
2561 |
|
|
#ifdef DEBUG
|
2562 |
|
|
db_printf("Finished cyg_pci_init();\n");
|
2563 |
|
|
#endif
|
2564 |
|
|
|
2565 |
|
|
devid = CYG_PCI_NULL_DEVID;
|
2566 |
|
|
|
2567 |
|
|
for (device_index = 0;
|
2568 |
|
|
device_index < CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT;
|
2569 |
|
|
device_index++) {
|
2570 |
|
|
struct i82544 *p_i82544 = i82544_priv_array[device_index];
|
2571 |
|
|
|
2572 |
|
|
p_i82544->index = device_index;
|
2573 |
|
|
|
2574 |
|
|
// See above for find_82544s_match_func
|
2575 |
|
|
if (cyg_pci_find_matching( &find_82544s_match_func, NULL, &devid )) {
|
2576 |
|
|
#ifdef DEBUG
|
2577 |
|
|
db_printf("eth%d = 8254x\n", device_index);
|
2578 |
|
|
#endif
|
2579 |
|
|
cyg_pci_get_device_info(devid, &dev_info);
|
2580 |
|
|
|
2581 |
|
|
p_i82544->interrupt_handle = 0; // Flag not attached.
|
2582 |
|
|
if (cyg_pci_translate_interrupt(&dev_info, &p_i82544->vector)) {
|
2583 |
|
|
#ifdef DEBUG
|
2584 |
|
|
db_printf(" Wired to HAL vector %d\n", p_i82544->vector);
|
2585 |
|
|
#endif
|
2586 |
|
|
#ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
|
2587 |
|
|
cyg_drv_interrupt_create(
|
2588 |
|
|
p_i82544->vector,
|
2589 |
|
|
0, // Priority - unused
|
2590 |
|
|
(CYG_ADDRWORD)p_i82544, // Data item passed to ISR & DSR
|
2591 |
|
|
#ifdef CYGHWR_DEVS_ETH_INTEL_I82544_DEMUX_ALL
|
2592 |
|
|
eth_mux_isr, // ISR
|
2593 |
|
|
#else
|
2594 |
|
|
eth_isr, // ISR
|
2595 |
|
|
#endif
|
2596 |
|
|
eth_dsr, // DSR
|
2597 |
|
|
&p_i82544->interrupt_handle, // handle to intr obj
|
2598 |
|
|
&p_i82544->interrupt_object ); // space for int obj
|
2599 |
|
|
|
2600 |
|
|
cyg_drv_interrupt_attach(p_i82544->interrupt_handle);
|
2601 |
|
|
|
2602 |
|
|
// Don't unmask the interrupt yet, that could get us into a
|
2603 |
|
|
// race.
|
2604 |
|
|
#ifdef CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT
|
2605 |
|
|
// ALSO attach it to MUX interrupt for multiplexed
|
2606 |
|
|
// interrupts. This is for certain boards where the
|
2607 |
|
|
// PCI backplane is wired "straight through" instead of
|
2608 |
|
|
// with a rotation of interrupt lines in the different
|
2609 |
|
|
// slots.
|
2610 |
|
|
{
|
2611 |
|
|
static cyg_handle_t mux_interrupt_handle = 0;
|
2612 |
|
|
static cyg_interrupt mux_interrupt_object;
|
2613 |
|
|
|
2614 |
|
|
if ( ! mux_interrupt_handle ) {
|
2615 |
|
|
#ifdef DEBUG
|
2616 |
|
|
db_printf(" Also attaching to HAL vector %d\n",
|
2617 |
|
|
CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT);
|
2618 |
|
|
#endif
|
2619 |
|
|
cyg_drv_interrupt_create(
|
2620 |
|
|
CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT,
|
2621 |
|
|
0, // Priority - unused
|
2622 |
|
|
(CYG_ADDRWORD)p_i82544,// Data item passed to ISR and DSR
|
2623 |
|
|
eth_mux_isr, // ISR
|
2624 |
|
|
eth_dsr, // DSR
|
2625 |
|
|
&mux_interrupt_handle,
|
2626 |
|
|
&mux_interrupt_object );
|
2627 |
|
|
|
2628 |
|
|
cyg_drv_interrupt_attach(mux_interrupt_handle);
|
2629 |
|
|
}
|
2630 |
|
|
}
|
2631 |
|
|
#endif // CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT
|
2632 |
|
|
#endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
|
2633 |
|
|
}
|
2634 |
|
|
else {
|
2635 |
|
|
p_i82544->vector=0;
|
2636 |
|
|
#ifdef DEBUG
|
2637 |
|
|
db_printf(" Does not generate interrupts.\n");
|
2638 |
|
|
#endif
|
2639 |
|
|
}
|
2640 |
|
|
|
2641 |
|
|
if (cyg_pci_configure_device(&dev_info)) {
|
2642 |
|
|
#ifdef DEBUG
|
2643 |
|
|
int i;
|
2644 |
|
|
db_printf("Found device on bus %d, devfn 0x%02x:\n",
|
2645 |
|
|
CYG_PCI_DEV_GET_BUS(devid),
|
2646 |
|
|
CYG_PCI_DEV_GET_DEVFN(devid));
|
2647 |
|
|
|
2648 |
|
|
if (dev_info.command & CYG_PCI_CFG_COMMAND_ACTIVE) {
|
2649 |
|
|
db_printf(" Note that board is active. Probed"
|
2650 |
|
|
" sizes and CPU addresses invalid!\n");
|
2651 |
|
|
}
|
2652 |
|
|
db_printf(" Vendor 0x%04x", dev_info.vendor);
|
2653 |
|
|
db_printf("\n Device 0x%04x", dev_info.device);
|
2654 |
|
|
db_printf("\n Command 0x%04x, Status 0x%04x\n",
|
2655 |
|
|
dev_info.command, dev_info.status);
|
2656 |
|
|
|
2657 |
|
|
db_printf(" Class/Rev 0x%08x", dev_info.class_rev);
|
2658 |
|
|
db_printf("\n Header 0x%02x\n", dev_info.header_type);
|
2659 |
|
|
|
2660 |
|
|
db_printf(" SubVendor 0x%04x, Sub ID 0x%04x\n",
|
2661 |
|
|
dev_info.header.normal.sub_vendor,
|
2662 |
|
|
dev_info.header.normal.sub_id);
|
2663 |
|
|
|
2664 |
|
|
for(i = 0; i < CYG_PCI_MAX_BAR; i++) {
|
2665 |
|
|
db_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
|
2666 |
|
|
db_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
|
2667 |
|
|
dev_info.base_size[i], dev_info.base_map[i]);
|
2668 |
|
|
}
|
2669 |
|
|
db_printf(" eth%d configured\n", device_index);
|
2670 |
|
|
#endif
|
2671 |
|
|
found_devices++;
|
2672 |
|
|
p_i82544->found = 1;
|
2673 |
|
|
p_i82544->active = 0;
|
2674 |
|
|
p_i82544->devid = devid;
|
2675 |
|
|
p_i82544->device = dev_info.device;
|
2676 |
|
|
p_i82544->io_address = dev_info.base_map[0];
|
2677 |
|
|
#ifdef DEBUG
|
2678 |
|
|
db_printf(" I/O address = 0x%08x device = %04x\n", dev_info.base_map[0],
|
2679 |
|
|
dev_info.device);
|
2680 |
|
|
#endif
|
2681 |
|
|
|
2682 |
|
|
// Don't use cyg_pci_set_device_info since it clears
|
2683 |
|
|
// some of the fields we want to print out below.
|
2684 |
|
|
cyg_pci_read_config_uint16(dev_info.devid,
|
2685 |
|
|
CYG_PCI_CFG_COMMAND, &cmd);
|
2686 |
|
|
cmd |= (CYG_PCI_CFG_COMMAND_IO // enable I/O space
|
2687 |
|
|
| CYG_PCI_CFG_COMMAND_MEMORY // enable memory space
|
2688 |
|
|
| CYG_PCI_CFG_COMMAND_MASTER); // enable bus master
|
2689 |
|
|
cyg_pci_write_config_uint16(dev_info.devid,
|
2690 |
|
|
CYG_PCI_CFG_COMMAND, cmd);
|
2691 |
|
|
|
2692 |
|
|
// Now the PCI part of the device is configured, reset
|
2693 |
|
|
// it. This should make it safe to enable the
|
2694 |
|
|
// interrupt
|
2695 |
|
|
i82544_reset(p_i82544);
|
2696 |
|
|
|
2697 |
|
|
// This is the indicator for "uses an interrupt"
|
2698 |
|
|
if (p_i82544->interrupt_handle != 0) {
|
2699 |
|
|
cyg_drv_interrupt_acknowledge(p_i82544->vector);
|
2700 |
|
|
#ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
|
2701 |
|
|
cyg_drv_interrupt_unmask(p_i82544->vector);
|
2702 |
|
|
#endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
|
2703 |
|
|
}
|
2704 |
|
|
#ifdef DEBUG
|
2705 |
|
|
db_printf(" **** Device enabled for I/O and Memory "
|
2706 |
|
|
"and Bus Master\n");
|
2707 |
|
|
#endif
|
2708 |
|
|
}
|
2709 |
|
|
else {
|
2710 |
|
|
p_i82544->found = 0;
|
2711 |
|
|
p_i82544->active = 0;
|
2712 |
|
|
#ifdef DEBUG
|
2713 |
|
|
db_printf("Failed to configure device %d\n",device_index);
|
2714 |
|
|
#endif
|
2715 |
|
|
}
|
2716 |
|
|
}
|
2717 |
|
|
else {
|
2718 |
|
|
p_i82544->found = 0;
|
2719 |
|
|
p_i82544->active = 0;
|
2720 |
|
|
#ifdef DEBUG
|
2721 |
|
|
db_printf("eth%d not found\n", device_index);
|
2722 |
|
|
#endif
|
2723 |
|
|
}
|
2724 |
|
|
}
|
2725 |
|
|
|
2726 |
|
|
if (0 == found_devices)
|
2727 |
|
|
return 0;
|
2728 |
|
|
|
2729 |
|
|
#ifdef CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT
|
2730 |
|
|
// Now enable the mux shared interrupt if it is in use
|
2731 |
|
|
if (mux_interrupt_handle) {
|
2732 |
|
|
cyg_drv_interrupt_acknowledge(CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT);
|
2733 |
|
|
cyg_drv_interrupt_unmask(CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT);
|
2734 |
|
|
}
|
2735 |
|
|
#endif
|
2736 |
|
|
|
2737 |
|
|
// Now a delay to ensure the hardware has "come up" before you try to
|
2738 |
|
|
// use it. Yes, really, the full 2 seconds. It's only really
|
2739 |
|
|
// necessary if DEBUG is off - otherwise all that printout wastes
|
2740 |
|
|
// enough time. No kidding.
|
2741 |
|
|
udelay( 2000000 );
|
2742 |
|
|
return 1;
|
2743 |
|
|
}
|
2744 |
|
|
|
2745 |
|
|
// ------------------------------------------------------------------------
|
2746 |
|
|
//
|
2747 |
|
|
// Function : i82544_configure
|
2748 |
|
|
//
|
2749 |
|
|
// Return : 0 = It worked.
|
2750 |
|
|
// non0 = It failed.
|
2751 |
|
|
// ------------------------------------------------------------------------
|
2752 |
|
|
|
2753 |
|
|
static int i82544_configure(struct i82544* p_i82544, int promisc, int oversized)
|
2754 |
|
|
{
|
2755 |
|
|
cyg_uint32 ioaddr;
|
2756 |
|
|
// volatile CFG *ccs;
|
2757 |
|
|
// volatile cyg_uint8* config_bytes;
|
2758 |
|
|
// cyg_uint16 status;
|
2759 |
|
|
// int count;
|
2760 |
|
|
|
2761 |
|
|
IF_BAD_82544( p_i82544 ) {
|
2762 |
|
|
#ifdef DEBUG
|
2763 |
|
|
os_printf( "eth_set_promiscuous_mode: Bad device pointer %x\n",
|
2764 |
|
|
p_i82544 );
|
2765 |
|
|
#endif
|
2766 |
|
|
return -1;
|
2767 |
|
|
}
|
2768 |
|
|
|
2769 |
|
|
ioaddr = p_i82544->io_address;
|
2770 |
|
|
|
2771 |
|
|
// Not currently supported
|
2772 |
|
|
|
2773 |
|
|
return 0;
|
2774 |
|
|
}
|
2775 |
|
|
|
2776 |
|
|
// ------------------------------------------------------------------------
|
2777 |
|
|
//
|
2778 |
|
|
// Function : eth_set_mac_address
|
2779 |
|
|
//
|
2780 |
|
|
// Return : 0 = It worked.
|
2781 |
|
|
// non0 = It failed.
|
2782 |
|
|
// ------------------------------------------------------------------------
|
2783 |
|
|
|
2784 |
|
|
static int
|
2785 |
|
|
eth_set_mac_address(struct i82544* p_i82544, cyg_uint8 *addr, int eeprom)
|
2786 |
|
|
{
|
2787 |
|
|
cyg_uint32 ioaddr;
|
2788 |
|
|
cyg_uint32 maclo, machi;
|
2789 |
|
|
|
2790 |
|
|
#ifdef DEBUG
|
2791 |
|
|
db_printf("eth_set_mac_address\n");
|
2792 |
|
|
#endif
|
2793 |
|
|
|
2794 |
|
|
IF_BAD_82544( p_i82544 ) {
|
2795 |
|
|
#ifdef DEBUG
|
2796 |
|
|
os_printf( "eth_set_mac_address : Bad device pointer %x\n",
|
2797 |
|
|
p_i82544 );
|
2798 |
|
|
#endif
|
2799 |
|
|
return -1;
|
2800 |
|
|
}
|
2801 |
|
|
|
2802 |
|
|
ioaddr = p_i82544->io_address;
|
2803 |
|
|
|
2804 |
|
|
// Write MAC address to RAT[0]
|
2805 |
|
|
|
2806 |
|
|
maclo = addr[0] | (addr[1]<<8) | (addr[2]<<16) | (addr[3]<<24);
|
2807 |
|
|
machi = (1<<31) | (0<<16) | addr[4] | (addr[5]<<8);
|
2808 |
|
|
|
2809 |
|
|
#ifdef DEBUG
|
2810 |
|
|
os_printf("setting: lo %08x hi %08x\n",maclo,machi);
|
2811 |
|
|
#endif
|
2812 |
|
|
|
2813 |
|
|
OUTL( maclo , ioaddr + I82544_RAT );
|
2814 |
|
|
OUTL( machi, ioaddr + I82544_RAT + 4 );
|
2815 |
|
|
|
2816 |
|
|
|
2817 |
|
|
// record the MAC address in the device structure
|
2818 |
|
|
p_i82544->mac_address[0] = addr[0];
|
2819 |
|
|
p_i82544->mac_address[1] = addr[1];
|
2820 |
|
|
p_i82544->mac_address[2] = addr[2];
|
2821 |
|
|
p_i82544->mac_address[3] = addr[3];
|
2822 |
|
|
p_i82544->mac_address[4] = addr[4];
|
2823 |
|
|
p_i82544->mac_address[5] = addr[5];
|
2824 |
|
|
p_i82544->mac_addr_ok = 1;
|
2825 |
|
|
|
2826 |
|
|
#ifdef DEBUG
|
2827 |
|
|
os_printf( "Set MAC Address = %02X %02X %02X %02X %02X %02X (ok %d)\n",
|
2828 |
|
|
p_i82544->mac_address[0],
|
2829 |
|
|
p_i82544->mac_address[1],
|
2830 |
|
|
p_i82544->mac_address[2],
|
2831 |
|
|
p_i82544->mac_address[3],
|
2832 |
|
|
p_i82544->mac_address[4],
|
2833 |
|
|
p_i82544->mac_address[5],
|
2834 |
|
|
p_i82544->mac_addr_ok );
|
2835 |
|
|
#endif
|
2836 |
|
|
|
2837 |
|
|
return p_i82544->mac_addr_ok ? 0 : 1;
|
2838 |
|
|
}
|
2839 |
|
|
|
2840 |
|
|
// ------------------------------------------------------------------------
|
2841 |
|
|
//
|
2842 |
|
|
// Function : eth_get_mac_address
|
2843 |
|
|
//
|
2844 |
|
|
// ------------------------------------------------------------------------
|
2845 |
|
|
#ifdef ETH_DRV_GET_MAC_ADDRESS
|
2846 |
|
|
static int
|
2847 |
|
|
eth_get_mac_address(struct i82544* p_i82544, char *addr)
|
2848 |
|
|
{
|
2849 |
|
|
#ifdef DEBUG
|
2850 |
|
|
db_printf("eth_get_mac_address\n");
|
2851 |
|
|
#endif
|
2852 |
|
|
|
2853 |
|
|
IF_BAD_82544( p_i82544 ) {
|
2854 |
|
|
#ifdef DEBUG
|
2855 |
|
|
os_printf( "eth_get_mac_address : Bad device pointer %x\n",
|
2856 |
|
|
p_i82544 );
|
2857 |
|
|
#endif
|
2858 |
|
|
return -1;
|
2859 |
|
|
}
|
2860 |
|
|
|
2861 |
|
|
memcpy( addr, (char *)(&p_i82544->mac_address[0]), 6 );
|
2862 |
|
|
return 0;
|
2863 |
|
|
}
|
2864 |
|
|
#endif
|
2865 |
|
|
// ------------------------------------------------------------------------
|
2866 |
|
|
//
|
2867 |
|
|
// Function : i82544_ioctl
|
2868 |
|
|
//
|
2869 |
|
|
// ------------------------------------------------------------------------
|
2870 |
|
|
static int
|
2871 |
|
|
i82544_ioctl(struct eth_drv_sc *sc, unsigned long key,
|
2872 |
|
|
void *data, int data_length)
|
2873 |
|
|
{
|
2874 |
|
|
struct i82544 *p_i82544;
|
2875 |
|
|
|
2876 |
|
|
#ifdef DEBUG
|
2877 |
|
|
db_printf("i82544_ioctl\n");
|
2878 |
|
|
#endif
|
2879 |
|
|
|
2880 |
|
|
p_i82544 = (struct i82544 *)sc->driver_private;
|
2881 |
|
|
|
2882 |
|
|
IF_BAD_82544( p_i82544 ) {
|
2883 |
|
|
#ifdef DEBUG
|
2884 |
|
|
os_printf( "i82544_ioctl/control: Bad device pointer %x\n", p_i82544 );
|
2885 |
|
|
#endif
|
2886 |
|
|
return -1;
|
2887 |
|
|
}
|
2888 |
|
|
|
2889 |
|
|
#ifdef ioctlDEBUG
|
2890 |
|
|
db_printf( "i82544_ioctl: device eth%d at %x; key is 0x%x, data at %x[%d]\n",
|
2891 |
|
|
p_i82544->index, p_i82544, key, data, data_length );
|
2892 |
|
|
#endif
|
2893 |
|
|
|
2894 |
|
|
switch ( key ) {
|
2895 |
|
|
|
2896 |
|
|
#ifdef ETH_DRV_SET_MAC_ADDRESS
|
2897 |
|
|
case ETH_DRV_SET_MAC_ADDRESS:
|
2898 |
|
|
if ( 6 != data_length )
|
2899 |
|
|
return -2;
|
2900 |
|
|
return eth_set_mac_address( p_i82544, data, 1 /* do write eeprom */ );
|
2901 |
|
|
#endif
|
2902 |
|
|
|
2903 |
|
|
#ifdef ETH_DRV_GET_MAC_ADDRESS
|
2904 |
|
|
case ETH_DRV_GET_MAC_ADDRESS:
|
2905 |
|
|
return eth_get_mac_address( p_i82544, data );
|
2906 |
|
|
#endif
|
2907 |
|
|
|
2908 |
|
|
default:
|
2909 |
|
|
break;
|
2910 |
|
|
}
|
2911 |
|
|
return -1;
|
2912 |
|
|
}
|
2913 |
|
|
|
2914 |
|
|
// ------------------------------------------------------------------------
|
2915 |
|
|
|
2916 |
|
|
// EOF if_i82544.c
|