1 |
786 |
skrzyp |
|
2 |
|
|
|
3 |
|
|
|
4 |
|
|
|
5 |
|
|
|
6 |
|
|
|
7 |
|
|
|
8 |
|
|
|
9 |
|
|
|
10 |
|
|
|
11 |
|
|
|
12 |
|
|
|
13 |
|
|
|
14 |
|
|
|
15 |
|
|
|
16 |
|
|
|
17 |
|
|
|
18 |
|
|
|
19 |
|
|
|
20 |
|
|
|
21 |
|
|
|
22 |
|
|
|
23 |
|
|
|
24 |
|
|
|
25 |
|
|
|
26 |
|
|
|
27 |
|
|
|
28 |
|
|
|
29 |
|
|
|
30 |
|
|
|
31 |
|
|
|
32 |
|
|
|
33 |
|
|
|
34 |
|
|
|
35 |
|
|
|
36 |
|
|
|
37 |
|
|
Freescale ColdFire Ethernet Driver
|
38 |
|
|
|
39 |
|
|
|
40 |
|
|
|
41 |
|
|
Freescale ColdFire Ethernet Driver
|
42 |
|
|
|
43 |
|
|
|
44 |
|
|
CYGPKG_DEVS_ETH_MCFxxxx
|
45 |
|
|
eCos Support for Freescale ColdFire On-chip Ethernet Devices
|
46 |
|
|
|
47 |
|
|
|
48 |
|
|
Description
|
49 |
|
|
|
50 |
|
|
Some members of the Freescale ColdFire family of processors come with
|
51 |
|
|
an on-chip ethernet device. This package provides an eCos driver for
|
52 |
|
|
that device. The driver supports both polled mode for use by RedBoot
|
53 |
|
|
and interrupt-driven mode for use by a full TCP/IP stack.
|
54 |
|
|
|
55 |
|
|
|
56 |
|
|
The original version of the driver was written specifically for the
|
57 |
|
|
MCF5272 processor. It has since been made to work on other members of
|
58 |
|
|
the ColdFire family.
|
59 |
|
|
|
60 |
|
|
|
61 |
|
|
|
62 |
|
|
Configuration Options
|
63 |
|
|
|
64 |
|
|
This ethernet package should be loaded automatically when
|
65 |
|
|
selecting a target containing a ColdFire processor with on-chip
|
66 |
|
|
ethernet, and it should never be necessary to load it explicitly. If
|
67 |
|
|
the application does not actually require ethernet functionality then
|
68 |
|
|
the package is inactive and the final executable will not suffer any
|
69 |
|
|
overheads from unused functionality. This is determined by the
|
70 |
|
|
presence of the generic ethernet I/O package
|
71 |
|
|
CYGPKG_IO_ETH_DRIVERS. Typically the choice of eCos
|
72 |
|
|
template causes the right thing to happen. For example the default
|
73 |
|
|
template does not include any TCP/IP stack so
|
74 |
|
|
CYGPKG_IO_ETH_DRIVERS is not included, but the
|
75 |
|
|
net, redboot and lwip_eth templates do include a TCP/IP stack so will
|
76 |
|
|
specify that package and hence enable the ethernet driver.
|
77 |
|
|
|
78 |
|
|
|
79 |
|
|
All eCos network devices need a unique name. By default the on-chip
|
80 |
|
|
ethernet device is assigned the name eth0 but
|
81 |
|
|
can be changed through the configuration option
|
82 |
|
|
CYGDAT_DEVS_ETH_MCFxxxx_NAME. This is useful if for
|
83 |
|
|
example the target hardware includes a number of additional off-chip
|
84 |
|
|
ethernet devices.
|
85 |
|
|
|
86 |
|
|
|
87 |
|
|
The hardware requires that incoming ethernet frames are received
|
88 |
|
|
into one of a small number of buffers, arranged in a ring. Once a
|
89 |
|
|
frame has been received and its size is known the driver will pass it
|
90 |
|
|
up to higher-level code for further processing. The number of these
|
91 |
|
|
buffers is configurable via the option
|
92 |
|
|
CYGNUM_DEVS_ETH_MCFxxxx_RXBUFFERS. Each receive
|
93 |
|
|
buffer requires 1528 bytes of memory. A smaller number of buffers
|
94 |
|
|
increases the probability that incoming ethernet frames have to be
|
95 |
|
|
discarded. TCP/IP stacks are designed to cope with the occasional lost
|
96 |
|
|
packet, but if too many frames are discarded then this will greatly
|
97 |
|
|
affect performance. A key issue here is that passing the incoming
|
98 |
|
|
frames up to higher-level code typically happens at thread level and
|
99 |
|
|
hence the system behaviour is defined in large part by the priority of
|
100 |
|
|
various threads running in the TCP/IP stack. If application code has
|
101 |
|
|
high-priority threads that take up much of the available cpu time and
|
102 |
|
|
the TCP/IP stack gets little chance to run then there will be little
|
103 |
|
|
opportunity to pass received frames up the stack. Balancing out the
|
104 |
|
|
various thread priorities and the number of receive buffers is the
|
105 |
|
|
responsibility of the application developer.
|
106 |
|
|
|
107 |
|
|
|
108 |
|
|
By default the ethernet driver will raise interrupts using a low
|
109 |
|
|
priority level. The exact value will depend on the processor being
|
110 |
|
|
used, for example the MCF5282 interrupt controllers impose specific
|
111 |
|
|
constraints on interrupt priorities. The driver does very little at
|
112 |
|
|
interrupt level, instead the real work is done via threads inside the
|
113 |
|
|
TCP/IP stack. Hence the interrupt priority has little or no effect on
|
114 |
|
|
the system's behaviour. If the default priorities are inappropriate for
|
115 |
|
|
some reason then they can be changed through the configuration options
|
116 |
|
|
CYGNUM_DEVS_ETH_MCFxxxx_ISR_RX_PRIORITY and
|
117 |
|
|
CYGNUM_DEVS_ETH_MCFxxxx_ISR_TX_PRIORITY.
|
118 |
|
|
|
119 |
|
|
|
120 |
|
|
There is an option related to the default network MAC address,
|
121 |
|
|
CYGDAT_DEVS_ETH_MCFxxxx_PLATFORM_MAC. This is
|
122 |
|
|
discussed in more detail
|
123 |
|
|
linkend="devs-eth-m68k-mcfxxxx-mac">below.
|
124 |
|
|
|
125 |
|
|
|
126 |
|
|
Optionally the ethernet driver can maintain statistics about the
|
127 |
|
|
number of incoming and transmitted ethernet frames, receive overruns,
|
128 |
|
|
collisions, and other conditions. Maintaining and providing these
|
129 |
|
|
statistics involves some overhead, and is controlled by the
|
130 |
|
|
configuration option
|
131 |
|
|
CYGFUN_DEVS_ETH_MCFxxxx_STATISTICS. Typically these
|
132 |
|
|
statistics are only accessed through SNMP, so by default statistics
|
133 |
|
|
gathering is enabled if the configuration includes
|
134 |
|
|
CYGPKG_SNMPAGENT and disabled otherwise.
|
135 |
|
|
|
136 |
|
|
|
137 |
|
|
|
138 |
|
|
MAC Address
|
139 |
|
|
|
140 |
|
|
The ColdFire processors do not have a built-in unique network MAC
|
141 |
|
|
address since that would require slightly different manufacturing for
|
142 |
|
|
each chip. All ethernet devices should have a unique address so this
|
143 |
|
|
has to come from elsewhere. There are a number of possibilities:
|
144 |
|
|
|
145 |
|
|
|
146 |
|
|
|
147 |
|
|
The platform HAL can provide the address. For example the target board
|
148 |
|
|
may have a small serial EPROM or similar which is initialized during
|
149 |
|
|
board manufacture. The platform HAL can read the serial EPROM during
|
150 |
|
|
system startup and provide the information to the ethernet driver. If
|
151 |
|
|
this is the case then the platform HAL should implement the CDL
|
152 |
|
|
interface CYGINT_DEVS_ETH_MCFxxxx_PLATFORM_MAC and
|
153 |
|
|
provide a macro HAL_MCFxxxx_ETH_GET_MAC_ADDRESS
|
154 |
|
|
in the exported header
|
155 |
|
|
class="headerfile">cyg/hal/plf_arch.h.
|
156 |
|
|
|
157 |
|
|
|
158 |
|
|
There is a configuration option
|
159 |
|
|
CYGDAT_DEVS_ETH_MCFxxxx_PLATFORM_MAC which
|
160 |
|
|
specifies the default MAC address. Manipulating this option is fine if
|
161 |
|
|
the configuration will only be used on a single board. However if
|
162 |
|
|
multiple boards run applications with the same configuration then they
|
163 |
|
|
would all have the same MAC address, and the resulting behaviour is
|
164 |
|
|
undefined.
|
165 |
|
|
|
166 |
|
|
|
167 |
|
|
If the target hardware boots via RedBoot and uses a block of flash to
|
168 |
|
|
hold configuration variables then one of these variables will be the
|
169 |
|
|
MAC address. It can be manipulated at the RedBoot prompt using the
|
170 |
|
|
fconfig command, thus giving each board a unique
|
171 |
|
|
address. An eCos application containing the ethernet driver will
|
172 |
|
|
automatically pick up this address.
|
173 |
|
|
|
174 |
|
|
|
175 |
|
|
|
176 |
|
|
When designing a new target board it is recommended that the board
|
177 |
|
|
comes with a unique network address supported by the platform HAL,
|
178 |
|
|
rather than relying on users to change the address. The latter
|
179 |
|
|
approach can be error-prone and will lead to failures that are
|
180 |
|
|
difficult to track down.
|
181 |
|
|
|
182 |
|
|
|
183 |
|
|
|
184 |
|
|
Platform-specific PHY
|
185 |
|
|
|
186 |
|
|
The on-chip ethernet hardware relies on an external media independent
|
187 |
|
|
interface (MII), also known as a PHY chip. This separate chip handles
|
188 |
|
|
the low-level details of ethernet communication, for example
|
189 |
|
|
negotiating a link speed with the hub. In most scenarios the PHY chip
|
190 |
|
|
simply does the right thing and needs no support from the ethernet
|
191 |
|
|
driver. If there are special requirements, for example if the board
|
192 |
|
|
has to be hardwired to communicate at 10Mbps rather than autonegotiate
|
193 |
|
|
the link speed, then usually this is handled by fixed logic levels on
|
194 |
|
|
some of the PHY pins or by using jumpers.
|
195 |
|
|
|
196 |
|
|
|
197 |
|
|
The eCos ethernet driver assumes that the PHY is already fully
|
198 |
|
|
operational and does not interact with it in any way. If the target
|
199 |
|
|
hardware does require software initialization of the PHY chip then
|
200 |
|
|
usually this will be done in the platform HAL, because the choice of
|
201 |
|
|
PHY chip is a characteristic of the platform.
|
202 |
|
|
|
203 |
|
|
|
204 |
|
|
|
205 |
|
|
|
206 |
|
|
|