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#ifndef _IF_MCF5272_FEC
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#define _IF_MCF5272_FEC
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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#include <cyg/hal/drv_api.h>
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#include <cyg/io/eth/eth_drv_stats.h>
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#include <cyg/devs/eth/nbuf.h>
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/* Ethernet controller inetrrupt priority level. */
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#define MCF5272_INT_LEVEL 4
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/* Bit level definitions and macros */
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#define MCF5272_FEC_ECR_RESET (0x00000001)
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#define MCF5272_FEC_ECR_ETHER_EN (0x00000002)
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#define MCF5272_FEC_EIR_GRA (0x10000000)
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#define MCF5272_FEC_EIR_HBE (0x80000000)
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#define MCF5272_FEC_EIR_BR (0x40000000)
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#define MCF5272_FEC_EIR_BT (0x20000000)
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#define MCF5272_FEC_EIR_GRA (0x10000000)
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#define MCF5272_FEC_EIR_TXF (0x08000000)
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#define MCF5272_FEC_EIR_TXB (0x04000000)
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#define MCF5272_FEC_EIR_RXF (0x02000000)
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#define MCF5272_FEC_EIR_RXB (0x01000000)
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#define MCF5272_FEC_EIR_MII (0x00800000)
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#define MCF5272_FEC_EIR_EBERR (0x00400000)
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#define MCF5272_FEC_EIR_UMINT (1<<21)
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#define MCF5272_FEC_IMR_HBEEN (0x80000000)
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#define MCF5272_FEC_IMR_BREN (0x40000000)
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#define MCF5272_FEC_IMR_BTEN (0x20000000)
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#define MCF5272_FEC_IMR_GRAEN (0x10000000)
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#define MCF5272_FEC_IMR_TXFEN (0x08000000)
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#define MCF5272_FEC_IMR_TXBEN (0x04000000)
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#define MCF5272_FEC_IMR_RXFEN (0x02000000)
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#define MCF5272_FEC_IMR_RXBEN (0x01000000)
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#define MCF5272_FEC_IMR_MIIEN (0x00800000)
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#define MCF5272_FEC_IMR_EBERREN (0x00400000)
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#define MCF5272_FEC_RCR_PROM (0x00000008)
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#define MCF5272_FEC_RCR_MII_MODE (0x00000004)
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#define MCF5272_FEC_RCR_DRT (0x00000002)
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#define MCF5272_FEC_RCR_LOOP (0x00000001)
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#define MCF5272_FEC_TCR_GTS (0x00000001)
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#define MCF5272_FEC_TCR_HBC (0x00000002)
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#define MCF5272_FEC_TCR_FDEN (0x00000004)
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#define MCF5272_FEC_RDAR_DESTACT (0x01000000)
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#define MCF5272_FEC_MFLR_BRDCAST (0x80000000)
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#define MCF5272_FEC_MFLR_MLTCAST (0x40000000)
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#define MCF5272_FEC_XWMRK_64 (0x00000000)
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#define MCF5272_FEC_XWMRK_128 (0x00000002)
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#define MCF5272_FEC_XWMRK_192 (0x00000003)
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/* Define the PHY addresss. This address specifies which 32 attached */
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/* PHY devices. */
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//#define MCF5272_PHY_ADD (0)
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#define MCF5272_PHY_ADD (0 << 23)
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/* Start of frame delimter for valid MII management frame. */
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#define MCF5272_FEC_MII_ST (0x40000000)
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/* Operation code. This field bust be programmed to generate a valid */
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/* MII management frame. */
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#define MCF5272_FEC_MII_OP_READ (0x20000000)
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#define MCF5272_FEC_MII_OP_WRITE (0x10000000)
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/* Register address. Specifies one of the 32 attached PHY devices. */
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#define MCF5272_FEC_MII_RA_POS (18)
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#define MCF5272_FEC_MII_RA_MASK (0x1F)
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/* Turn around. Must be programmed to 10 to generate a valid MII */
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/* management frame. */
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#define MCF5272_FEC_MII_TA (0x00020000)
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/* The management frame data maske. Field for data to be written to */
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/* or read from PHY register. */
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#define MCF5272_FEC_MII_DATA_MASK (0x0000FFFF)
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/* This define the MII unchanged MII frame management bits. */
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#define MCF5272_FEC_MII_FIX_HDR (0 | \
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MCF5272_FEC_MII_ST | \
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MCF5272_PHY_ADD | \
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MCF5272_FEC_MII_TA)
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/* The PHY address mask. */
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#define MCF5272_FEC_MII_PA (0x1F << 23)
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/* Define the interrupt mask. */
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#define MCF5272_FEC_INTERRUPT_MASK (MCF5272_FEC_IMR_TXFEN | \
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MCF5272_FEC_IMR_RXFEN )
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/**************************************************
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* FEC diagnostic counters
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**************************************************/
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typedef struct MCF5272_FEC_DIAG
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{
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/* We put all the receive statistics first. */
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unsigned long rx_pk_cnt; /* The total number of */
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/* received packets */
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unsigned long rx_pk_cnt_sec;
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unsigned long rx_bytes_cnt; /* The total number of */
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/* received bytes */
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unsigned long rx_bytes_cnt_sec;
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unsigned long rx_err_cnt; /* The total number of bad */
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/* packets received */
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unsigned long rx_long_frm_err_cnt; /* The total number of long */
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/* frame errors. */
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unsigned long rx_short_frm_err_cnt; /* The total number of short */
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/* frame errors. */
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unsigned long rx_crc_err_cnt; /* The total number of CRC */
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/* errors. */
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unsigned long rx_overrun_err_cnt; /* The total number of */
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/* overrun errors. */
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unsigned long rx_trunc_error_cnt; /* The total numbers of */
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/* receieve truncated packet */
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/* errors. */
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/* We put all the transmit statistics next. start_of_transmit */
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/* doesn't take any space but only separates the receive statistics */
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/* from the transmit statistics. */
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char start_of_transmit[0];
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unsigned long tx_pk_cnt; /* The total number of */
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/* transmitted packet */
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unsigned long tx_pk_cnt_sec;
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unsigned long tx_bytes_cnt; /* The total number of */
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/* transmitted bytes */
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unsigned long tx_bytes_cnt_sec;
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unsigned long tx_err_cnt; /* The total number of failed */
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/* packet transmission */
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unsigned long tx_def_cnt; /* The total number of tansmit */
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/* defers. */
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unsigned long tx_hb_err_cnt; /* The total number of heart */
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/* beat errors. */
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unsigned long tx_late_col_cnt; /* The total number of late */
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/* collisions. */
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unsigned long tx_exes_retry_cnt; /* Excessive rettry count. */
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unsigned long tx_retry_cnt; /* The total number of transmit */
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/* retries. */
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unsigned long tx_underrun_cnt; /* The total number of transmit */
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/* underruns. */
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unsigned long tx_carrrier_loss_cnt; /* The total number of */
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/* trasnmit carrier losses. */
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unsigned long tx_free_bd_cnt; /* The total number of freed */
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/* buffer descriptor. */
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unsigned long tx_free_min_bd_cnt; /* The minimum number of free */
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/* buffer descriptor count. */
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unsigned long tx_full_cnt; /* The number of times when */
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/* there is no transmit buffer. */
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unsigned long tx_not_complete_cnt; /* The number of times the */
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/* device driver discovered */
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/* that the BD is still in use */
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/* by the FEC. */
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unsigned long internal_bus_error_cnt; /* FEC bus error count. A */
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/* bus error occurred when */
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/* the FEC was accessing an */
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/* internal bus. */
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}MCF5272_FEC_DIAG __attribute__ ((aligned, packed));
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/* Ethernet driver status. */
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enum eth_drv_status_t
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{
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ETH_DEV_UNKNOWN = 1,
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ETH_DEV_DOWN = 2,
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ETH_DEV_UP = 3
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};
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/* Ethernet duplex mode. */
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enum eth_drv_mode_t
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{
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ETH_MODE_UNKNOWN = 1,
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ETH_MODE_SIMPLEX = 2,
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ETH_MODE_DUPLEX = 3
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};
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/* Ethernet speed values. */
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enum eth_speed_t
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{
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ETH_SPEED_10MB = 10*1000*1000,
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ETH_SPEED_100MB = 100*1000*1000
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};
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/* Ethernet driver statistics information structure. */
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struct mcf5272_ether_drv_stats
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{
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struct ifreq ifreq; // tell ioctl() which interface.
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char description[ DESC_LEN ]; // Textual description of hardware
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unsigned char snmp_chipset[ SNMP_CHIPSET_LEN ];
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// SNMP ID of chipset
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enum eth_drv_mode_t duplex; // 1 = UNKNOWN, 2 = SIMPLEX, 3 = DUPLEX
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enum eth_drv_status_t operational; // 1 = UNKNOWN, 2 = DOWN, 3 = UP
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// These are general status information:
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unsigned int speed; // 10,000,000 or 100,000,000
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// to infinity and beyond?
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MCF5272_FEC_DIAG stats;
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}__attribute__ ((aligned, packed));
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#ifndef FIELD_OFFSET
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#define FIELD_OFFSET(type,field) (cyg_uint32)(&(((type*)0)->field)
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#endif /* FIELD_OFFSET */
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/* The value of 1 second in nanosecond. */
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#define SEC_IN_NS 1000000000
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/* 48-bit Ethernet Addresses */
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typedef u8_t ETH_ADDR[6];
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/* 16-bit Ethernet Frame Type, ie. Protocol */
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typedef u16_t ETH_FTYPE;
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/* Maximum and Minimum Ethernet Frame Size (Data Field) */
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#define ETH_DATA_MAX_SIZE (1500)
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#define ETH_DATA_MIN_SIZE (46)
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/* Maximum and Minimum Ethernet Frame Size (Entire frame) */
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#define ETH_MAX_SIZE (ETH_DATA_MAX_SIZE+14)
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#define ETH_MIN_SIZE (ETH_DATA_MIN_SIZE+14)
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/* Common Ethernet Frame definition */
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typedef struct
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{
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ETH_ADDR dest;
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ETH_ADDR src;
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ETH_FTYPE type;
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u8_t data[ETH_DATA_MAX_SIZE];
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u32_t fcs;
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} eth_frame_hdr __attribute__ ((aligned, packed));
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/* 802.1Q Ethernet Frame definition */
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typedef struct
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{
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ETH_ADDR dest;
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ETH_ADDR src;
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u32_t header_802_1q;
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ETH_FTYPE type;
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u8_t data[ETH_DATA_MAX_SIZE];
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u32_t fcs;
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} eth_802_1Q_frame_hdr __attribute__ ((aligned, packed));
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/* Definition of macros that access the FEC registers */
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#define put_reg(_addr_,_value_) \
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*((volatile u32_t*)&(_addr_)) = (cyg_uint32)(_value_)
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#define get_reg(_addr_) \
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*(((volatile u32_t*)&(_addr_)))
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#endif /* _IF_MCF5272_FEC */
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