OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [devs/] [eth/] [mips/] [atlas/] [current/] [src/] [saa9730.h] - Blame information for rev 817

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
#ifndef CYGONCE_DEVS_ETH_MIPS_ATLAS_SAA9730_H
2
#define CYGONCE_DEVS_ETH_MIPS_ATLAS_SAA9730_H
3
/*==========================================================================
4
//
5
//      saa9730.h
6
//      Philips SAA9730 IO Chip Ethernet Interface
7
//
8
//
9
//==========================================================================
10
// ####ECOSGPLCOPYRIGHTBEGIN####
11
// -------------------------------------------
12
// This file is part of eCos, the Embedded Configurable Operating System.
13
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
14
//
15
// eCos is free software; you can redistribute it and/or modify it under
16
// the terms of the GNU General Public License as published by the Free
17
// Software Foundation; either version 2 or (at your option) any later
18
// version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT
21
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License
26
// along with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
28
//
29
// As a special exception, if other files instantiate templates or use
30
// macros or inline functions from this file, or you compile this file
31
// and link it with other works to produce a work based on this file,
32
// this file does not by itself cause the resulting work to be covered by
33
// the GNU General Public License. However the source code for this file
34
// must still be made available in accordance with section (3) of the GNU
35
// General Public License v2.
36
//
37
// This exception does not invalidate any other reasons why a work based
38
// on this file might be covered by the GNU General Public License.
39
// -------------------------------------------
40
// ####ECOSGPLCOPYRIGHTEND####
41
//==========================================================================
42
//#####DESCRIPTIONBEGIN####
43
//
44
// Author(s):     msalter
45
// Contributors:  msalter, nickg
46
// Date:          2000-12-09
47
// Description:   Definitions for Philips SAA9730 Ethernet module.
48
//
49
//####DESCRIPTIONEND####
50
*/
51
 
52
// QS6612 PHY definitions 
53
 
54
#define PHY_CONTROL                     0
55
#define PHY_STATUS                      1
56
#define PHY_REG31                       31
57
 
58
#define PHY_CONTROL_RESET               (1 << 15)
59
#define PHY_CONTROL_AUTO_NEG            (1 << 12)
60
#define PHY_CONTROL_RESTART_AUTO_NEG    (1 <<  9)
61
 
62
#define PHY_STATUS_LINK_UP              (1 << 2)
63
 
64
#define PHY_REG31_OPMODE_SHIFT           2
65
#define PHY_REG31_OPMODE_MSK             (7 << PHY_REG31_OPMODE_SHIFT)
66
 
67
#define OPMODE_AUTONEGOTIATE             0
68
#define OPMODE_10BASET_HALFDUPLEX        1
69
#define OPMODE_100BASEX_HALFDUPLEX       2
70
#define OPMODE_REPEATER_MODE             3
71
#define OPMODE_UNDEFINED                 4
72
#define OPMODE_10BASET_FULLDUPLEX        5
73
#define OPMODE_100BASEX_FULLDUPLEX       6
74
#define OPMODE_ISOLATE                   7
75
 
76
#define QS6612_PHY_ADDRESS              0
77
#define PHY_ADDRESS                     QS6612_PHY_ADDRESS
78
 
79
// Number of 6-byte entries in the CAM
80
#define SAA9730_CAM_ENTRIES                       10
81
 
82
// TX and RX packet size fixed at 2k bytes by hw
83
#define SAA9730_PACKET_SIZE   2048
84
 
85
// Number of TX buffers = number of RX buffers = 2,
86
// which is fixed according to HW requirements
87
#define SAA9730_BUFFERS                           2
88
 
89
// Number of RX packets per RX buffer
90
#define SAA9730_RXPKTS_PER_BUFFER                2
91
 
92
// Number of TX packets per TX buffer
93
#define SAA9730_TXPKTS_PER_BUFFER                1
94
 
95
// Minimum packet size
96
#define SAA9730_MIN_PACKET_SIZE                   60
97
 
98
// owner ship bit
99
#define SAA9730_BLOCK_OWNED_BY_SYSTEM             0
100
#define SAA9730_BLOCK_OWNED_BY_HARDWARE           1
101
 
102
// Default Rcv interrupt count
103
#define SAA9730_DEFAULT_RCV_INTERRUPT_CNT         4
104
 
105
// Default maxium transmit retry
106
#define SAA9730_DEFAULT_MAX_TXM_RETRY         16
107
 
108
// Default time out value
109
#define SAA9730_DEFAULT_TIME_OUT_CNT              200
110
 
111
// MAX map registers
112
#define SAA9730__MAX_MAP_REGISTERS                    64
113
 
114
// Defines used by Interrupt code
115
#define  SAA9730_DMA_PACKET_SIZE                  2048
116
#define  SAA9730_VALID_PACKET                     0xC0000000
117
#define  SAA9730_FRAME_TYPELEN_OFFSET             12
118
#define  SAA9730_ETH_MIN_FRAME_SIZE               60
119
#define  SAA9730_DEST_ADDR_SIZE                   6
120
#define  SAA9730_SRC_ADDR_SIZE                    6
121
#define  SAA9730_TYPE_LEN_SIZE                    2
122
 
123
// MAC receive error
124
#define  SAA9730_MAC_GOOD_RX                      (0x00004000) << 11
125
#define  SAA9730_MAC_RCV_ALIGN_ERROR              (0x00000100) << 11
126
#define  SAA9730_MAC_RCV_CRC_ERROR                (0x00000200) << 11
127
#define  SAA9730_MAC_RCV_OVERFLOW                 (0x00000400) << 11
128
 
129
// This number is arbitrary and can be increased if needed
130
#define SAA9730_MAX_MULTICAST_ADDRESSES           20 
131
 
132
// SAA9730 Event Manager Registers
133
#define SAA9730_EVM_ISR         *((volatile unsigned *)(__base + 0x02000))
134
#define SAA9730_EVM_IER         *((volatile unsigned *)(__base + 0x02004))
135
#define SAA9730_EVM_IMR         *((volatile unsigned *)(__base + 0x02008))
136
 
137
#define SAA9730_EVM_IER_SW      *((volatile unsigned *)(__base + 0x0202c))
138
 
139
#define SAA9730_EVM_LAN_INT     (1<<16)         // LAN interrupt bit
140
#define SAA9730_EVM_MASTER      (1<<0)          // Master interrupt bit
141
 
142
//  SAA9730 LAN Registers
143
#define SAA9730_TXBUFA          *((volatile unsigned *)(__base + 0x20400)) // TX buffer A
144
 
145
#define SAA9730_TXBUFB          *((volatile unsigned *)(__base + 0x20404)) // TX buffer B
146
 
147
#define SAA9730_RXBUFA          *((volatile unsigned *)(__base + 0x20408)) // RX buffer A
148
 
149
#define SAA9730_RXBUFB          *((volatile unsigned *)(__base + 0x2040C)) // RX buffer B
150
 
151
#define SAA9730_PKTCNT          *((volatile unsigned *)(__base + 0x20410)) // Packet count
152
 
153
#define SAA9730_OK2USE          *((volatile unsigned *)(__base + 0x20414)) // OK-to-use
154
#  define SAA9730_OK2USE_TXA  8            
155
#  define SAA9730_OK2USE_TXB  4            
156
#  define SAA9730_OK2USE_RXA  2            
157
#  define SAA9730_OK2USE_RXB  1            
158
 
159
#define SAA9730_DMACTL          *((volatile unsigned *)(__base + 0x20418)) // DMA control
160
#  define SAA9730_DMACTL_BLKINT           (1 << 31)
161
#  define SAA9730_DMACTL_MAXXFER_ANY      (0 << 18)
162
#  define SAA9730_DMACTL_MAXXFER_8        (1 << 18)
163
#  define SAA9730_DMACTL_MAXXFER_32       (2 << 18)
164
#  define SAA9730_DMACTL_MAXXFER_64       (3 << 18)
165
#  define SAA9730_DMACTL_ENDIAN_LITTLE    (0 << 16)
166
#  define SAA9730_DMACTL_ENDIAN_2143      (1 << 16)
167
#  define SAA9730_DMACTL_ENDIAN_4321      (2 << 16)
168
#  define SAA9730_DMACTL_RXINTCNT_SHIFT   8
169
#  define SAA9730_DMACTL_RXINTCNT_MSK     (0xff << SAA9730_DMACTL_RXINTCNT_SHIFT)
170
#  define SAA9730_DMACTL_ENTX             (1 << 7)
171
#  define SAA9730_DMACTL_ENRX             (1 << 6)
172
#  define SAA9730_DMACTL_RXFULL           (1 << 5)
173
#  define SAA9730_DMACTL_RXTOINT          (1 << 4)
174
#  define SAA9730_DMACTL_RXINT            (1 << 3)
175
#  define SAA9730_DMACTL_TXINT            (1 << 2)
176
#  define SAA9730_DMACTL_MACTXINT         (1 << 1)
177
#  define SAA9730_DMACTL_MACRXINT         (1 << 0)
178
 
179
#define SAA9730_TIMOUT          *((volatile unsigned *)(__base + 0x2041C)) // Time out
180
 
181
#define SAA9730_DMASTA          *((volatile unsigned *)(__base + 0x20420)) // DMA status
182
#  define SAA9730_DMASTA_TXABADR_MSK          (1 << 19)
183
#  define SAA9730_DMASTA_TXBBADR_MSK          (1 << 18)
184
#  define SAA9730_DMASTA_RXABADR_MSK          (1 << 17)
185
#  define SAA9730_DMASTA_RXBBADR_MSK          (1 << 16)
186
#  define SAA9730_DMASTA_RXBBADR_SHIFT        8
187
#  define SAA9730_DMASTA_RXPCKCNT_MASK        (0xff << SAA9730_DMASTA_RXPCKCNT_SHIFT)
188
#  define SAA9730_DMASTA_TXMACBUSY_MSK        (1 << 7)
189
#  define SAA9730_DMASTA_RXAFULL_MSK          (1 << 6)
190
#  define SAA9730_DMASTA_RXBFULL_MSK          (1 << 5)
191
#  define SAA9730_DMASTA_RXTOINT_MSK          (1 << 4)
192
#  define SAA9730_DMASTA_RXINT_MSK            (1 << 3)
193
#  define SAA9730_DMASTA_TXINT_MSK            (1 << 2)
194
#  define SAA9730_DMASTA_MACTXINT_MSK         (1 << 1)
195
#  define SAA9730_DMASTA_MACRXINT_MSK         (1 << 0)
196
 
197
#define SAA9730_DMATST          *((volatile unsigned *)(__base + 0x20424)) // DMA loop back
198
#  define SAA9730_DMATST_LPBACK           (1 << 24)
199
#  define SAA9730_DMATST_RESET            1
200
 
201
#define SAA9730_PAUSE           *((volatile unsigned *)(__base + 0x20430)) // Pause count
202
 
203
#define SAA9730_REMPAUSE        *((volatile unsigned *)(__base + 0x20434)) // Remote Pause count
204
 
205
#define SAA9730_MACCTL          *((volatile unsigned *)(__base + 0x20440)) // MAC control
206
#  define SAA9730_MACCTL_MISSRINT         (1 << 13)
207
#  define SAA9730_MACCTL_MISSROLL         (1 << 10)
208
#  define SAA9730_MACCTL_LOOP10           (1 << 7)
209
#  define SAA9730_MACCTL_CONMODE_AUTOMATIC  (0 << 5)
210
#  define SAA9730_MACCTL_CONMODE_FORCE_10MB (1 << 5)
211
#  define SAA9730_MACCTL_CONMODE_FORCE_MII  (2 << 5)
212
#  define SAA9730_MACCTL_LPBACK           (1 << 4)
213
#  define SAA9730_MACCTL_FULLDUP          (1 << 3)
214
#  define SAA9730_MACCTL_RESET            (1 << 2)
215
#  define SAA9730_MACCTL_HALTNOW          (1 << 1)
216
#  define SAA9730_MACCTL_HALTREQ          (1 << 0)
217
 
218
#define SAA9730_CAMCTL          *((volatile unsigned *)(__base + 0x20444)) // CAM control
219
#  define SAA9730_CAMCTL_COMPARE          (1 << 4)
220
#  define SAA9730_CAMCTL_NEGATE           (1 << 3)
221
#  define SAA9730_CAMCTL_BROADCAST        (1 << 2)
222
#  define SAA9730_CAMCTL_MULTICAST        (1 << 1)
223
#  define SAA9730_CAMCTL_UNICAST          (1 << 0)
224
 
225
#define SAA9730_TXCTL           *((volatile unsigned *)(__base + 0x20448)) // TX control
226
#  define SAA9730_TXCTL_COMPLINT            (1 << 14)
227
#  define SAA9730_TXCTL_TXPARINT            (1 << 13)
228
#  define SAA9730_TXCTL_LATECOLLINT         (1 << 12)
229
#  define SAA9730_TXCTL_EXCOLLINT           (1 << 11)
230
#  define SAA9730_TXCTL_CARRIERINT          (1 << 10)
231
#  define SAA9730_TXCTL_DEFERINT            (1 << 9)
232
#  define SAA9730_TXCTL_UNDERINT            (1 << 8)
233
#  define SAA9730_TXCTL_MII10               (1 << 7)
234
#  define SAA9730_TXCTL_SDPAUSE             (1 << 6)
235
#  define SAA9730_TXCTL_NOEXDEF             (1 << 5)
236
#  define SAA9730_TXCTL_FBACK               (1 << 4)
237
#  define SAA9730_TXCTL_NOCRC               (1 << 3)
238
#  define SAA9730_TXCTL_NOPAD               (1 << 2)
239
#  define SAA9730_TXCTL_TXHALT              (1 << 1)
240
#  define SAA9730_TXCTL_ENTX                (1 << 0)
241
 
242
#define SAA9730_TXSTA           *((volatile unsigned *)(__base + 0x2044C)) // TX status
243
#  define SAA9730_TXSTA_SQERR             (1 << 16)
244
#  define SAA9730_TXSTA_TXHALTED          (1 << 15)
245
#  define SAA9730_TXSTA_COMPLETION        (1 << 14)
246
#  define SAA9730_TXSTA_PARITYERR         (1 << 13)
247
#  define SAA9730_TXSTA_LATECOLLERR       (1 << 12)
248
#  define SAA9730_TXSTA_WAS10MB           (1 << 11)
249
#  define SAA9730_TXSTA_LOSTCARRIER       (1 << 10)
250
#  define SAA9730_TXSTA_EXDEFER           (1 << 9)
251
#  define SAA9730_TXSTA_UNDERRUN          (1 << 8)
252
#  define SAA9730_TXSTA_INTERRUPT         (1 << 7)
253
#  define SAA9730_TXSTA_PAUSED            (1 << 6)
254
#  define SAA9730_TXSTA_DEFERRED          (1 << 5)
255
#  define SAA9730_TXSTA_EXCOLL            (1 << 4)
256
#  define SAA9730_TXSTA_COLLISIONS_MASK   0xf
257
 
258
#define SAA9730_RXCTL           *((volatile unsigned *)(__base + 0x20450)) // RX control
259
#  define SAA9730_RXCTL_ENGOOD            (1 << 14)
260
#  define SAA9730_RXCTL_ENPARITY          (1 << 13)
261
#  define SAA9730_RXCTL_ENLONGERR         (1 << 11)
262
#  define SAA9730_RXCTL_ENOVER            (1 << 10)
263
#  define SAA9730_RXCTL_ENCRCERR          (1 << 9)
264
#  define SAA9730_RXCTL_ENALIGN           (1 << 8)
265
#  define SAA9730_RXCTL_IGNORECRC         (1 << 6)
266
#  define SAA9730_RXCTL_PASSCTL           (1 << 5)
267
#  define SAA9730_RXCTL_STRIPCRC          (1 << 4)
268
#  define SAA9730_RXCTL_SHORTEN           (1 << 3)
269
#  define SAA9730_RXCTL_LONGEN            (1 << 2)
270
#  define SAA9730_RXCTL_RXHALT            (1 << 1)
271
#  define SAA9730_RXCTL_ENRX              (1 << 0)
272
 
273
#define SAA9730_RXSTA           *((volatile unsigned *)(__base + 0x20454)) // RX status
274
#  define SAA9730_RXSTA_HALTED            (1 << 15)
275
#  define SAA9730_RXSTA_GOOD              (1 << 14)
276
#  define SAA9730_RXSTA_PARITY            (1 << 13)
277
#  define SAA9730_RXSTA_LONGERR           (1 << 11)
278
#  define SAA9730_RXSTA_OVERFLOW          (1 << 10)
279
#  define SAA9730_RXSTA_CRCERR            (1 << 9)
280
#  define SAA9730_RXSTA_ALIGNERR          (1 << 8)
281
#  define SAA9730_RXSTA_WAS10MB           (1 << 7)
282
#  define SAA9730_RXSTA_INTERRUPT         (1 << 6)
283
#  define SAA9730_RXSTA_CONTROLRCV        (1 << 5)
284
 
285
#define SAA9730_MDDATA          *((volatile unsigned *)(__base + 0x20458)) // PHY mgmt data
286
#  define SAA9730_MDDATA_DATA_MASK             (0xffff << SAA9730_MDDATA_DATA_SHIFT)
287
 
288
#define SAA9730_MDCTL           *((volatile unsigned *)(__base + 0x2045C)) // PHY mgmt control
289
#  define SAA9730_MDCTL_PRESUP            (1 << 12)
290
#  define SAA9730_MDCTL_BUSY              (1 << 11)
291
#  define SAA9730_MDCTL_WRITE             (1 << 10)
292
#  define SAA9730_MDCTL_PHY_SHIFT         5
293
#  define SAA9730_MDCTL_PHY_MASK          (0x1f << SAA9730_MDCTL_PHY_SHIFT)
294
#  define SAA9730_MDCTL_ADDR_MASK         0x1f
295
 
296
#define SAA9730_CAMADR          *((volatile unsigned *)(__base + 0x20460)) // CAM address
297
#  define SAA9730_CAMADR_ADDRESS_MASK          (0x1ff << SAA9730_CAMADR_ADDRESS_SHIFT)
298
 
299
#define SAA9730_CAMDAT          *((volatile unsigned *)(__base + 0x20464)) // CAM data
300
 
301
#define SAA9730_CAMENA          *((volatile unsigned *)(__base + 0x20468)) // CAM enable
302
#  define SAA9730_CAMENA_ENABLE_MASK          (0x3fffff << SAA9730_CAMENA_ENABLE_SHIFT)
303
 
304
#define SAA9730_DBGRXS          *((volatile unsigned *)(__base + 0x20508)) // DEBUG
305
#  define SAA9730_DBGRXS_RXPI_MASK           (0x3ff << 16)
306
#  define SAA9730_DBGRXS_RXPI_ERROR          (0x001 << 16)
307
#  define SAA9730_DBGRXS_RXDII_MASK          0x1ff
308
#  define SAA9730_DBGRXS_RXDII_ERROR         8
309
 
310
 
311
#define SAA9730_DBGRXFIFO       *((volatile unsigned *)(__base + 0x20510)) // DEBUG
312
 
313
#define SAA9730_DBGLANSTA       *((volatile unsigned *)(__base + 0x20514)) // DEBUG
314
 
315
// ******** Packet control/status **********
316
 
317
#define TXPACKET_CTL_FLAG_MASK      (0x3 << 30)
318
#  define TX_EMPTY                  (0 << 30)
319
#  define TX_READY                  (2 << 30)
320
#  define TX_HWDONE                 (3 << 30)
321
 
322
#  define TXPACKET_CTL_IRQ_MASK     (1 << 29)
323
#  define TXPACKET_CTL_NOCRC_MASK   (1 << 28)
324
#  define TXPACKET_CTL_NOPAD_MASK   (1 << 27)
325
#  define TXPACKET_CTL_SIZE_MASK    0x7ff
326
 
327
#define TXPACKET_STATUS_FLAG_MASK     (0x3 << 30)
328
#  define TXPACKET_STATUS_SQERR       (1 << 27)
329
#  define TXPACKET_STATUS_TXHALTED    (1 << 26)
330
#  define TXPACKET_STATUS_COMPLETION  (1 << 25)
331
#  define TXPACKET_STATUS_PARITYERR   (1 << 24)
332
#  define TXPACKET_STATUS_LATECOLLERR (1 << 23)
333
#  define TXPACKET_STATUS_WAS10MB     (1 << 22)
334
#  define TXPACKET_STATUS_LOSTCARRIER (1 << 21)
335
#  define TXPACKET_STATUS_EXDEFER     (1 << 20)
336
#  define TXPACKET_STATUS_UNDERRUN    (1 << 19)
337
#  define TXPACKET_STATUS_COLLISIONS_SHIFT 11
338
#  define TXPACKET_STATUS_COLLISIONS_MASK  (0x1f << TXPACKET_STATUS_COLLISIONS_SHIFT)
339
#  define TXPACKET_STATUS_SIZE_MASK   0x7ff
340
 
341
#  define TXPACKET_STATUS_ERROR  (TXPACKET_STATUS_EXDEFER      | \
342
                                  TXPACKET_STATUS_LATECOLLERR  | \
343
                                  TXPACKET_STATUS_LOSTCARRIER  | \
344
                                  TXPACKET_STATUS_UNDERRUN     | \
345
                                  TXPACKET_STATUS_SQERR)
346
 
347
#  define RXPACKET_STATUS_FLAG_MASK       (0x3 << 30)
348
#  define RX_NDIS                         (0 << 30)
349
#  define RX_INVALID_STAT                 (1 << 30)
350
#  define RX_READY                        (2 << 30)
351
#  define RX_HWDONE                       (3 << 30)
352
 
353
#  define RXPACKET_STATUS_GOOD        (1 << 25)
354
#  define RXPACKET_STATUS_PARITY      (1 << 24)
355
#  define RXPACKET_STATUS_LONGERR     (1 << 22)
356
#  define RXPACKET_STATUS_OVERFLOW    (1 << 21)
357
#  define RXPACKET_STATUS_CRCERR      (1 << 20)
358
#  define RXPACKET_STATUS_ALIGNERR    (1 << 19)
359
#  define RXPACKET_STATUS_WAS10MB     (1 << 18)
360
#  define RXPACKET_STATUS_SIZE_MASK   0x7ff
361
 
362
#endif  // CYGONCE_DEVS_ETH_MIPS_ATLAS_SAA9730_H

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.