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//==========================================================================
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//
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// dev/KSZ8041.c
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//
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// Ethernet transceiver (PHY) support for Micrel KSZ8041
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2008 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Uwe Kindler <uwe_kindler@web.de>
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// Contributors: oli@snr.ch
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// Date: 2008-09-18
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// Purpose:
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// Description: Support for ethernet PHY Micrel KSZ8041
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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//==========================================================================
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// INCLUDES
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//==========================================================================
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#include <pkgconf/system.h>
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#include <pkgconf/devs_eth_phy.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/hal_arch.h>
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#include <cyg/hal/drv_api.h>
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#include <cyg/hal/hal_if.h>
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#include <cyg/hal/hal_tables.h>
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#include <cyg/io/eth_phy.h>
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#include <cyg/io/eth_phy_dev.h>
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//==========================================================================
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// DEFINES
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//==========================================================================
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// 100BASE-TX PHY Control Register
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#define PHY_100BASE_CTRL 0x1f
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#define PHY_100BASE_CTRL_OP_MODE_MASK (0x07 << 2)
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#define PHY_100BASE_CTRL_AN_MODE (0x00 << 2)
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#define PHY_100BASE_CTRL_10T_HDX (0x01 << 2)
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#define PHY_100BASE_CTRL_100T_HDX (0x02 << 2)
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#define PHY_100BASE_CTRL_DEFAULT (0x03 << 2)
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#define PHY_100BASE_CTRL_10T_FDX (0x05 << 2)
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#define PHY_100BASE_CTRL_100T_FDX (0x06 << 2)
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//==========================================================================
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// Query the 100BASE-TX PHY Control Register and return a status bitmap
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// indicating the state of the physical connection
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//==========================================================================
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#ifdef CYGDBG_DEVS_ETH_PHY
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void
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ksz8041_diag (eth_phy_access_t * f)
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{
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cyg_uint32 i;
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cyg_uint16 reg;
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eth_phy_printf ("KSZ8041 MIIM Register setings:\n");
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for (i = 0; i < 0x20; i++) {
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if (i % 2 == 0) {
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_eth_phy_read (f, i, f->phy_addr, ®);
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eth_phy_printf ("r%02x: %04x ", i, reg);
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} else {
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_eth_phy_read (f, i, f->phy_addr, ®);
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eth_phy_printf ("%04x\n", reg);
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}
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}
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}
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#endif
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static bool
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ksz8041_stat (eth_phy_access_t * f, int *state)
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{
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cyg_uint16 phy_state;
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cyg_uint16 phy_100ctrl_reg;
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cyg_uint32 tries;
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cyg_uint32 ms;
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#ifdef CYGDBG_DEVS_ETH_PHY
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ksz8041_diag (f);
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#endif
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if (_eth_phy_read (f, PHY_BMSR, f->phy_addr, &phy_state)) {
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if ((phy_state & PHY_BMSR_AUTO_NEG) == 0) {
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eth_phy_printf ("... waiting for auto-negotiation");
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for (tries = 0; tries < CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME;
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tries++) {
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if (_eth_phy_read (f, PHY_BMSR, f->phy_addr, &phy_state)) {
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if ((phy_state & PHY_BMSR_AUTO_NEG) != 0) {
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break;
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}
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} else {
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eth_phy_printf ("error: _eth_phy_read()\n");
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}
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//
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// Wait for 1 second
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//
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for (ms = 0; ms < 1000; ++ms) {
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CYGACC_CALL_IF_DELAY_US (1000); // 1 ms
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}
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eth_phy_printf (".");
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}
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eth_phy_printf ("\n");
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}
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if ((phy_state & PHY_BMSR_AUTO_NEG) != 0) {
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*state = 0;
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if ((phy_state & PHY_BMSR_LINK) != 0) {
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*state |= ETH_PHY_STAT_LINK;
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}
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_eth_phy_read (f, PHY_100BASE_CTRL, f->phy_addr, &phy_100ctrl_reg);
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phy_100ctrl_reg &= PHY_100BASE_CTRL_OP_MODE_MASK;
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switch (phy_100ctrl_reg) {
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case PHY_100BASE_CTRL_10T_HDX:
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break;
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case PHY_100BASE_CTRL_100T_HDX:
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*state |= ETH_PHY_STAT_100MB;
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break;
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case PHY_100BASE_CTRL_10T_FDX:
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*state |= ETH_PHY_STAT_FDX;
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break;
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case PHY_100BASE_CTRL_100T_FDX:
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*state |= ETH_PHY_STAT_100MB | ETH_PHY_STAT_FDX;
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break;
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default:
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// force to set default 100 Full Duplex
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*state |= ETH_PHY_STAT_100MB | ETH_PHY_STAT_FDX;
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} // switch (phy_100ctrl_reg)
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return true;
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}
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}
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return false;
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}
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_eth_phy_dev ("Micrel KSZ8041", 0x00221512, ksz8041_stat)
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_eth_phy_dev ("Micrel KSZ8041", 0x00221513, ksz8041_stat)
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