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//==========================================================================
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//
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// devs_eth_powerpc_ec555.inl
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//
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// ec555 ethernet I/O definitions.
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Bob Koninckx
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// Contributors:Bob Koninckx
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// Date: 2002-11-20
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// Purpose: ec555 ethernet defintions
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//
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//####DESCRIPTIONEND####
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//==========================================================================
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#include
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#include
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#ifdef CYGPKG_REDBOOT
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# include
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# ifdef CYGSEM_REDBOOT_FLASH_CONFIG
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# include
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# include
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# endif
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#endif
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#ifdef __WANT_CONFIG
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# define CS8900A_step 2
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#endif
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#ifdef __WANT_DEVS
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#ifdef CYGPKG_DEVS_ETH_POWERPC_EC555_ETH0
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#ifndef CYGSEM_DEVS_ETH_POWERPC_EC555_ETH0_SET_ESA
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# if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
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RedBoot_config_option("Set " CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_NAME " network hardware address [MAC]",
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eth0_esa,
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ALWAYS_ENABLED, true,
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CONFIG_BOOL, false
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);
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RedBoot_config_option(CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_NAME " network hardware address [MAC]",
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eth0_esa_data,
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"eth0_esa", true,
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CONFIG_ESA, 0
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);
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# endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
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# ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
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// Note that this section *is* active in an application, outside RedBoot,
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// where the above section is not included.
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# include
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# ifndef CONFIG_ESA
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# define CONFIG_ESA (6)
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# endif
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# ifndef CONFIG_BOOL
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# define CONFIG_BOOL (1)
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# endif
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cyg_bool
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_ec555_provide_eth0_esa(struct cs8900a_priv_data* cpd)
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{
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cyg_bool set_esa;
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int ok;
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ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
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"eth0_esa", &set_esa, CONFIG_BOOL);
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if (ok && set_esa) {
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ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
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"eth0_esa_data", cpd->esa, CONFIG_ESA);
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}
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return ok && set_esa;
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}
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# endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
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#endif // ! CYGSEM_DEVS_ETH_POWERPC_EC555_ETH0_SET_ESA
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// ------------------------------------------------------------------------
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// EEPROM access functions
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// These are byte swapped
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#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
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#define PP_ECR 0x4000 // EEPROM Command Register
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#define PP_EE_READ_CMD 0x0002
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#define PP_EE_WRITE_CMD 0x0001
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#define PP_EE_DATA 0x4200
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#else
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#define PP_ECR 0x0040 // EEPROM Command Register
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#define PP_EE_READ_CMD 0x0200
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#define PP_EE_WRITE_CMD 0x0100
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#define PP_EE_DATA 0x0042
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#endif
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#define PP_EE_ADDR_W0 0x001C // Notice that the EEPROM is not programmed when you got the
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#define PP_EE_ADDR_W1 0x001D // Module from Wuerz. Make sure to program the address to these
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#define PP_EE_ADDR_W2 0x001E // locations before using the adapter. This is fairly easy using GDB
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// The example below programs the MAC address 0050 c4ff fc07 to the eeprom, supposed that the module
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// is mapped to adresses 0x0400 0000, and supposed that the data bus is _not_ byte swapped
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//
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// set *(unsigned short *)0x0400030a = 0x0040 Make the eeprom writable / erasable
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// set *(unsigned short *)0x0400030c = 0x0030
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//
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// set *(unsigned short *)0x0400030a = 0x0040 erase the old esa
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// set *(unsigned short *)0x0400030c = 0x031c
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// set *(unsigned short *)0x0400030c = 0x031d
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// set *(unsigned short *)0x0400030c = 0x031e
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//
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// set *(unsigned short *)0x0400030a = 0x0042 program the new esa
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// set *(unsigned short *)0x0400030c = 0x5000
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// set *(unsigned short *)0x0400030a = 0x0040
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// set *(unsigned short *)0x0400030c = 0x011c
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// set *(unsigned short *)0x0400030a = 0x0042
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// set *(unsigned short *)0x0400030c = 0xffc4
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// set *(unsigned short *)0x0400030a = 0x0040
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// set *(unsigned short *)0x0400030c = 0x011d
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// set *(unsigned short *)0x0400030a = 0x0042
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// set *(unsigned short *)0x0400030c = 0x07fc
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// set *(unsigned short *)0x0400030a = 0x0040
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// set *(unsigned short *)0x0400030c = 0x011e
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//
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// set *(unsigned short *)0x0400030a = 0x0040 Write protect the eeprom
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// set *(unsigned short *)0x0400030c = 0x0030
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static __inline__ cyg_uint16
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read_eeprom(cyg_addrword_t base, cyg_uint16 offset)
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{
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while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
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;
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#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
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put_reg(base, PP_ECR, (CYG_SWAP16(offset) | PP_EE_READ_CMD));
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#else
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put_reg(base, PP_ECR, (offset | PP_EE_READ_CMD));
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#endif
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while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
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;
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return get_reg(base, PP_EE_DATA);
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}
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static __inline__ void
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copy_eeprom(cyg_addrword_t base)
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{
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volatile cyg_uint16 esa_word;
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cyg_uint16 i;
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for (i = 0; i < 6; i += 2)
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{ // Offset in the eeprom is WORD oriented, in the packetpage BYTE oriented
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esa_word = read_eeprom(base, PP_EE_ADDR_W0 + (i/2));
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#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
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put_reg(base, (PP_IA + CYG_SWAP16(i)), esa_word);
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#else
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put_reg(base, (PP_IA + i), esa_word);
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#endif
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}
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}
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// Not so nice, but reading these will never conflict on the ec555
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// They certainly differ in A18
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#define FIRSTRAM 0x01000000
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#define LASTRAM 0x010ffffe
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static __inline__ void
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post_reset(cyg_addrword_t base)
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{
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cyg_uint16 tmp;
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// The following must toggle Address line 18, connected to SBHE on the CS8900a
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HAL_READ_UINT16( LASTRAM, tmp);
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HAL_READ_UINT16( FIRSTRAM, tmp);
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HAL_READ_UINT16( LASTRAM, tmp);
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HAL_READ_UINT16( FIRSTRAM, tmp);
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}
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#undef CYGHWR_CL_CS8900A_PLF_POST_RESET
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#define CYGHWR_CL_CS8900A_PLF_POST_RESET(base) post_reset(base)
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#undef CYGHWR_CL_CS8900A_PLF_RESET
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#define CYGHWR_CL_CS8900A_PLF_RESET(base) copy_eeprom(base)
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static cs8900a_priv_data_t cs8900a_eth0_priv_data = {
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base : (cyg_addrword_t) (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_BASE + 0x300),
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interrupt:((CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_IRQ*2)+1),
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#ifdef CYGSEM_DEVS_ETH_POWERPC_EC555_ETH0_SET_ESA
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esa : CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_ESA,
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hardwired_esa : true,
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#else
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hardwired_esa : false,
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# ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
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provide_esa : &_ec555_provide_eth0_esa,
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# else
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provide_esa : NULL,
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# endif
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#endif
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};
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ETH_DRV_SC(cs8900a_sc,
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&cs8900a_eth0_priv_data, // Driver specific data
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CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_NAME,
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cs8900a_start,
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cs8900a_stop,
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cs8900a_control,
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cs8900a_can_send,
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cs8900a_send,
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cs8900a_recv,
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cs8900a_deliver, // "pseudoDSR" called from fast net thread
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cs8900a_poll, // poll function, encapsulates ISR and DSR
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cs8900a_int_vector);
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NETDEVTAB_ENTRY(cs8900a_netdev,
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"cs8900a_" CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_NAME,
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cs8900a_init,
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&cs8900a_sc);
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#endif // CYGPKG_DEVS_ETH_POWERPC_EC555_ETH0
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#endif // __WANT_DEVS
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// EOF devs_eth_powerpc_ec555.inl
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