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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [devs/] [eth/] [powerpc/] [mbx/] [current/] [include/] [mbx_eth.inl] - Blame information for rev 786

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1 786 skrzyp
#ifndef CYGONCE_DEVS_MBX_ETH_INL
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#define CYGONCE_DEVS_MBX_ETH_INL
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//==========================================================================
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//
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//      mbx_eth.inl
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//
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//      Hardware specifics for Motorola MBX ethernet support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    gthomas
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// Contributors: gthomas
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// Date:         2002-11-19
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// Purpose:
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// Description:
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#define _get_led()
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#define _set_led(v)
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#define LED_TxACTIVE  7
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#define LED_RxACTIVE  6
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#define LED_IntACTIVE 5
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#if 0
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// Fetch ESA from on-board EEPROM
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extern int _mbx_fetch_VPD(int, void *, int);
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#define QUICC_ETH_FETCH_ESA(_ok_)                              \
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     _ok_ = _mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr));
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#endif
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// Reset/enable any external hardware
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#define QUICC_ETH_ENABLE()                                     \
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    *MBX_CTL1 = MBX_CTL1_ETEN | MBX_CTL1_TPEN;  /* Enable ethernet, TP mode */
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// Port layout - uses SCC1
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#define QUICC_ETH_PA_RXD            0x0001  // Rx Data on Port A
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#define QUICC_ETH_PA_TXD            0x0002  // Tx Data on Port A
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#define QUICC_ETH_PA_Tx_CLOCK       0x0200  // Tx Clock = CLK2
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#define QUICC_ETH_PA_Rx_CLOCK       0x0800  // Rx Clock = CLK4
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#define QUICC_ETH_PC_Tx_ENABLE      0x0001  // Tx Enable (TENA)
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#define QUICC_ETH_PC_COLLISION      0x0010  // Collision detect
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#define QUICC_ETH_PC_Rx_ENABLE      0x0020  // Rx Enable (RENA)
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#define QUICC_ETH_SICR_MASK         0x00FF  // SI Clock Route - important bits
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#define QUICC_ETH_SICR_ENET  (7<<3)|(5<<0)  //   Rx=CLK4, Tx=CLK2
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#define QUICC_ETH_SICR_ENABLE       0x0040  // Enable SCC1 to use NMSI
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#define QUICC_ETH_INT               CYGNUM_HAL_INTERRUPT_CPM_SCC1
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#define QUICC_ETH_SCC               0       // SCC1
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#define QUICC_CPM_SCCx              QUICC_CPM_SCC1
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#define MBX_CTL1   (cyg_uint8 *)0xFA100000  // System control register
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#define MBX_CTL1_ETEN                 0x80  // 1 = Enable ethernet tranceiver
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#define MBX_CTL1_ELEN                 0x40  // 1 = Enable ethernet loopback
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#define MBX_CTL1_EAEN                 0x20  // 1 = Auto select ethernet interface
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#define MBX_CTL1_TPEN                 0x10  // 0 = AUI, 1 = TPI
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#define MBX_CTL1_FDDIS                0x08  // 1 = Disable full duplex (if TP mode)
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#endif  // CYGONCE_DEVS_MBX_ETH_INL
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// ------------------------------------------------------------------------

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