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skrzyp |
//==========================================================================
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//
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// devs_eth_sh_hs7729pci.inl
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//
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// HS7729PCI ethernet I/O definitions.
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors:jskov
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// Date: 2001-05-31
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// Purpose: HS7729PCI ethernet defintions
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//####DESCRIPTIONEND####
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//==========================================================================
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#include // CYGNUM_HAL_INTERRUPT_ETHR
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#ifdef __WANT_CONFIG
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#define CYGHWR_VIA_RHINE_PCI_MEM_MAP_BASE (CYGARC_UNCACHED_ADDRESS(&CYGMEM_SECTION_pci_window[0]))
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#define CYGHWR_VIA_RHINE_PCI_MEM_MAP_SIZE (CYGMEM_SECTION_pci_window_SIZE)
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#endif // __WANT_CONFIG
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#ifdef __WANT_DEVS
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#ifdef CYGPKG_DEVS_ETH_SH_HS7729PCI_ETH0
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static rhine_priv_data via_rhine_eth0_priv_data = {
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#ifdef CYGSEM_DEVS_ETH_SH_HS7729PCI_ETH0_SET_ESA
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enaddr : CYGDAT_DEVS_ETH_SH_HS7729PCI_ETH0_ESA,
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#endif
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config_esa : NULL, // rely on the hardwired address for now
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rx_ring : NULL,
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rx_ring_cnt : (1<<2) /*CYGNUM_DEVS_ETH_SH_HS7729PCI_ETH0_RX_RING_SIZE*/,
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rx_ring_log_cnt : 2,
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tx_ring : NULL,
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tx_ring_cnt : (1<<2) /*CYGNUM_DEVS_ETH_SH_HS7729PCI_ETH0_TX_RING_SIZE*/,
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tx_ring_log_cnt : 2,
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};
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static rhine_priv_data *rhine_priv_array[1] = {&via_rhine_eth0_priv_data};
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ETH_DRV_SC(via_rhine_sc,
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&via_rhine_eth0_priv_data, // Driver specific data
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CYGDAT_DEVS_ETH_SH_HS7729PCI_ETH0_NAME,
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rhine_start,
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rhine_stop,
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rhine_control,
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rhine_can_send,
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rhine_send,
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rhine_recv,
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rhine_deliver, // "pseudoDSR" called from fast net thread
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rhine_poll, // poll function, encapsulates ISR and DSR
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rhine_int_vector);
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NETDEVTAB_ENTRY(rhine_netdev,
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"rhine_" CYGDAT_DEVS_ETH_SH_HS7729PCI_ETH0_NAME,
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via_rhine_init,
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&via_rhine_sc);
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#endif // CYGPKG_DEVS_ETH_SH_HS7729PCI_ETH0
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#endif // __WANT_DEVS
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// EOF devs_eth_sh_hs7729pci.inl
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