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skrzyp |
//==========================================================================
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//
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// i2c_a2fxxx.c
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//
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// I2C driver for Smartfusion Cortex M3 microcontroller
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2011 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): ccoutand
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// Contributors:
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// Date: 2011-01-18
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// Original: Uwe Kindler, Bart Veer
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// I2C driver for motorola coldfire processor
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// Description: I2C driver for Smartfusion Cortex M3 microcontroller
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// The RX part of the driver has not been tested.
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//
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//####DESCRIPTIONEND####
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//==========================================================================
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#include <pkgconf/system.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/cyg_ass.h>
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#include <cyg/infra/diag.h>
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#include <cyg/io/i2c.h>
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#include <cyg/io/i2c_a2fxxx.h>
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#include <cyg/hal/hal_arch.h>
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#include <cyg/hal/hal_io.h>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/hal/drv_api.h>
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#ifdef CYGDBG_DEVS_I2C_CORTEXM_A2FXXX_TRACE
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# define I2C_TRACE(args...) diag_printf(args)
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#else
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# define I2C_TRACE(args...)
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#endif
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#define I2C_DAT(_base_) (_base_ + CYGHWR_HAL_A2FXXX_I2C_DATA)
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#define I2C_ADR(_base_) (_base_ + CYGHWR_HAL_A2FXXX_I2C_ADDR)
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#define I2C_SR(_base_) (_base_ + CYGHWR_HAL_A2FXXX_I2C_STATUS)
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#define I2C_CR(_base_) (_base_ + CYGHWR_HAL_A2FXXX_I2C_CTRL)
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#define I2C_FREQ(_base_) (_base_ + CYGHWR_HAL_A2FXXX_I2C_FREQ)
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#define I2C_SMBUS(_base_) (_base_ + CYGHWR_HAL_A2FXXX_I2C_SMBUS)
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#define I2C_GLITCH(_base_) (_base_ + CYGHWR_HAL_A2FXXX_I2C_GLITCH)
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// Bit-band definition
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#define I2C_CR_CR0(_base_) (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) + \
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( 0*sizeof(cyg_uint32) ) )
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#define I2C_CR_CR1(_base_) (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) + \
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( 1*sizeof(cyg_uint32) ) )
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#define I2C_CR_AA(_base_) (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) + \
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( 2*sizeof(cyg_uint32) ) )
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#define I2C_CR_SI(_base_) (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) + \
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( 3*sizeof(cyg_uint32) ) )
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#define I2C_CR_STO(_base_) (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) + \
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( 4*sizeof(cyg_uint32) ) )
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#define I2C_CR_STA(_base_) (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) + \
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( 5*sizeof(cyg_uint32) ) )
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#define I2C_CR_ENS1(_base_) (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) + \
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( 6*sizeof(cyg_uint32) ) )
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#define I2C_CR_CR2(_base_) (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) + \
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( 7*sizeof(cyg_uint32) ) )
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#define I2C_MTX_STATE(x) CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_##x
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#define I2C_MRX_STATE(x) CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_##x
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// Divider coefficient
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static const unsigned int i2c_div[] = {
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256,
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224,
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192,
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160,
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960,
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120,
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60,
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8,
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};
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static cyg_uint32
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a2fxxx_i2c_isr(cyg_vector_t vec, cyg_addrword_t data)
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{
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a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) data;
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cyg_uint32 result = CYG_ISR_HANDLED;
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cyg_uint32 sr,
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dr;
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cyg_uint8 tx_data = *extra->i2c_data.i2c_tx_data;
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cyg_uint32 cr = 0;
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// Read the current status of the I2C
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HAL_READ_UINT32(I2C_SR(extra->i2c_base), sr);
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HAL_READ_UINT32(I2C_CR(extra->i2c_base), cr);
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// What to do next depends on the current transfer mode.
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if (A2FXXX_I2C_XFER_MODE_TX == extra->i2c_mode) {
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I2C_TRACE("I2C: TX IRQ handling -> 0x%x\n", sr);
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switch (sr) {
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// Start/Repeated start, write the slave address and clear the
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// START and SI bits
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case I2C_MTX_STATE(START):
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case I2C_MTX_STATE(REPEAT_START):
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HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base), extra->slave_addr);
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cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_STA;
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cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
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break;
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// ACK is received for the address or data, keep sending
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// START and SI bits
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case I2C_MTX_STATE(ADDR_ACK):
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case I2C_MTX_STATE(DATA_ACK):
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if (0 == extra->i2c_count) {
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if (extra->send_stop) {
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cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_STO;
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cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
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} else {
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// For repeated start, we must disable interrupt
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extra->i2c_isr_mask = true;
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}
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// No more bytes to send.
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result |= CYG_ISR_CALL_DSR;
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} else {
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// Send byte
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HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base),
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(cyg_uint32)tx_data);
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extra->i2c_data.i2c_tx_data += 1;
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extra->i2c_count -= 1;
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cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
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}
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break;
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case I2C_MTX_STATE(ARBLOST):
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case I2C_MTX_STATE(DATA_NACK):
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// Lost the bus, abort the transfer. count has already been
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// decremented. Assume the byte did not actually arrive.
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extra->i2c_count += 1;
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case I2C_MTX_STATE(ADDR_NACK):
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// For all error type, clear interrupt and send stop bit
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cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_STO;
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cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
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extra->i2c_got_nack = 1;
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result |= CYG_ISR_CALL_DSR;
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break;
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default:
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HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
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return result;
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}
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} else if (A2FXXX_I2C_XFER_MODE_RX == extra->i2c_mode) {
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I2C_TRACE("I2C: RX IRQ handling -> 0x%x\n", sr);
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cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_AA;
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switch (sr) {
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// Start/Repeated start, write the slave address and clear the
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// START and SI bits
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case I2C_MRX_STATE(START):
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case I2C_MRX_STATE(REPEAT_START):
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HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base), extra->slave_addr);
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cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_STA;
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cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
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break;
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// ACK is received for the address
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case I2C_MRX_STATE(ADDR_ACK):
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if (extra->i2c_count > 1) {
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cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_AA;
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}
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cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
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break;
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// Receive data
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case I2C_MRX_STATE(DATA_ACK):
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case I2C_MRX_STATE(DATA_NACK):
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cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
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if (extra->i2c_count > 2) {
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cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_AA;
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}
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if (1 == extra->i2c_count) {
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if (extra->send_stop) {
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cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_STO;
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} else {
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// For repeated start, we must disable interrupt
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cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
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extra->i2c_isr_mask = true;
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}
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// Received the last byte.
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result |= CYG_ISR_CALL_DSR;
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}
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HAL_READ_UINT32(I2C_DAT(extra->i2c_base), dr);
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*(extra->i2c_data.i2c_rx_data) = (cyg_uint8)dr;
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extra->i2c_data.i2c_rx_data += 1;
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extra->i2c_count -= 1;
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break;
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| 220 |
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case I2C_MRX_STATE(ARBLOST):
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| 221 |
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case I2C_MRX_STATE(ADDR_NACK):
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// Lost the bus? Maybe a spurious stop
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| 223 |
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cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_STO;
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| 224 |
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result |= CYG_ISR_CALL_DSR;
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| 225 |
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break;
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| 226 |
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default:
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| 227 |
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HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
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| 228 |
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return result;
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| 229 |
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}
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| 230 |
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} else {
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| 231 |
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// Invalid state? Some kind of spurious interrupt?
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| 232 |
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// Just ignore it.
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| 233 |
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I2C_TRACE("I2C spurious interrupt\n");
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| 234 |
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}
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| 235 |
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| 236 |
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HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), cr);
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| 237 |
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| 238 |
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HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
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| 239 |
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| 240 |
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if (extra->i2c_isr_mask)
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| 241 |
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HAL_INTERRUPT_MASK(extra->i2c_isr_id);
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| 242 |
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| 243 |
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return result;
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| 244 |
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}
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| 245 |
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| 246 |
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| 247 |
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static void
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| 248 |
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a2fxxx_i2c_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
|
| 249 |
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{
|
| 250 |
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a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) data;
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| 251 |
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extra->i2c_completed = 1;
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| 252 |
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cyg_drv_cond_signal(&(extra->i2c_wait));
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| 253 |
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}
|
| 254 |
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| 255 |
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|
| 256 |
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// A transfer has been started. Wait for completion
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| 257 |
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static inline void
|
| 258 |
|
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a2fxxx_i2c_doit(a2fxxx_i2c_extra * extra)
|
| 259 |
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{
|
| 260 |
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cyg_drv_mutex_lock(&(extra->i2c_lock));
|
| 261 |
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cyg_drv_dsr_lock();
|
| 262 |
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while (!extra->i2c_completed) {
|
| 263 |
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cyg_drv_cond_wait(&(extra->i2c_wait));
|
| 264 |
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}
|
| 265 |
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cyg_drv_dsr_unlock();
|
| 266 |
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cyg_drv_mutex_unlock(&(extra->i2c_lock));
|
| 267 |
|
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}
|
| 268 |
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|
| 269 |
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|
| 270 |
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static inline void
|
| 271 |
|
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a2fxxx_i2c_stopit(a2fxxx_i2c_extra * extra)
|
| 272 |
|
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{
|
| 273 |
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extra->i2c_lost_arb = 0;
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| 274 |
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extra->i2c_owner = 0;
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| 275 |
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extra->i2c_mode = A2FXXX_I2C_XFER_MODE_INVALID;
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| 276 |
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}
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| 277 |
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| 278 |
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| 279 |
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void
|
| 280 |
|
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a2fxxx_i2c_stop(const cyg_i2c_device * dev)
|
| 281 |
|
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{
|
| 282 |
|
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a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) dev->i2c_bus->i2c_extra;
|
| 283 |
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a2fxxx_i2c_stopit(extra);
|
| 284 |
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}
|
| 285 |
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|
| 286 |
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|
| 287 |
|
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cyg_uint32
|
| 288 |
|
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a2fxxx_i2c_tx(const cyg_i2c_device * dev, cyg_bool send_start,
|
| 289 |
|
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const cyg_uint8 *tx_data, cyg_uint32 count, cyg_bool send_stop)
|
| 290 |
|
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{
|
| 291 |
|
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a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) dev->i2c_bus->i2c_extra;
|
| 292 |
|
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extra->send_stop = send_stop;
|
| 293 |
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extra->send_start = send_start;
|
| 294 |
|
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extra->i2c_count = count;
|
| 295 |
|
|
extra->slave_addr = ((dev->i2c_address << 1) | 0x00);
|
| 296 |
|
|
cyg_uint32 si = 0;
|
| 297 |
|
|
|
| 298 |
|
|
if (!extra->i2c_lost_arb) {
|
| 299 |
|
|
extra->i2c_completed = 0;
|
| 300 |
|
|
extra->i2c_mode = A2FXXX_I2C_XFER_MODE_TX;
|
| 301 |
|
|
|
| 302 |
|
|
if (send_start || !extra->i2c_got_nack) {
|
| 303 |
|
|
I2C_TRACE
|
| 304 |
|
|
("I2C: TX to %2x, data %2x, count: %4d, START flag: %s, STOP flag: %s\n",
|
| 305 |
|
|
dev->i2c_address, *tx_data, count,
|
| 306 |
|
|
(send_start == true) ? "true" : "false",
|
| 307 |
|
|
(send_stop == true) ? "true" : "false");
|
| 308 |
|
|
extra->i2c_data.i2c_tx_data = tx_data;
|
| 309 |
|
|
HAL_READ_UINT32(I2C_CR_SI(extra->i2c_base_bb), si);
|
| 310 |
|
|
// Set start bit
|
| 311 |
|
|
HAL_WRITE_UINT32(I2C_CR_STA(extra->i2c_base_bb),
|
| 312 |
|
|
CYGHWR_HAL_A2FXXX_BITSET);
|
| 313 |
|
|
// For repeated start, we need to clear the interrupt
|
| 314 |
|
|
if (si != 0) {
|
| 315 |
|
|
HAL_WRITE_UINT32(I2C_CR_SI(extra->i2c_base_bb),
|
| 316 |
|
|
CYGHWR_HAL_A2FXXX_BITCLEAR);
|
| 317 |
|
|
HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
|
| 318 |
|
|
}
|
| 319 |
|
|
// For repeated start, we need to un-mask the interrupt
|
| 320 |
|
|
if (extra->i2c_isr_mask) {
|
| 321 |
|
|
extra->i2c_isr_mask = false;
|
| 322 |
|
|
HAL_INTERRUPT_UNMASK(extra->i2c_isr_id);
|
| 323 |
|
|
}
|
| 324 |
|
|
a2fxxx_i2c_doit(extra);
|
| 325 |
|
|
}
|
| 326 |
|
|
|
| 327 |
|
|
}
|
| 328 |
|
|
if (send_stop) {
|
| 329 |
|
|
I2C_TRACE("I2C: TX send stop\n");
|
| 330 |
|
|
a2fxxx_i2c_stopit(extra);
|
| 331 |
|
|
}
|
| 332 |
|
|
|
| 333 |
|
|
I2C_TRACE("I2C: TX count %d\n", extra->i2c_count);
|
| 334 |
|
|
|
| 335 |
|
|
// tx() should return the number of bytes actually transmitted.
|
| 336 |
|
|
// ISR() increments extra->count after a failure, which leads to
|
| 337 |
|
|
// an edge condition when send_start and there is no acknowledgment
|
| 338 |
|
|
// of the address byte.
|
| 339 |
|
|
if (extra->i2c_count > count) {
|
| 340 |
|
|
return 0;
|
| 341 |
|
|
}
|
| 342 |
|
|
|
| 343 |
|
|
return count - extra->i2c_count;
|
| 344 |
|
|
}
|
| 345 |
|
|
|
| 346 |
|
|
|
| 347 |
|
|
cyg_uint32
|
| 348 |
|
|
a2fxxx_i2c_rx(const cyg_i2c_device * dev, cyg_bool send_start,
|
| 349 |
|
|
cyg_uint8 *rx_data, cyg_uint32 count, cyg_bool send_nack,
|
| 350 |
|
|
cyg_bool send_stop)
|
| 351 |
|
|
{
|
| 352 |
|
|
a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) dev->i2c_bus->i2c_extra;
|
| 353 |
|
|
extra->i2c_send_nack = send_nack;
|
| 354 |
|
|
extra->i2c_count = count;
|
| 355 |
|
|
extra->send_stop = send_stop;
|
| 356 |
|
|
extra->send_start = send_start;
|
| 357 |
|
|
extra->slave_addr = ((dev->i2c_address << 1) | 0x01);
|
| 358 |
|
|
cyg_uint32 si = 0;
|
| 359 |
|
|
|
| 360 |
|
|
if (!extra->i2c_lost_arb) {
|
| 361 |
|
|
extra->i2c_completed = 0;
|
| 362 |
|
|
extra->i2c_data.i2c_rx_data = rx_data;
|
| 363 |
|
|
extra->i2c_mode = A2FXXX_I2C_XFER_MODE_RX;
|
| 364 |
|
|
I2C_TRACE
|
| 365 |
|
|
("I2C: RX to %2x, count: %4d, START flag: %s, STOP flag: %s\n",
|
| 366 |
|
|
dev->i2c_address, count, (send_start == true) ? "true" : "false",
|
| 367 |
|
|
(send_stop == true) ? "true" : "false");
|
| 368 |
|
|
HAL_READ_UINT32(I2C_CR_SI(extra->i2c_base_bb), si);
|
| 369 |
|
|
// Set start bit
|
| 370 |
|
|
HAL_WRITE_UINT32(I2C_CR_STA(extra->i2c_base_bb),
|
| 371 |
|
|
CYGHWR_HAL_A2FXXX_BITSET);
|
| 372 |
|
|
// For repeated start, we need to clear the interrupt
|
| 373 |
|
|
if (si != 0) {
|
| 374 |
|
|
HAL_WRITE_UINT32(I2C_CR_SI(extra->i2c_base_bb),
|
| 375 |
|
|
CYGHWR_HAL_A2FXXX_BITCLEAR);
|
| 376 |
|
|
HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
|
| 377 |
|
|
}
|
| 378 |
|
|
// For repeated start, we need to un-mask the interrupt
|
| 379 |
|
|
if (extra->i2c_isr_mask) {
|
| 380 |
|
|
extra->i2c_isr_mask = false;
|
| 381 |
|
|
HAL_INTERRUPT_UNMASK(extra->i2c_isr_id);
|
| 382 |
|
|
}
|
| 383 |
|
|
a2fxxx_i2c_doit(extra);
|
| 384 |
|
|
}
|
| 385 |
|
|
|
| 386 |
|
|
if (send_stop) {
|
| 387 |
|
|
I2C_TRACE("I2C: RX send stop\n");
|
| 388 |
|
|
a2fxxx_i2c_stopit(extra);
|
| 389 |
|
|
}
|
| 390 |
|
|
|
| 391 |
|
|
return count - extra->i2c_count;
|
| 392 |
|
|
}
|
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
// ----------------------------------------------------------------------------
|
| 396 |
|
|
// The functions needed for all I2C devices.
|
| 397 |
|
|
|
| 398 |
|
|
void
|
| 399 |
|
|
a2fxxx_i2c_init(struct cyg_i2c_bus *bus)
|
| 400 |
|
|
{
|
| 401 |
|
|
a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) bus->i2c_extra;
|
| 402 |
|
|
cyg_uint8 div = 0;
|
| 403 |
|
|
#ifdef CYGDBG_DEVS_I2C_CORTEXM_A2FXXX_TRACE
|
| 404 |
|
|
cyg_uint32 i2c_freq =
|
| 405 |
|
|
((hal_a2fxxx_i2c_clock(extra->i2c_base) /
|
| 406 |
|
|
CYGNUM_HAL_CORTEXM_A2FXXX_I2C_CLK_DIV));
|
| 407 |
|
|
#endif
|
| 408 |
|
|
|
| 409 |
|
|
while ((i2c_div[div] != CYGNUM_HAL_CORTEXM_A2FXXX_I2C_CLK_DIV) &&
|
| 410 |
|
|
i2c_div[div] != 0) {
|
| 411 |
|
|
div++;
|
| 412 |
|
|
}
|
| 413 |
|
|
|
| 414 |
|
|
I2C_TRACE("\nI2C INIT, divider: %d(%d), frequency: %d\n", i2c_div[div],
|
| 415 |
|
|
div, i2c_freq);
|
| 416 |
|
|
|
| 417 |
|
|
cyg_drv_mutex_init(&extra->i2c_lock);
|
| 418 |
|
|
cyg_drv_cond_init(&extra->i2c_wait, &extra->i2c_lock);
|
| 419 |
|
|
cyg_drv_interrupt_create(extra->i2c_isr_id,
|
| 420 |
|
|
extra->i2c_isr_pri,
|
| 421 |
|
|
(cyg_addrword_t)extra,
|
| 422 |
|
|
&a2fxxx_i2c_isr,
|
| 423 |
|
|
&a2fxxx_i2c_dsr,
|
| 424 |
|
|
&(extra->i2c_interrupt_handle),
|
| 425 |
|
|
&(extra->i2c_interrupt_data));
|
| 426 |
|
|
cyg_drv_interrupt_attach(extra->i2c_interrupt_handle);
|
| 427 |
|
|
|
| 428 |
|
|
// Enable I2C peripheral
|
| 429 |
|
|
CYGHWR_HAL_A2FXXX_PERIPH_RELEASE(extra->i2c_periph);
|
| 430 |
|
|
|
| 431 |
|
|
// Set I2C bus speed
|
| 432 |
|
|
HAL_WRITE_UINT32(I2C_CR_ENS1(extra->i2c_base_bb),
|
| 433 |
|
|
CYGHWR_HAL_A2FXXX_BITSET);
|
| 434 |
|
|
|
| 435 |
|
|
HAL_WRITE_UINT32(I2C_CR_CR0(extra->i2c_base_bb),
|
| 436 |
|
|
((div & 0x1) ? CYGHWR_HAL_A2FXXX_BITSET :
|
| 437 |
|
|
CYGHWR_HAL_A2FXXX_BITCLEAR));
|
| 438 |
|
|
HAL_WRITE_UINT32(I2C_CR_CR1(extra->i2c_base_bb),
|
| 439 |
|
|
((div & 0x2) ? CYGHWR_HAL_A2FXXX_BITSET :
|
| 440 |
|
|
CYGHWR_HAL_A2FXXX_BITCLEAR));
|
| 441 |
|
|
HAL_WRITE_UINT32(I2C_CR_CR2(extra->i2c_base_bb),
|
| 442 |
|
|
((div & 0x4) ? CYGHWR_HAL_A2FXXX_BITSET :
|
| 443 |
|
|
CYGHWR_HAL_A2FXXX_BITCLEAR));
|
| 444 |
|
|
|
| 445 |
|
|
// Interrupts can now be safely unmasked
|
| 446 |
|
|
HAL_INTERRUPT_UNMASK(extra->i2c_isr_id);
|
| 447 |
|
|
}
|
| 448 |
|
|
|
| 449 |
|
|
//---------------------------------------------------------------------------
|
| 450 |
|
|
// EOF i2c_a2fxxx.c
|
