OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [devs/] [i2c/] [cortexm/] [lm3s/] [current/] [include/] [i2c_lm3s.h] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
//==========================================================================
2
//
3
//      i2c_lm3s8xx.h
4
//
5
//      I2C driver for Stellaris Cortex M3 microcontroller
6
//
7
//==========================================================================
8
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
9
// -------------------------------------------                              
10
// This file is part of eCos, the Embedded Configurable Operating System.   
11
// Copyright (C) 2010, 2011 Free Software Foundation, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under    
14
// the terms of the GNU General Public License as published by the Free     
15
// Software Foundation; either version 2 or (at your option) any later      
16
// version.                                                                 
17
//
18
// eCos is distributed in the hope that it will be useful, but WITHOUT      
19
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
20
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
21
// for more details.                                                        
22
//
23
// You should have received a copy of the GNU General Public License        
24
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
25
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
26
//
27
// As a special exception, if other files instantiate templates or use      
28
// macros or inline functions from this file, or you compile this file      
29
// and link it with other works to produce a work based on this file,       
30
// this file does not by itself cause the resulting work to be covered by   
31
// the GNU General Public License. However the source code for this file    
32
// must still be made available in accordance with section (3) of the GNU   
33
// General Public License v2.                                               
34
//
35
// This exception does not invalidate any other reasons why a work based    
36
// on this file might be covered by the GNU General Public License.         
37
// -------------------------------------------                              
38
// ####ECOSGPLCOPYRIGHTEND####                                              
39
//==========================================================================
40
//#####DESCRIPTIONBEGIN####
41
//
42
// Author(s):     ccoutand
43
// Contributors:  
44
// Date:          2011-01-18
45
// Original:      Bart Veer
46
//                I2C driver for motorola coldfire processor
47
// Description:   I2C driver for Stellaris Cortex M3 microcontroller
48
//####DESCRIPTIONEND####
49
//==========================================================================
50
 
51
#ifndef CYGONCE_I2C_LM3S_H
52
#define CYGONCE_I2C_LM3S_H
53
 
54
#include <pkgconf/devs_i2c_cortexm_lm3s.h>
55
#include <cyg/infra/cyg_type.h>
56
#include <cyg/hal/drv_api.h>
57
 
58
typedef enum lm3s_i2c_xfer_mode {
59
    LM3S_I2C_XFER_MODE_INVALID = 0x00,
60
    LM3S_I2C_XFER_MODE_TX = 0x01,
61
    LM3S_I2C_XFER_MODE_RX = 0x02
62
} lm3s_i2c_xfer_mode;
63
 
64
typedef struct lm3s_i2c_extra {
65
    cyg_uint32      i2c_base;          // I2C base address
66
    cyg_uint32      i2c_periph;        // I2C peripheral bit mask
67
    cyg_uint8       i2c_owner;         // We have bus ownership
68
    cyg_uint8       i2c_lost_arb;      // Error condition leading to loss of
69
                                       // bus ownership
70
    cyg_uint8       i2c_send_nack;     // As per rx send_nack argument
71
    cyg_uint8       i2c_got_nack;      // The last tx resulted in a nack
72
    cyg_uint8       i2c_completed;     // Set by DSR, checked by thread
73
 
74
    union {
75
        const cyg_uint8 *i2c_tx_data;
76
        cyg_uint8      *i2c_rx_data;
77
    } i2c_data;                        // The current buffer for rx or tx
78
    cyg_uint32      i2c_count;         // Number of bytes left in buffer
79
    lm3s_i2c_xfer_mode i2c_mode;       // TX, RX, ...
80
 
81
    cyg_bool        send_stop;
82
    cyg_bool        send_start;
83
    cyg_drv_mutex_t i2c_lock;          // For synchronizing between DSR and
84
                                       // foreground
85
    cyg_drv_cond_t  i2c_wait;
86
    // For initializing the interrupt
87
    cyg_handle_t    i2c_interrupt_handle;
88
    cyg_interrupt   i2c_interrupt_data;
89
    cyg_uint32      i2c_isr_id;
90
    cyg_uint32      i2c_isr_pri;
91
} lm3s_i2c_extra;
92
 
93
externC void    lm3s_i2c_init(struct cyg_i2c_bus *);
94
externC cyg_uint32 lm3s_i2c_tx(const cyg_i2c_device *, cyg_bool,
95
                               const cyg_uint8 *, cyg_uint32, cyg_bool);
96
externC cyg_uint32 lm3s_i2c_rx(const cyg_i2c_device *, cyg_bool, cyg_uint8 *,
97
                               cyg_uint32, cyg_bool, cyg_bool);
98
externC void    lm3s_i2c_stop(const cyg_i2c_device *);
99
 
100
#define CYG_LM3S_I2C_BUS(                               \
101
        _name_,                                         \
102
        _init_fn_,                                      \
103
        _base_,                                         \
104
        _periph_,                                       \
105
        _isr_vec_,                                      \
106
        _isr_pri_,                                      \
107
        _fdr_)                                          \
108
    static lm3s_i2c_extra _name_ ## _extra = {          \
109
       .i2c_base = _base_,                              \
110
       .i2c_periph = _periph_,                          \
111
       .i2c_isr_id = _isr_vec_,                         \
112
       .i2c_isr_pri= _isr_pri_                          \
113
    };                                                  \
114
    CYG_I2C_BUS(_name_,                                 \
115
                _init_fn_,                              \
116
                lm3s_i2c_tx,                            \
117
                lm3s_i2c_rx,                            \
118
                lm3s_i2c_stop,                          \
119
                (void*) & ( _name_ ## _extra)) ;
120
 
121
#endif // CYGONCE_I2C_LM3S_H
122
 
123
// -------------------------------------------------------------------------
124
// EOF i2c_lm3s.h

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.