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skrzyp |
//==========================================================================
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//
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// i2c_lm3s.c
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//
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// I2C driver for Stellaris Cortex M3 microcontroller
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2011 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): ccoutand
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// Contributors:
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// Date: 2011-01-18
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// Original: Uwe Kindler, Bart Veer
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// I2C driver for motorola coldfire processor
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// Description: I2C driver for Stellaris Cortex M3 microcontroller
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// The RX part of the driver has not been tested.
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//
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//####DESCRIPTIONEND####
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//==========================================================================
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#include <pkgconf/system.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/cyg_ass.h>
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#include <cyg/infra/diag.h>
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#include <cyg/io/i2c.h>
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#include <cyg/io/i2c_lm3s.h>
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#include <cyg/hal/hal_arch.h>
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#include <cyg/hal/hal_io.h>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/hal/drv_api.h>
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#ifdef CYGPKG_DEVS_I2C_CORTEXM_LM3S_TRACE
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# define I2C_TRACE(args...) diag_printf(args)
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#else
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# define I2C_TRACE(args...)
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#endif
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#define I2C_DAT(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MDR)
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#define I2C_ADR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MSA)
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#define I2C_SR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MCS)
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#define I2C_CR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MCS)
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#define I2C_MCR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MCR)
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#define I2C_MTPR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MTPR)
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#define I2C_MCR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MCR)
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#define I2C_IMR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MIMR)
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#define I2C_ICR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MICR)
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#define WAIT_BUS_READY( __sr__, __extra__ ) \
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{ \
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if (!__extra__->i2c_owner) { \
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__extra__->i2c_got_nack = 0; \
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__extra__->i2c_owner = 1; \
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HAL_READ_UINT32(I2C_SR(__extra__->i2c_base), __sr__); \
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while (__sr__ & CYGHWR_HAL_LM3S_I2C_MCS_BUSBSY) { \
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HAL_READ_UINT32(I2C_SR(__extra__->i2c_base),__sr__); \
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} \
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} \
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}
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static cyg_uint32
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lm3s_i2c_isr(cyg_vector_t vec, cyg_addrword_t data)
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{
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lm3s_i2c_extra *extra = (lm3s_i2c_extra *) data;
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cyg_uint32 sr,
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dr;
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cyg_uint32 result = CYG_ISR_HANDLED;
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cyg_uint32 reg = CYGHWR_HAL_LM3S_I2C_MCS_RUN;
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cyg_uint8 tx_data = *extra->i2c_data.i2c_tx_data;
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// Read the current status, then clear the interrupt
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HAL_READ_UINT32(I2C_SR(extra->i2c_base), sr);
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HAL_WRITE_UINT32(I2C_ICR(extra->i2c_base), 1);
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// What to do next depends on the current transfer mode.
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if (LM3S_I2C_XFER_MODE_TX == extra->i2c_mode) {
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I2C_TRACE("I2C: TX IRQ handling\n");
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if (sr & CYGHWR_HAL_LM3S_I2C_MCS_ERR) {
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// Lost the bus, abort the transfer. count has already been
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// decremented. Assume the byte did not actually arrive.
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extra->i2c_count += 1;
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// Arbitration lost, stop
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if (sr & CYGHWR_HAL_LM3S_I2C_MCS_ARBLST) {
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reg = CYGHWR_HAL_LM3S_I2C_MCS_STOP;
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HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg);
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}
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// This byte has been sent but the device cannot accept
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// any more. The nack must be remembered. Otherwise if
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// we got a nack for the last byte in a tx then the
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// calling code will think the entire tx succeeded,
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// and there will be problems if the next call is
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// another tx without a repeated start.
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if ((sr & CYGHWR_HAL_LM3S_I2C_MCS_ADRACK) |
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(sr & CYGHWR_HAL_LM3S_I2C_MCS_DATACK)) {
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extra->i2c_got_nack = 1;
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}
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result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
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I2C_TRACE("I2C TX, bus arbitration error\n");
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} else if (0 == extra->i2c_count) {
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// No more bytes to send.
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result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
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} else {
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// Send byte
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HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base), (cyg_uint32)tx_data);
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extra->i2c_data.i2c_tx_data += 1;
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extra->i2c_count -= 1;
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// Last byte
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if ((0 == extra->i2c_count) && extra->send_stop) {
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reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP;
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}
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HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg);
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}
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} else if (LM3S_I2C_XFER_MODE_RX == extra->i2c_mode) {
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I2C_TRACE("I2C: RX IRQ handling\n");
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if (sr & CYGHWR_HAL_LM3S_I2C_MCS_ERR) {
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// Lost the bus? Maybe a spurious stop
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result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
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} else {
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if (2 == extra->i2c_count) {
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// Received one, one more to go,
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// and that one should be nacked.
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if (!extra->i2c_send_nack) {
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reg |= CYGHWR_HAL_LM3S_I2C_MCS_ACK;
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}
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if (extra->send_stop) {
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reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP;
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}
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HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg);
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} else if (1 == extra->i2c_count) {
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// Received the last byte.
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result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
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}
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HAL_READ_UINT32(I2C_DAT(extra->i2c_base), dr);
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*(extra->i2c_data.i2c_rx_data) = (cyg_uint8)dr;
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extra->i2c_data.i2c_rx_data += 1;
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extra->i2c_count -= 1;
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}
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} else {
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// Invalid state? Some kind of spurious interrupt?
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// Just ignore it.
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I2C_TRACE("I2C spurious interrupt\n");
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}
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HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
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return result;
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}
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static void
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lm3s_i2c_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
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{
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lm3s_i2c_extra *extra = (lm3s_i2c_extra *) data;
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extra->i2c_completed = 1;
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cyg_drv_cond_signal(&(extra->i2c_wait));
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}
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// A transfer has been started. Wait for completion
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static inline void
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lm3s_i2c_doit(lm3s_i2c_extra * extra)
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{
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cyg_drv_mutex_lock(&(extra->i2c_lock));
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cyg_drv_dsr_lock();
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while (!extra->i2c_completed) {
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cyg_drv_cond_wait(&(extra->i2c_wait));
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}
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cyg_drv_dsr_unlock();
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cyg_drv_mutex_unlock(&(extra->i2c_lock));
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}
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static inline void
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lm3s_i2c_stopit(lm3s_i2c_extra * extra)
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{
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extra->i2c_lost_arb = 0;
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extra->i2c_owner = 0;
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extra->i2c_mode = LM3S_I2C_XFER_MODE_INVALID;
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}
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void
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lm3s_i2c_stop(const cyg_i2c_device * dev)
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{
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lm3s_i2c_extra *extra = (lm3s_i2c_extra *) dev->i2c_bus->i2c_extra;
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lm3s_i2c_stopit(extra);
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}
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static cyg_bool
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lm3s_i2c_handle_xfer(lm3s_i2c_extra * extra, int address)
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{
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cyg_uint32 sr;
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cyg_uint8 data = *extra->i2c_data.i2c_tx_data;
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cyg_uint32 reg = CYGHWR_HAL_LM3S_I2C_MCS_RUN;
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// Nothing to send or receive
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if (extra->i2c_count == 0)
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return 0;
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// Take the bus ownership
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WAIT_BUS_READY(sr, extra);
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// This can be a start or repeated start
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if (extra->send_start) {
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reg |= CYGHWR_HAL_LM3S_I2C_MCS_START;
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HAL_WRITE_UINT32(I2C_ADR(extra->i2c_base), address);
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}
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// TX transfer
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if (extra->i2c_mode == LM3S_I2C_XFER_MODE_TX) {
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extra->i2c_data.i2c_tx_data += 1;
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extra->i2c_count -= 1;
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HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base), (cyg_uint32)data);
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// Single byte transfer
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if (extra->send_stop && (extra->i2c_count == 0)) {
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reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP;
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}
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} else {
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// Single byte transfer, set the STOP bit
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if (extra->send_stop && (extra->i2c_count == 1)) {
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reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP;
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}
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// Do not ACK last byte per user request
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if (!extra->i2c_send_nack || !(extra->i2c_count == 1)) {
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reg |= CYGHWR_HAL_LM3S_I2C_MCS_ACK;
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}
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}
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| 263 |
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HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg);
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| 264 |
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| 265 |
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return 1;
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}
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| 267 |
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| 269 |
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cyg_uint32
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lm3s_i2c_tx(const cyg_i2c_device * dev, cyg_bool send_start,
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| 271 |
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const cyg_uint8 *tx_data, cyg_uint32 count, cyg_bool send_stop)
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| 272 |
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{
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| 273 |
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lm3s_i2c_extra *extra = (lm3s_i2c_extra *) dev->i2c_bus->i2c_extra;
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| 274 |
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extra->send_stop = send_stop;
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| 275 |
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extra->send_start = send_start;
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| 276 |
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extra->i2c_count = count;
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| 277 |
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| 278 |
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if (!extra->i2c_lost_arb) {
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| 279 |
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extra->i2c_completed = 0;
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| 280 |
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extra->i2c_mode = LM3S_I2C_XFER_MODE_TX;
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| 281 |
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| 282 |
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if (send_start || !extra->i2c_got_nack) {
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I2C_TRACE
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| 284 |
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("I2C: TX to %2x, data %2x, count: %4d, START flag: %s\n",
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| 285 |
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dev->i2c_address, *tx_data, count,
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| 286 |
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(send_start == true) ? "true" : "false");
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| 287 |
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extra->i2c_data.i2c_tx_data = tx_data;
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| 288 |
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if (!lm3s_i2c_handle_xfer(extra, (dev->i2c_address << 1) | 0x00)) {
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| 289 |
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return 0;
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| 290 |
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}
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| 291 |
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lm3s_i2c_doit(extra);
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| 292 |
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}
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| 293 |
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| 294 |
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}
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| 295 |
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if (send_stop) {
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| 296 |
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I2C_TRACE("I2C: TX send stop\n");
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| 297 |
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lm3s_i2c_stopit(extra);
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| 298 |
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}
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| 299 |
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| 300 |
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|
I2C_TRACE("I2C: TX count %d\n", extra->i2c_count);
|
| 301 |
|
|
|
| 302 |
|
|
// tx() should return the number of bytes actually transmitted.
|
| 303 |
|
|
// ISR() increments extra->count after a failure, which leads to
|
| 304 |
|
|
// an edge condition when send_start and there is no acknowledgment
|
| 305 |
|
|
// of the address byte.
|
| 306 |
|
|
if (extra->i2c_count > count) {
|
| 307 |
|
|
return 0;
|
| 308 |
|
|
}
|
| 309 |
|
|
|
| 310 |
|
|
return count - extra->i2c_count;
|
| 311 |
|
|
}
|
| 312 |
|
|
|
| 313 |
|
|
|
| 314 |
|
|
cyg_uint32
|
| 315 |
|
|
lm3s_i2c_rx(const cyg_i2c_device * dev, cyg_bool send_start,
|
| 316 |
|
|
cyg_uint8 *rx_data, cyg_uint32 count, cyg_bool send_nack,
|
| 317 |
|
|
cyg_bool send_stop)
|
| 318 |
|
|
{
|
| 319 |
|
|
lm3s_i2c_extra *extra = (lm3s_i2c_extra *) dev->i2c_bus->i2c_extra;
|
| 320 |
|
|
extra->i2c_count = count;
|
| 321 |
|
|
extra->i2c_send_nack = send_nack;
|
| 322 |
|
|
extra->send_stop = send_stop;
|
| 323 |
|
|
extra->send_start = send_start;
|
| 324 |
|
|
|
| 325 |
|
|
if (!extra->i2c_lost_arb) {
|
| 326 |
|
|
extra->i2c_completed = 0;
|
| 327 |
|
|
extra->i2c_data.i2c_rx_data = rx_data;
|
| 328 |
|
|
extra->i2c_mode = LM3S_I2C_XFER_MODE_RX;
|
| 329 |
|
|
I2C_TRACE("I2C: RX to %2x, count: %4d, START flag: %s\n",
|
| 330 |
|
|
dev->i2c_address, count,
|
| 331 |
|
|
(send_start == true) ? "true" : "false");
|
| 332 |
|
|
if (!lm3s_i2c_handle_xfer(extra, (dev->i2c_address << 1) | 0x01)) {
|
| 333 |
|
|
return 0;
|
| 334 |
|
|
}
|
| 335 |
|
|
lm3s_i2c_doit(extra);
|
| 336 |
|
|
}
|
| 337 |
|
|
|
| 338 |
|
|
if (send_stop) {
|
| 339 |
|
|
I2C_TRACE("I2C: RX send stop\n");
|
| 340 |
|
|
lm3s_i2c_stopit(extra);
|
| 341 |
|
|
}
|
| 342 |
|
|
|
| 343 |
|
|
return count - extra->i2c_count;
|
| 344 |
|
|
}
|
| 345 |
|
|
|
| 346 |
|
|
|
| 347 |
|
|
// ----------------------------------------------------------------------------
|
| 348 |
|
|
// The functions needed for all I2C devices.
|
| 349 |
|
|
|
| 350 |
|
|
void
|
| 351 |
|
|
lm3s_i2c_init(struct cyg_i2c_bus *bus)
|
| 352 |
|
|
{
|
| 353 |
|
|
lm3s_i2c_extra *extra = (lm3s_i2c_extra *) bus->i2c_extra;
|
| 354 |
|
|
cyg_uint32 tpr =
|
| 355 |
|
|
((hal_lm3s_i2c_clock() /
|
| 356 |
|
|
(20 * CYGNUM_HAL_CORTEXM_LM3S_I2C_CLK_SPEED)) - 1);
|
| 357 |
|
|
|
| 358 |
|
|
I2C_TRACE("I2C INIT, TPR register: %d\n", tpr);
|
| 359 |
|
|
|
| 360 |
|
|
cyg_drv_mutex_init(&extra->i2c_lock);
|
| 361 |
|
|
cyg_drv_cond_init(&extra->i2c_wait, &extra->i2c_lock);
|
| 362 |
|
|
cyg_drv_interrupt_create(extra->i2c_isr_id,
|
| 363 |
|
|
extra->i2c_isr_pri,
|
| 364 |
|
|
(cyg_addrword_t)extra,
|
| 365 |
|
|
&lm3s_i2c_isr,
|
| 366 |
|
|
&lm3s_i2c_dsr,
|
| 367 |
|
|
&(extra->i2c_interrupt_handle),
|
| 368 |
|
|
&(extra->i2c_interrupt_data));
|
| 369 |
|
|
cyg_drv_interrupt_attach(extra->i2c_interrupt_handle);
|
| 370 |
|
|
|
| 371 |
|
|
// Enable I2C peripheral, it is left to the variant/platform HAL to
|
| 372 |
|
|
// configure the SDA and SCL IOs.
|
| 373 |
|
|
CYGHWR_HAL_LM3S_PERIPH_SET(extra->i2c_periph, 1);
|
| 374 |
|
|
|
| 375 |
|
|
// Enable Master mode
|
| 376 |
|
|
HAL_WRITE_UINT32(I2C_MCR(extra->i2c_base), CYGHWR_HAL_LM3S_I2C_MCR_MFE);
|
| 377 |
|
|
|
| 378 |
|
|
// Set I2C bus speed
|
| 379 |
|
|
HAL_WRITE_UINT32(I2C_MTPR(extra->i2c_base), tpr);
|
| 380 |
|
|
|
| 381 |
|
|
// Enable Interrupt
|
| 382 |
|
|
HAL_WRITE_UINT32(I2C_IMR(extra->i2c_base), 1);
|
| 383 |
|
|
|
| 384 |
|
|
// Interrupts can now be safely unmasked
|
| 385 |
|
|
HAL_INTERRUPT_UNMASK(extra->i2c_isr_id);
|
| 386 |
|
|
}
|
| 387 |
|
|
|
| 388 |
|
|
//---------------------------------------------------------------------------
|
| 389 |
|
|
// EOF i2c_lm3s.c
|
