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//==========================================================================
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//
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// devs/i2c/m68k/mcf52xx/current/src/i2c_mcf52xx.c
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//
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// I2C driver for Motorola coldfire processors
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2005, 2006, 2009 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Uwe Kindler, Bart Veer
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// Contributors:
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// Date: 2005-10-23
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// Description: I2C driver for motorola coldfire processor
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//####DESCRIPTIONEND####
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//==========================================================================
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#include <pkgconf/system.h>
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#include <pkgconf/devs_i2c_mcf52xx.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/cyg_ass.h>
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#include <cyg/infra/diag.h>
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#include <cyg/io/i2c.h>
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#include <cyg/io/i2c_mcf52xx.h>
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#include <cyg/hal/hal_arch.h>
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#include <cyg/hal/hal_io.h>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/hal/drv_api.h>
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// Optimize for the case of a single bus device, while still allowing
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// multiple devices.
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#ifndef CYGHWR_DEVS_I2C_MCF52xx_MULTIPLE_BUSES
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# define I2C_BASE(_extra_) (cyg_uint8*)HAL_MCF52xx_I2C_SINGLETON_BASE
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# define I2C_ISRVEC(_extra_) HAL_MCF52xx_I2C_SINGLETON_ISRVEC
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# define I2C_ISRPRI(_extra_) HAL_MCF52xx_I2C_SINGLETON_ISRPRI
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# define I2C_FDR(_extra_) HAL_MCF52xx_I2C_SINGLETON_FDR
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#else
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# define I2C_BASE(_extra_) ((_extra_)->i2c_base)
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# define I2C_ISRVEC(_extra_) ((_extra_)->i2c_isrvec)
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# define I2C_ISRPRI(_extra_) ((_extra_)->i2c_isrpri)
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# define I2C_FDR(_extra_) ((_extra_)->i2c_fdr)
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#endif
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// If building for a singleton but the macros are no defined, assume
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// the I2C support is conditional on a disabled platform HAL
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// configuration option. This handles the common case of an I2C bus
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// accessed only via an expansion connector.
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#if defined(CYGHWR_DEVS_I2C_MCF52xx_MULTIPLE_BUSES) || defined(HAL_MCF52xx_I2C_SINGLETON_BASE)
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// ----------------------------------------------------------------------------
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// Interrupt handling and polling
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//
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// The MCF52xx I2C bus device does not have a fifo or any kind of DMA
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// capability, so can generate interrupts at a very high rate: ~10K
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// interrupts per second if the bus is running at the standard 100KHz,
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// or 50K for a high-speed 400KHz bus. To keep the cpu load down to
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// something vaguely reasonable as much work as possible has to be
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// done in the ISR, with the DSR used only for completion.
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static cyg_uint32
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mcf52xx_i2c_isr(cyg_vector_t vec, cyg_addrword_t data)
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{
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cyg_mcf52xx_i2c_extra* extra = (cyg_mcf52xx_i2c_extra*)data;
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cyg_uint8 sr, dr;
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cyg_uint8* base = I2C_BASE(extra);
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cyg_uint32 result = CYG_ISR_HANDLED;
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// Read the current status, then clear the interrupt and
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// arbitration-lost flags. No later code will look at the
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// SR register again.
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HAL_READ_UINT8( base + HAL_MCF52xx_I2C_SR_OFF, sr);
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_SR_OFF, 0x00);
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// What to do next depends on the current transfer mode.
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if (CYG_MCF52xx_I2C_XFER_MODE_TX == extra->i2c_mode) {
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// We are in a transmit, or sending the address byte just
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// before a transmit.
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if (sr & HAL_MCF52xx_I2C_SR_IAL) {
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// Lost the bus, abort the transfer. count has already been
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// decremented. Assume the byte did not actually arrive.
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extra->i2c_count += 1;
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result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
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} else if (sr & HAL_MCF52xx_I2C_SR_RXAK) {
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// This byte has been sent but the device cannot accept
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// any more. The nack must be remembered. Otherwise if
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// we got a nack for the last byte in a tx then the
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// calling code will think the entire tx succeeded,
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// and there will be problems if the next call is
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// another tx without a repeated start.
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extra->i2c_got_nack = 1;
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result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
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} else if (0 == extra->i2c_count) {
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// No more bytes to send.
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result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
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} else {
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_DR_OFF, *(extra->i2c_data.i2c_tx_data));
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extra->i2c_data.i2c_tx_data += 1;
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extra->i2c_count -= 1;
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}
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} else if (CYG_MCF52xx_I2C_XFER_MODE_RX == extra->i2c_mode) {
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if (sr & HAL_MCF52xx_I2C_SR_IAL) {
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// Lost the bus? Maybe a spurious stop
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result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
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} else {
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if (extra->i2c_send_nack && (2 == extra->i2c_count)) {
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// Received one, one more to go, and that one should be nacked.
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF,
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HAL_MCF52xx_I2C_CR_IEN |
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HAL_MCF52xx_I2C_CR_IIEN |
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HAL_MCF52xx_I2C_CR_MSTA |
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HAL_MCF52xx_I2C_CR_TXAK);
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} else if (1 == extra->i2c_count) {
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// Received the last byte. The docs say to send a stop,
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// but there may be another transaction_rx() call. We
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// cannot just read DR again, that would trigger another
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// read. So instead switch to transmit mode for now,
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// which should cause the h/w to wait until a byte is
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// written to DR.
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF,
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HAL_MCF52xx_I2C_CR_IEN |
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HAL_MCF52xx_I2C_CR_IIEN |
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HAL_MCF52xx_I2C_CR_MSTA |
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HAL_MCF52xx_I2C_CR_MTX);
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result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
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}
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HAL_READ_UINT8(base + HAL_MCF52xx_I2C_DR_OFF, dr);
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*(extra->i2c_data.i2c_rx_data) = dr;
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extra->i2c_data.i2c_rx_data += 1;
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extra->i2c_count -= 1;
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}
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} else if (CYG_MCF52xx_I2C_XFER_MODE_STARTRX == extra->i2c_mode) {
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// Start followed by RX. The address byte has been sent, we
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// need to switch to receiving.
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if (sr & (HAL_MCF52xx_I2C_SR_IAL | HAL_MCF52xx_I2C_SR_RXAK)) {
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// Looks like no device acknowledged the address.
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result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
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} else {
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extra->i2c_mode = CYG_MCF52xx_I2C_XFER_MODE_RX;
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if (extra->i2c_send_nack && (1 == extra->i2c_count)) {
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF,
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HAL_MCF52xx_I2C_CR_IEN |
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HAL_MCF52xx_I2C_CR_IIEN |
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HAL_MCF52xx_I2C_CR_MSTA |
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HAL_MCF52xx_I2C_CR_TXAK);
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} else {
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF,
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HAL_MCF52xx_I2C_CR_IEN |
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HAL_MCF52xx_I2C_CR_IIEN |
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HAL_MCF52xx_I2C_CR_MSTA);
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}
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// This dummy read causes the next rx to start
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HAL_READ_UINT8(base + HAL_MCF52xx_I2C_DR_OFF, dr);
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}
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} else {
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// Invalid state? Some kind of spurious interrupt? Just ignore
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// it.
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CYG_FAIL("I2C spurious interrupt");
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}
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// NOTE: this will acknowledge the interrupt even in polled mode.
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// Probably harmless. Using I2C_ISRVEC rather than the vec arg
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// means a constant number for the singleton case, which may
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// allow the HAL to optimize the acknowledge away completely.
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HAL_INTERRUPT_ACKNOWLEDGE(I2C_ISRVEC(extra));
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return result;
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}
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static void
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mcf52xx_i2c_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
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{
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cyg_mcf52xx_i2c_extra* extra = (cyg_mcf52xx_i2c_extra*)data;
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extra->i2c_completed = 1;
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cyg_drv_cond_signal(&(extra->i2c_wait));
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}
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// A transfer has been started. Wait for completion, allowing for both
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// polled and interrupt-driven mode.
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static inline void
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mcf52xx_i2c_doit(cyg_mcf52xx_i2c_extra* extra)
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{
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cyg_uint8* base = I2C_BASE(extra);
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int ints_state;
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int sr;
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HAL_QUERY_INTERRUPTS(ints_state);
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if (((ints_state >> 8) & 0x07) > CYGNUM_HAL_INTERRUPT_DEFAULT_IPL_LEVEL) {
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// Interrupts are currently disabled. We'll have to poll.
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for ( ; ; ) {
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HAL_READ_UINT8(base + HAL_MCF52xx_I2C_SR_OFF, sr);
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if (sr & HAL_MCF52xx_I2C_SR_IIF) {
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if (CYG_ISR_CALL_DSR & mcf52xx_i2c_isr(I2C_ISRVEC(extra), (cyg_addrword_t)extra)) {
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break;
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}
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}
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}
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} else {
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cyg_drv_mutex_lock(&(extra->i2c_lock));
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cyg_drv_dsr_lock();
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while (! extra->i2c_completed) {
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cyg_drv_cond_wait(&(extra->i2c_wait));
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}
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cyg_drv_dsr_unlock();
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cyg_drv_mutex_unlock(&(extra->i2c_lock));
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}
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}
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238 |
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239 |
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static cyg_bool
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mcf52xx_i2c_send_start(cyg_mcf52xx_i2c_extra* extra, int address)
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{
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cyg_uint8* base = I2C_BASE(extra);
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cyg_uint8 sr;
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244 |
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// This may be a repeated start or the beginning of a transaction.
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// If the former then we still own the bus.
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247 |
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if (!extra->i2c_owner) {
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248 |
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// The bus is currently in slave mode. See if another master
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249 |
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// currently owns the bus and if so fail immediately. It is up
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250 |
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// to higher level code to decide when to retry. Alternatively
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// if the bus has somehow got stuck in busy mode it is again
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252 |
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// up to higher level code to sort things out.
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HAL_READ_UINT8(I2C_BASE(extra) + HAL_MCF52xx_I2C_SR_OFF, sr);
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if (sr & HAL_MCF52xx_I2C_SR_IBB) {
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return 0;
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}
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257 |
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258 |
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// Now we can put the bus into master mode
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259 |
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF,
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260 |
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HAL_MCF52xx_I2C_CR_IEN |
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HAL_MCF52xx_I2C_CR_IIEN |
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HAL_MCF52xx_I2C_CR_MSTA | // This implicitly generates the start
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HAL_MCF52xx_I2C_CR_MTX); // The address byte needs to be transmitted.
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extra->i2c_owner = 1;
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} else {
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266 |
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF,
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267 |
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HAL_MCF52xx_I2C_CR_IEN |
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268 |
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HAL_MCF52xx_I2C_CR_IIEN |
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269 |
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HAL_MCF52xx_I2C_CR_MSTA | // Already set so no start generated by this
|
270 |
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HAL_MCF52xx_I2C_CR_MTX |
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HAL_MCF52xx_I2C_CR_RSTA); // Repeated start
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}
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273 |
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274 |
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// Any previous nack is no longer relevant. If the device cannot accept
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275 |
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// more data it will nack the address.
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276 |
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extra->i2c_got_nack = 0;
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277 |
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// Now send the address. The rest of the transfer is handled by the
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278 |
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// interrupt/polling code.
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279 |
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_DR_OFF, address);
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return 1;
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281 |
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}
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282 |
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static inline void
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284 |
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mcf52xx_i2c_stopit(cyg_mcf52xx_i2c_extra* extra)
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{
|
286 |
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// If we still own the bus this releases it (by clearing MSTA) and
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287 |
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// generating a stop. If we have lost arbitration then this write
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288 |
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// has no effect (other than disabling interrupts). Either way the
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289 |
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// bus should end up in a consistent state.
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290 |
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HAL_WRITE_UINT8(I2C_BASE(extra) + HAL_MCF52xx_I2C_CR_OFF, HAL_MCF52xx_I2C_CR_IEN);
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291 |
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extra->i2c_lost_arb = 0;
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292 |
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extra->i2c_owner = 0;
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293 |
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extra->i2c_mode = CYG_MCF52xx_I2C_XFER_MODE_INVALID;
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294 |
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}
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295 |
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296 |
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// ----------------------------------------------------------------------------
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297 |
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// The functions needed for all I2C devices.
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298 |
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299 |
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void
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300 |
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cyg_mcf52xx_i2c_init(struct cyg_i2c_bus* bus)
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301 |
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{
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cyg_mcf52xx_i2c_extra* extra = (cyg_mcf52xx_i2c_extra*)bus->i2c_extra;
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cyg_uint8 reg;
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304 |
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cyg_uint8* base = I2C_BASE(extra);
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306 |
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cyg_drv_mutex_init(&extra->i2c_lock);
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cyg_drv_cond_init(&extra->i2c_wait, &extra->i2c_lock);
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cyg_drv_interrupt_create(I2C_ISRVEC(extra),
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I2C_ISRPRI(extra),
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(cyg_addrword_t) extra,
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&mcf52xx_i2c_isr,
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&mcf52xx_i2c_dsr,
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&(extra->i2c_interrupt_handle),
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&(extra->i2c_interrupt_data));
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cyg_drv_interrupt_attach(extra->i2c_interrupt_handle);
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// Before unmasking the interrupt sort out the hardware.
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//
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// The bus frequency is set by the platform HAL or user, since
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// it depends on what mixture of devices are present on the bus.
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_FDR_OFF, I2C_FDR(extra));
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// The device will operate in slave mode when idle. If there is
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// another bus master then the coldfire might accidentally accept
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// requests intended for another device. Address 0 is installed
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// as the slave address. This is the General Call address, used
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// for broadcasting. It might be better to use another address
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// like an Hs-mode one, but conflicts are still possible.
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_ADR_OFF, 0x0);
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// Enable the I2C device but do not start any transfers and
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// leave interrupts disabled.
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF, HAL_MCF52xx_I2C_CR_IEN);
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// As per the documentation, if IBB is set then issue a stop. It
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// is not really clear this is the right thing to do in
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// multimaster setups, if another master happens to start a
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// transfer at this exact time. Presumably it solves more problems
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// than it might cause.
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HAL_READ_UINT8(base + HAL_MCF52xx_I2C_SR_OFF, reg);
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if (reg & HAL_MCF52xx_I2C_SR_IBB) {
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF, 0x0000);
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF, 0x00A0);
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HAL_READ_UINT8( base + HAL_MCF52xx_I2C_DR_OFF, reg);
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_SR_OFF, 0x0000);
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF, 0x0000);
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346 |
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// Don't forget to reenable the device.
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF, HAL_MCF52xx_I2C_CR_IEN);
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348 |
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}
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349 |
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350 |
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// Clear any pending conditions including interrupts.
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351 |
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HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_SR_OFF, 0);
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352 |
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353 |
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// Interrupts can now be safely unmasked
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354 |
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HAL_INTERRUPT_UNMASK(I2C_ISRVEC(extra));
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355 |
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}
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356 |
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357 |
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cyg_uint32
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cyg_mcf52xx_i2c_tx(const cyg_i2c_device* dev, cyg_bool send_start, const cyg_uint8* tx_data, cyg_uint32 count, cyg_bool send_stop)
|
359 |
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{
|
360 |
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cyg_mcf52xx_i2c_extra* extra = (cyg_mcf52xx_i2c_extra*)dev->i2c_bus->i2c_extra;
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361 |
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362 |
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extra->i2c_count = count;
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363 |
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if (! extra->i2c_lost_arb) {
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364 |
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extra->i2c_completed = 0;
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365 |
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extra->i2c_mode = CYG_MCF52xx_I2C_XFER_MODE_TX;
|
366 |
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|
367 |
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if (send_start) {
|
368 |
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extra->i2c_data.i2c_tx_data = tx_data;
|
369 |
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if (! mcf52xx_i2c_send_start(extra, (dev->i2c_address << 1) | 0x00)) {
|
370 |
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return 0;
|
371 |
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}
|
372 |
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mcf52xx_i2c_doit(extra);
|
373 |
|
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} else if ( !extra->i2c_got_nack) {
|
374 |
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// We are in the middle of a transaction and not
|
375 |
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// generating a repeated start, so the device must already
|
376 |
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// be set up for writes.
|
377 |
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extra->i2c_data.i2c_tx_data = &(tx_data[1]);
|
378 |
|
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extra->i2c_count = count - 1;
|
379 |
|
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HAL_WRITE_UINT8(I2C_BASE(extra) + HAL_MCF52xx_I2C_DR_OFF, *tx_data);
|
380 |
|
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mcf52xx_i2c_doit(extra);
|
381 |
|
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}
|
382 |
|
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}
|
383 |
|
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if (send_stop) {
|
384 |
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mcf52xx_i2c_stopit(extra);
|
385 |
|
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}
|
386 |
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|
387 |
|
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// tx() should return the number of bytes actually transmitted.
|
388 |
|
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// ISR() increments extra->count after a failure, which leads to
|
389 |
|
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// an edge condition when send_start and there is no acknowledgment
|
390 |
|
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// of the address byte.
|
391 |
|
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if (extra->i2c_count > count) {
|
392 |
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return 0;
|
393 |
|
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}
|
394 |
|
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return count - extra->i2c_count;
|
395 |
|
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}
|
396 |
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|
397 |
|
|
cyg_uint32
|
398 |
|
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cyg_mcf52xx_i2c_rx(const cyg_i2c_device* dev, cyg_bool send_start, cyg_uint8* rx_data, cyg_uint32 count, cyg_bool send_nack, cyg_bool send_stop)
|
399 |
|
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{
|
400 |
|
|
cyg_mcf52xx_i2c_extra* extra = (cyg_mcf52xx_i2c_extra*)dev->i2c_bus->i2c_extra;
|
401 |
|
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cyg_uint8* base = I2C_BASE(extra);
|
402 |
|
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cyg_uint8 discard;
|
403 |
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|
404 |
|
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extra->i2c_count = count;
|
405 |
|
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extra->i2c_send_nack = send_nack;
|
406 |
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|
407 |
|
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if (! extra->i2c_lost_arb) {
|
408 |
|
|
extra->i2c_completed = 0;
|
409 |
|
|
extra->i2c_data.i2c_rx_data = rx_data;
|
410 |
|
|
if (send_start) {
|
411 |
|
|
extra->i2c_mode = CYG_MCF52xx_I2C_XFER_MODE_STARTRX;
|
412 |
|
|
if (! mcf52xx_i2c_send_start(extra, (dev->i2c_address << 1) | 0x01) ) {
|
413 |
|
|
return 0;
|
414 |
|
|
}
|
415 |
|
|
} else {
|
416 |
|
|
// In the middle of a transaction. The previous transfer
|
417 |
|
|
// will have left the device in tx mode.
|
418 |
|
|
extra->i2c_mode = CYG_MCF52xx_I2C_XFER_MODE_RX;
|
419 |
|
|
if (send_nack && (1 == count)) {
|
420 |
|
|
HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF,
|
421 |
|
|
HAL_MCF52xx_I2C_CR_IEN |
|
422 |
|
|
HAL_MCF52xx_I2C_CR_IIEN |
|
423 |
|
|
HAL_MCF52xx_I2C_CR_MSTA |
|
424 |
|
|
HAL_MCF52xx_I2C_CR_TXAK);
|
425 |
|
|
} else {
|
426 |
|
|
HAL_WRITE_UINT8(base + HAL_MCF52xx_I2C_CR_OFF,
|
427 |
|
|
HAL_MCF52xx_I2C_CR_IEN |
|
428 |
|
|
HAL_MCF52xx_I2C_CR_IIEN |
|
429 |
|
|
HAL_MCF52xx_I2C_CR_MSTA);
|
430 |
|
|
}
|
431 |
|
|
// So reading the data register here should get the device
|
432 |
|
|
// reading the next byte.
|
433 |
|
|
HAL_READ_UINT8(base + HAL_MCF52xx_I2C_DR_OFF, discard);
|
434 |
|
|
}
|
435 |
|
|
mcf52xx_i2c_doit(extra);
|
436 |
|
|
}
|
437 |
|
|
if (send_stop) {
|
438 |
|
|
mcf52xx_i2c_stopit(extra);
|
439 |
|
|
}
|
440 |
|
|
return count - extra->i2c_count;
|
441 |
|
|
}
|
442 |
|
|
|
443 |
|
|
void
|
444 |
|
|
cyg_mcf52xx_i2c_stop(const cyg_i2c_device* dev)
|
445 |
|
|
{
|
446 |
|
|
cyg_mcf52xx_i2c_extra* extra = (cyg_mcf52xx_i2c_extra*)dev->i2c_bus->i2c_extra;
|
447 |
|
|
mcf52xx_i2c_stopit(extra);
|
448 |
|
|
}
|
449 |
|
|
|
450 |
|
|
#endif // defined(CYGHWR_DEVS_I2C_MCF52xx_MULTIPLE_BUSES) || defined(HAL_MCF52xx_I2C_SINGLETON_BASE)
|
451 |
|
|
//---------------------------------------------------------------------------
|
452 |
|
|
// EOF i2c_mcf52xx.c
|