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#ifndef CYGONCE_CORTEXM_STM32_SERIAL_H
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#define CYGONCE_CORTEXM_STM32_SERIAL_H
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// ====================================================================
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//
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// stm32_serial.h
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//
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// Device I/O - Description of ST STM32 serial hardware
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//
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// ====================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2008 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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// ====================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Date: 2008-09-10
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// Purpose: Internal interfaces for serial I/O drivers
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// Description:
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//
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//####DESCRIPTIONEND####
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//
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// ====================================================================
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#include <cyg/hal/hal_io.h> // Register definitions
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// ====================================================================
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// Translate system stop bit selector into control register bits.
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static cyg_uint32 select_stop_bits[] = {
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CYGHWR_HAL_STM32_UART_CR2_STOP_0_5, // 0.5 stop bits
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CYGHWR_HAL_STM32_UART_CR2_STOP_1, // 1 stop bit
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CYGHWR_HAL_STM32_UART_CR2_STOP_1_5, // 1.5 stop bit
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CYGHWR_HAL_STM32_UART_CR2_STOP_2 // 2 stop bit
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};
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// Translate system parity selector into local values.
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static cyg_uint32 select_parity[] = {
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0, // No parity
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CYGHWR_HAL_STM32_UART_CR1_PCE|CYGHWR_HAL_STM32_UART_CR1_PS_EVEN, // Even parity
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CYGHWR_HAL_STM32_UART_CR1_PCE|CYGHWR_HAL_STM32_UART_CR1_PS_ODD, // Odd parity
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0, // Mark (1) parity -- not supported
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};
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// ====================================================================
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// Translate system baud selector into direct baud rate value. This is
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// then used to calculate the clock divisor from the PCLK clock.
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static cyg_int32 select_baud[] = {
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0, // Unused
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50, // 50
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75, // 75
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110, // 110
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0, // 134.5
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150, // 150
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200, // 200
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300, // 300
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600, // 600
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1200, // 1200
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1800, // 1800
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2400, // 2400
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3600, // 3600
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4800, // 4800
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7200, // 7200
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9600, // 9600
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14400, // 14400
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19200, // 19200
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38400, // 38400
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57600, // 57600
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115200, // 115200
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230400, // 230400
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};
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// ====================================================================
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#endif // CYGONCE_CORTEXM_STM32_SERIAL_H
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