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skrzyp |
//==========================================================================
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//
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// ser_esci.c
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//
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// Freescale sSCI Serial I/O Interface Module (interrupt driven)
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Ilija Koco <ilijak@siva.com.mk>
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// Contributors:
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// Date: 2006-04-20
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// Purpose: eSCI Serial I/O module (interrupt driven version)
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// Description:
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//
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//
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//####DESCRIPTIONEND####
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//==========================================================================
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#include <pkgconf/io_serial.h>
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#include <pkgconf/io.h>
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#include <cyg/io/io.h>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/hal/hal_arbiter.h>
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#include <cyg/hal/var_io.h>
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#include <cyg/io/devtab.h>
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#include <cyg/infra/diag.h>
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#include <cyg/io/serial.h>
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#include <cyg/devs/ser_esci.h>
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// Only build this driver for if ESCI is needed.
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#ifdef CYGPKG_IO_SERIAL_FREESCALE_ESCI
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typedef struct esci_serial_info {
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CYG_ADDRWORD esci_base; // Base address of the esci port
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CYG_WORD interrupt_num; // INTC interrupt vector
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cyg_priority_t interrupt_priority; // INTC interupt priority
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cyg_interrupt interrupt_obj; // Interrupt object
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cyg_handle_t interrupt_handle; // Interrupt handle
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} esci_serial_info;
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static bool esci_serial_init(struct cyg_devtab_entry * tab);
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static bool esci_serial_putc(serial_channel * chan, unsigned char c);
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static Cyg_ErrNo esci_serial_lookup(struct cyg_devtab_entry ** tab,
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struct cyg_devtab_entry * sub_tab,
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const char * name);
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static unsigned char esci_serial_getc(serial_channel *chan);
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static Cyg_ErrNo esci_serial_set_config(serial_channel *chan, cyg_uint32 key,
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const void *xbuf, cyg_uint32 *len);
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static void esci_serial_start_xmit(serial_channel *chan);
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static void esci_serial_stop_xmit(serial_channel *chan);
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// Interrupt servers
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static cyg_uint32 esci_serial_ISR(cyg_vector_t vector, cyg_addrword_t data);
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static void esci_serial_DSR(cyg_vector_t vector, cyg_ucount32 count,
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cyg_addrword_t data);
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static SERIAL_FUNS(esci_serial_funs,
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esci_serial_putc,
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esci_serial_getc,
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esci_serial_set_config,
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esci_serial_start_xmit,
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esci_serial_stop_xmit);
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// Available baud rates
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static unsigned short select_baud[] = {
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0, // Unused
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0, // 50 bps unsupported
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0, // 75 bps unsupported
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0, // 110 bps unsupported
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0, // 134_5 bps unsupported
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0, // 150 bps unsupported
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0, // 200 bps unsupported
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FREESCALE_ESCI_BAUD(300), // 300 bps
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FREESCALE_ESCI_BAUD(600), // 600 bps
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FREESCALE_ESCI_BAUD(1200), // 1200 bps
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0, // 1800 bps unsupported
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FREESCALE_ESCI_BAUD(2400), // 2400 bps
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0, // 3600 bps unsupported
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FREESCALE_ESCI_BAUD(4800), // 4800 bps
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0, // 7200 bps unsupported
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FREESCALE_ESCI_BAUD(9600), // 9600 bps
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FREESCALE_ESCI_BAUD(14400), // 14400 bps
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FREESCALE_ESCI_BAUD(19200), // 19200 bps
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FREESCALE_ESCI_BAUD(38400), // 38400 bps
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FREESCALE_ESCI_BAUD(57600), // 57600 bps
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FREESCALE_ESCI_BAUD(115200), // 115200 bps
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};
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#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_A
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static esci_serial_info esci_serial_info0 = {
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esci_base : CYGADDR_IO_SERIAL_FREESCALE_ESCI_A_BASE,
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interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_INT_VECTOR,
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interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_INT_PRIORITY
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};
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#if CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BUFSIZE > 0
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static unsigned char
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esci_serial_out_buf0[CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BUFSIZE];
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static unsigned char
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esci_serial_in_buf0[CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BUFSIZE];
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static
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SERIAL_CHANNEL_USING_INTERRUPTS(
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esci_serial_channel0,
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esci_serial_funs,
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esci_serial_info0,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT,
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&esci_serial_out_buf0[0],
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sizeof(esci_serial_out_buf0),
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&esci_serial_in_buf0[0],
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sizeof(esci_serial_in_buf0));
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#else
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static
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SERIAL_CHANNEL(esci_serial_channel0,
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esci_serial_funs,
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esci_serial_info0,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT);
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#endif
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DEVTAB_ENTRY(esci_serial_io0,
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CYGDAT_IO_SERIAL_FREESCALE_ESCI_A_NAME,
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0, // does not depend on a lower level device driver
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&cyg_io_serial_devio,
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esci_serial_init,
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esci_serial_lookup,
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&esci_serial_channel0);
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#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_ESCI_A
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#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_B
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static esci_serial_info esci_serial_info1 = {
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esci_base : CYGADDR_IO_SERIAL_FREESCALE_ESCI_B_BASE,
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interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_INT_VECTOR,
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interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_INT_PRIORITY
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};
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#if CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BUFSIZE > 0
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static unsigned char
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esci_serial_out_buf1[CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BUFSIZE];
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static unsigned char
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esci_serial_in_buf1[CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BUFSIZE];
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static
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SERIAL_CHANNEL_USING_INTERRUPTS(esci_serial_channel1,
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esci_serial_funs,
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esci_serial_info1,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT,
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&esci_serial_out_buf1[0],
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sizeof(esci_serial_out_buf1),
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&esci_serial_in_buf1[0],
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sizeof(esci_serial_in_buf1));
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#else
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static
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SERIAL_CHANNEL(esci_serial_channel1,
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esci_serial_funs,
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esci_serial_info1,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT);
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#endif
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DEVTAB_ENTRY(esci_serial_io1,
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CYGDAT_IO_SERIAL_FREESCALE_ESCI_B_NAME,
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0, // does not depend on a lower level device driver
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&cyg_io_serial_devio,
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esci_serial_init,
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esci_serial_lookup,
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&esci_serial_channel1);
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#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_ESCI_B
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#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_C
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static esci_serial_info esci_serial_info2 = {
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esci_base : CYGADDR_IO_SERIAL_FREESCALE_ESCI_C_BASE,
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interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_INT_VECTOR,
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interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_INT_PRIORITY
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};
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#if CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BUFSIZE > 0
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static unsigned char
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esci_serial_out_buf2[CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BUFSIZE];
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static unsigned char
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esci_serial_in_buf2[CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BUFSIZE];
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static
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SERIAL_CHANNEL_USING_INTERRUPTS(esci_serial_channel2,
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esci_serial_funs,
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esci_serial_info2,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT,
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&esci_serial_out_buf2[0],
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sizeof(esci_serial_out_buf2),
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&esci_serial_in_buf2[0],
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sizeof(esci_serial_in_buf2));
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#else
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static
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| 241 |
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SERIAL_CHANNEL(esci_serial_channel2,
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esci_serial_funs,
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esci_serial_info2,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT);
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#endif
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DEVTAB_ENTRY(esci_serial_io2,
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| 251 |
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CYGDAT_IO_SERIAL_FREESCALE_ESCI_C_NAME,
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0, // does not depend on a lower level device driver
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&cyg_io_serial_devio,
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esci_serial_init,
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esci_serial_lookup,
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&esci_serial_channel2);
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| 257 |
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#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_ESCI_C
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| 259 |
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#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_D
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static esci_serial_info esci_serial_info3 = {
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esci_base : CYGADDR_IO_SERIAL_FREESCALE_ESCI_D_BASE,
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interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_INT_VECTOR,
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interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_INT_PRIORITY
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};
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| 266 |
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#if CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BUFSIZE > 0
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| 267 |
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static unsigned char
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| 268 |
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esci_serial_out_buf3[CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BUFSIZE];
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| 269 |
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static unsigned char
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| 270 |
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esci_serial_in_buf3[CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BUFSIZE];
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| 271 |
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| 272 |
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static
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| 273 |
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SERIAL_CHANNEL_USING_INTERRUPTS(esci_serial_channel3,
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| 274 |
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esci_serial_funs,
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esci_serial_info3,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT,
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&esci_serial_out_buf3[0],
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| 282 |
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sizeof(esci_serial_out_buf3),
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&esci_serial_in_buf3[0],
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| 284 |
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sizeof(esci_serial_in_buf3));
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| 285 |
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#else
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| 286 |
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static
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| 287 |
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SERIAL_CHANNEL(esci_serial_channel3,
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| 288 |
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esci_serial_funs,
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esci_serial_info3,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_BAUD),
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|
CYG_SERIAL_STOP_DEFAULT,
|
| 292 |
|
|
CYG_SERIAL_PARITY_DEFAULT,
|
| 293 |
|
|
CYG_SERIAL_WORD_LENGTH_DEFAULT,
|
| 294 |
|
|
CYG_SERIAL_FLAGS_DEFAULT);
|
| 295 |
|
|
#endif
|
| 296 |
|
|
DEVTAB_ENTRY(esci_serial_io3,
|
| 297 |
|
|
CYGDAT_IO_SERIAL_FREESCALE_ESCI_D_NAME,
|
| 298 |
|
|
0, // does not depend on a lower level device driver
|
| 299 |
|
|
&cyg_io_serial_devio,
|
| 300 |
|
|
esci_serial_init,
|
| 301 |
|
|
esci_serial_lookup,
|
| 302 |
|
|
&esci_serial_channel3);
|
| 303 |
|
|
#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_ESCI_D
|
| 304 |
|
|
|
| 305 |
|
|
//----------------------------------------------------------------------------
|
| 306 |
|
|
// Internal function to actually configure the hardware to desired
|
| 307 |
|
|
// baud rate, etc.
|
| 308 |
|
|
//----------------------------------------------------------------------------
|
| 309 |
|
|
static bool
|
| 310 |
|
|
esci_serial_config_port(serial_channel * chan, cyg_serial_info_t * new_config,
|
| 311 |
|
|
bool init)
|
| 312 |
|
|
{
|
| 313 |
|
|
esci_serial_info * esci_chan = (esci_serial_info *)(chan->dev_priv);
|
| 314 |
|
|
cyg_addrword_t esci_base = esci_chan->esci_base;
|
| 315 |
|
|
cyg_uint16 baud_rate = ((new_config->baud >= 0) &&
|
| 316 |
|
|
(new_config->baud < (sizeof(select_baud)/
|
| 317 |
|
|
sizeof(select_baud[0]))))
|
| 318 |
|
|
? select_baud[new_config->baud] : 0;
|
| 319 |
|
|
|
| 320 |
|
|
cyg_uint16 esci_cr12=0, esci_cr12_old;
|
| 321 |
|
|
|
| 322 |
|
|
HAL_WRITE_UINT8(FREESCALE_ESCI_CR3(esci_base), 0);
|
| 323 |
|
|
HAL_WRITE_UINT16(FREESCALE_ESCI_LINCTRL(esci_base), 0);
|
| 324 |
|
|
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(esci_base), 0);
|
| 325 |
|
|
|
| 326 |
|
|
if(!baud_rate) return false; // Invalid baud rate selected
|
| 327 |
|
|
|
| 328 |
|
|
switch(new_config->word_length){
|
| 329 |
|
|
case 8: break;
|
| 330 |
|
|
default: return false;
|
| 331 |
|
|
}
|
| 332 |
|
|
|
| 333 |
|
|
switch(new_config->parity){
|
| 334 |
|
|
case CYGNUM_SERIAL_PARITY_ODD:
|
| 335 |
|
|
esci_cr12 |= FREESCALE_ESCI_CR12_PT;
|
| 336 |
|
|
case CYGNUM_SERIAL_PARITY_EVEN:
|
| 337 |
|
|
esci_cr12 |= FREESCALE_ESCI_CR12_PE;
|
| 338 |
|
|
case CYGNUM_SERIAL_PARITY_NONE:
|
| 339 |
|
|
break;
|
| 340 |
|
|
default: return false;
|
| 341 |
|
|
}
|
| 342 |
|
|
|
| 343 |
|
|
if(new_config->stop!=CYGNUM_SERIAL_STOP_1) return false;
|
| 344 |
|
|
|
| 345 |
|
|
// Enable the device
|
| 346 |
|
|
esci_cr12 |= FREESCALE_ESCI_CR12_TE | FREESCALE_ESCI_CR12_RE;
|
| 347 |
|
|
|
| 348 |
|
|
if(init){ // Enable the receiver interrupt
|
| 349 |
|
|
esci_cr12 |= FREESCALE_ESCI_CR12_RIE;
|
| 350 |
|
|
}else{ // Restore the old interrupt state
|
| 351 |
|
|
HAL_READ_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12_old);
|
| 352 |
|
|
esci_cr12 |= (esci_cr12_old & FREESCALE_ESCI_CR12_RIE);
|
| 353 |
|
|
}
|
| 354 |
|
|
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12);
|
| 355 |
|
|
|
| 356 |
|
|
if(new_config != &chan->config)
|
| 357 |
|
|
chan->config = *new_config;
|
| 358 |
|
|
|
| 359 |
|
|
return true;
|
| 360 |
|
|
}
|
| 361 |
|
|
|
| 362 |
|
|
//--------------------------------------------------------------
|
| 363 |
|
|
// Function to initialize the device. Called at bootstrap time.
|
| 364 |
|
|
//--------------------------------------------------------------
|
| 365 |
|
|
static bool
|
| 366 |
|
|
esci_serial_init(struct cyg_devtab_entry * tab)
|
| 367 |
|
|
{
|
| 368 |
|
|
serial_channel * chan = (serial_channel *)tab->priv;
|
| 369 |
|
|
esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv;
|
| 370 |
|
|
|
| 371 |
|
|
// Really only required for interrupt driven devices
|
| 372 |
|
|
(chan->callbacks->serial_init)(chan);
|
| 373 |
|
|
if(chan->out_cbuf.len != 0){
|
| 374 |
|
|
cyg_drv_interrupt_create(esci_chan->interrupt_num,
|
| 375 |
|
|
esci_chan->interrupt_priority,
|
| 376 |
|
|
// Data item passed to interrupt handler
|
| 377 |
|
|
(cyg_addrword_t)chan,
|
| 378 |
|
|
esci_serial_ISR,
|
| 379 |
|
|
esci_serial_DSR,
|
| 380 |
|
|
&esci_chan->interrupt_handle,
|
| 381 |
|
|
&esci_chan->interrupt_obj);
|
| 382 |
|
|
|
| 383 |
|
|
cyg_drv_interrupt_attach(esci_chan->interrupt_handle);
|
| 384 |
|
|
cyg_drv_interrupt_unmask(esci_chan->interrupt_num);
|
| 385 |
|
|
}
|
| 386 |
|
|
return esci_serial_config_port(chan, &chan->config, true);
|
| 387 |
|
|
}
|
| 388 |
|
|
|
| 389 |
|
|
//----------------------------------------------------------------------
|
| 390 |
|
|
// This routine is called when the device is "looked" up (i.e. attached)
|
| 391 |
|
|
//----------------------------------------------------------------------
|
| 392 |
|
|
static Cyg_ErrNo
|
| 393 |
|
|
esci_serial_lookup(struct cyg_devtab_entry ** tab,
|
| 394 |
|
|
struct cyg_devtab_entry * sub_tab, const char * name)
|
| 395 |
|
|
{
|
| 396 |
|
|
serial_channel * chan = (serial_channel *)(*tab)->priv;
|
| 397 |
|
|
// Really only required for interrupt driven devices
|
| 398 |
|
|
(chan->callbacks->serial_init)(chan);
|
| 399 |
|
|
|
| 400 |
|
|
return ENOERR;
|
| 401 |
|
|
}
|
| 402 |
|
|
|
| 403 |
|
|
//-----------------------------------------------------------------
|
| 404 |
|
|
// Send a character to Tx
|
| 405 |
|
|
//-----------------------------------------------------------------
|
| 406 |
|
|
static bool
|
| 407 |
|
|
esci_serial_putc(serial_channel * chan, unsigned char ch_out)
|
| 408 |
|
|
{
|
| 409 |
|
|
esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv;
|
| 410 |
|
|
cyg_addrword_t esci_base = esci_chan->esci_base;
|
| 411 |
|
|
cyg_uint16 esci_sr;
|
| 412 |
|
|
|
| 413 |
|
|
HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr);
|
| 414 |
|
|
if(esci_sr & FREESCALE_ESCI_SR_TDRE){
|
| 415 |
|
|
HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_TDRE);
|
| 416 |
|
|
HAL_WRITE_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_out);
|
| 417 |
|
|
return true;
|
| 418 |
|
|
}else
|
| 419 |
|
|
return false;
|
| 420 |
|
|
}
|
| 421 |
|
|
|
| 422 |
|
|
//---------------------------------------------------------------------
|
| 423 |
|
|
// Fetch a character Rx (for polled operation only)
|
| 424 |
|
|
//---------------------------------------------------------------------
|
| 425 |
|
|
static unsigned char
|
| 426 |
|
|
esci_serial_getc(serial_channel * chan)
|
| 427 |
|
|
{
|
| 428 |
|
|
cyg_uint8 ch_in;
|
| 429 |
|
|
esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv;
|
| 430 |
|
|
cyg_addrword_t esci_base = esci_chan->esci_base;
|
| 431 |
|
|
|
| 432 |
|
|
cyg_uint16 esci_sr;
|
| 433 |
|
|
|
| 434 |
|
|
do{
|
| 435 |
|
|
HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr);
|
| 436 |
|
|
}while(esci_sr & FREESCALE_ESCI_SR_RDRF);
|
| 437 |
|
|
|
| 438 |
|
|
HAL_READ_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_in);
|
| 439 |
|
|
HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_RDRF);
|
| 440 |
|
|
|
| 441 |
|
|
return ch_in;
|
| 442 |
|
|
}
|
| 443 |
|
|
|
| 444 |
|
|
//---------------------------------------------------
|
| 445 |
|
|
// Set up the device characteristics; baud rate, etc.
|
| 446 |
|
|
//---------------------------------------------------
|
| 447 |
|
|
static bool
|
| 448 |
|
|
esci_serial_set_config(serial_channel * chan, cyg_uint32 key,
|
| 449 |
|
|
const void *xbuf, cyg_uint32 * len)
|
| 450 |
|
|
{
|
| 451 |
|
|
switch(key) {
|
| 452 |
|
|
case CYG_IO_SET_CONFIG_SERIAL_INFO:{
|
| 453 |
|
|
cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
|
| 454 |
|
|
if(*len < sizeof(cyg_serial_info_t)) {
|
| 455 |
|
|
return -EINVAL;
|
| 456 |
|
|
}
|
| 457 |
|
|
*len = sizeof(cyg_serial_info_t);
|
| 458 |
|
|
if(true != esci_serial_config_port(chan, config, false))
|
| 459 |
|
|
return -EINVAL;
|
| 460 |
|
|
}
|
| 461 |
|
|
break;
|
| 462 |
|
|
default:
|
| 463 |
|
|
return -EINVAL;
|
| 464 |
|
|
}
|
| 465 |
|
|
return ENOERR;
|
| 466 |
|
|
}
|
| 467 |
|
|
|
| 468 |
|
|
//-------------------------------------
|
| 469 |
|
|
// Enable the transmitter on the device
|
| 470 |
|
|
//-------------------------------------
|
| 471 |
|
|
static void esci_serial_start_xmit(serial_channel * chan)
|
| 472 |
|
|
{
|
| 473 |
|
|
esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv;
|
| 474 |
|
|
cyg_addrword_t esci_base = esci_chan->esci_base;
|
| 475 |
|
|
cyg_uint16 esci_cr12;
|
| 476 |
|
|
|
| 477 |
|
|
HAL_READ_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12);
|
| 478 |
|
|
esci_cr12 |= FREESCALE_ESCI_CR12_TIE;
|
| 479 |
|
|
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12);
|
| 480 |
|
|
}
|
| 481 |
|
|
|
| 482 |
|
|
//--------------------------------------
|
| 483 |
|
|
// Disable the transmitter on the device
|
| 484 |
|
|
//--------------------------------------
|
| 485 |
|
|
static void esci_serial_stop_xmit(serial_channel * chan)
|
| 486 |
|
|
{
|
| 487 |
|
|
esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv;
|
| 488 |
|
|
|
| 489 |
|
|
cyg_addrword_t esci_base = esci_chan->esci_base;
|
| 490 |
|
|
cyg_uint16 esci_cr12;
|
| 491 |
|
|
|
| 492 |
|
|
HAL_READ_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12);
|
| 493 |
|
|
esci_cr12 &= ~FREESCALE_ESCI_CR12_TIE;
|
| 494 |
|
|
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(esci_base), esci_cr12);
|
| 495 |
|
|
}
|
| 496 |
|
|
|
| 497 |
|
|
//-----------------------------------------
|
| 498 |
|
|
// The low level interrupt handler
|
| 499 |
|
|
//-----------------------------------------
|
| 500 |
|
|
static
|
| 501 |
|
|
cyg_uint32 esci_serial_ISR(cyg_vector_t vector, cyg_addrword_t data)
|
| 502 |
|
|
{
|
| 503 |
|
|
serial_channel * chan = (serial_channel *)data;
|
| 504 |
|
|
esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv;
|
| 505 |
|
|
|
| 506 |
|
|
cyg_drv_interrupt_mask(esci_chan->interrupt_num);
|
| 507 |
|
|
cyg_drv_interrupt_acknowledge(esci_chan->interrupt_num);
|
| 508 |
|
|
|
| 509 |
|
|
return CYG_ISR_CALL_DSR; // cause the DSR to run
|
| 510 |
|
|
}
|
| 511 |
|
|
|
| 512 |
|
|
|
| 513 |
|
|
//------------------------------------------
|
| 514 |
|
|
// The high level interrupt handler
|
| 515 |
|
|
//------------------------------------------
|
| 516 |
|
|
|
| 517 |
|
|
#define FREESCALE_ESCI_SR_ERRORS (FREESCALE_ESCI_SR_OR | \
|
| 518 |
|
|
FREESCALE_ESCI_SR_NF | \
|
| 519 |
|
|
FREESCALE_ESCI_SR_FE | \
|
| 520 |
|
|
FREESCALE_ESCI_SR_PF)
|
| 521 |
|
|
|
| 522 |
|
|
static void
|
| 523 |
|
|
esci_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
|
| 524 |
|
|
{
|
| 525 |
|
|
serial_channel * chan = (serial_channel *)data;
|
| 526 |
|
|
esci_serial_info * esci_chan = (esci_serial_info *)chan->dev_priv;
|
| 527 |
|
|
cyg_addrword_t esci_base = esci_chan->esci_base;
|
| 528 |
|
|
cyg_uint16 esci_sr;
|
| 529 |
|
|
cyg_uint8 esci_dr;
|
| 530 |
|
|
|
| 531 |
|
|
HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr);
|
| 532 |
|
|
if(esci_sr & FREESCALE_ESCI_SR_RDRF){ // Receiver full
|
| 533 |
|
|
HAL_READ_UINT8(FREESCALE_ESCI_DRL(esci_base), esci_dr);
|
| 534 |
|
|
HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_RDRF);
|
| 535 |
|
|
if(esci_sr &= (cyg_uint16)FREESCALE_ESCI_SR_ERRORS){
|
| 536 |
|
|
HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr);
|
| 537 |
|
|
}else{
|
| 538 |
|
|
(chan->callbacks->rcv_char)(chan, (cyg_uint8)esci_dr);
|
| 539 |
|
|
}
|
| 540 |
|
|
}else if(esci_sr & FREESCALE_ESCI_SR_TDRE){ //Transmitter empty
|
| 541 |
|
|
(chan->callbacks->xmt_char)(chan);
|
| 542 |
|
|
}
|
| 543 |
|
|
|
| 544 |
|
|
cyg_drv_interrupt_unmask(esci_chan->interrupt_num);
|
| 545 |
|
|
}
|
| 546 |
|
|
|
| 547 |
|
|
#endif // CYGPKG_IO_SERIAL_FREESCALE_ESCI_[ABCD]
|
| 548 |
|
|
// EOF ser_esci.c
|
